1.

A counter that has a modulus of 64 should use a minimum of

a. Six flip-flops b. Six J-K flip-flops
c. Six D-flip-flops d. 64 flip-flops
2. How many stable states does a flip-flop have?

a. 2 b. 3
c. 4 d. 5
3. An inverter is wired between J and K inputs of the J-K flip-flop and J-input is treated as
the input to the flip-flop. In that case, what will be the logic status of the true output
when clocked for J = 1?
a. 1 b. 3
c. 5 d. 7
4. A Schmitt NAND gate is used as an inverter and the two trip points are 1.5 V and 2.7 V. If
the output is initially HIGH, it will go to LOW state for input voltage greater than X (in
volts). Find X in this case.
a. 1.7 b. 2.7
c. 3.3 d. 4.3
5. The following figures (a) and (b), respectively, show the circuit symbol and incomplete
function table of a D-flip-flop. Fill in the missing places marked as (i), (ii), (iii), and (iv).

(a)
 PR C1 Clk D Q Q̅
(i) 1 . . 1 0
1 0 . . 0 1
0 (ii) . . Unstable
1 (iii) ↑ 1 1 0
1 1 ↑ 0 0 (iv)
(b)

a. (0, 0, 1, 1) b. (1, 0, 1, 0)
c. (1, 1, 0, 1) d. (1, 1, 0, 0)
6. Refer to the circuit symbol of the flip-flop shown in the following figure. What will be the
logic status of the Q-output on the rising edge of the clock pulse for Pr = C1 = 0, J = 0 and
K = 1.

a. 1 b. 2
c. 3 d. 4
7. What is least modulus a four-bit binary counter can be configured for?
a. 3 b. 5
c. 7 d. 9
8. Determine the maximum usable clock frequency in MHz of a Modulo-7 binary ripple
counter if the propagation delay specifications of the flip-flops used are t PLH = 20 ns, tPHL =
25 ns.
a. 11.33 b. 13.33
c. 11.55 d. 13.55
9. It is desired to design a binary ripple counter capable of counting the number of items
passing on a conveyor belt. Each time an item passes a given point, a pulse is generated
that can be used as a clock input. If the maximum number of items to be counted is
6000, determine the number of flip-flops required.
a. 11 b. 13
c. 15 d. 17
10. A bit sequence 0010 is entered (right-most bit first) into a 4-bit parallel out shift register,
which is initially clear. What are the Q-output after two clock pulses?
a. 1000 b. 1001
c. 1010 d. 1111
11. A bidirectional 4-bit shift register is storing the nibble 1101. Its RIGHT/LEFT input is
HIGH. The nibble 1011 is waiting to be entered on the serial data-input line. After three
clock pulses, the shift register is storing?
a. 0001 b. 0011
c. 0111 d. 1111
12. A decade counter is also referred to as
a. BCD counter b. BCD-Decade counter
c. Modulo-10 counter d. None of these
13. PRESET and CLEAR inputs are referred to as
a. Synchronous inputs b. serial inputs
c. load inputs d. asynchronous inputs
14. In a negative edge-triggered D-type flip-flop, the data at D-input is transferred to the Q-
output during
a. LOW-to-HIGH transition of the clock pulses b. HIGH-to-LOW edge of the clock pulse
c. HIGH time of the clock pulse d. LOW time of the clock pulse
15. Two of the four synchronous modes of operation in a clocked J-K flip-flop are SET and
HOLD. The other two are
a. PRESET and CLEAR b. PRESET and RESET
c. RESET and TOGGLE d. PRESET and TOGGLE
16. Mark the incorrect statement.
a. D-flip-flop is same as D-type latch.
b. When the PRESET input of a certain flip-flop is active, it sets the flip-flop to logic ‘1’
state irrespective of status of synchronous inputs.
 c. PRESET and CLEAR inputs should not be active simultaneously.
d. A J-K flip-flop with active LOW J and K inputs will function like a toggle flip-flop for J =
K = 0.
17. A MOD-32 synchronous counter would require
a. Six flip-flops and three AND gates b. five flip-flops
c. five flip-flops and three AND gates d. none of these
18. Mark the false statement:
a. Ring counter is a synchronous counter.
b. Johnson counter is a synchronous counter.
c. The output of a ring counter is always a square wave.
d. The decoding circuitry of a Johnson counter is always simpler than that of a ring
counter.
19. A four-bit presettable DOWN counter initially loaded with 0101 will divide the input
clock frequency by
a. 16 b. 5
c. 11 d. 10
20. A cascade arrangement of four stages of BCD counters will be used to count a maximum
of
a. 1111 pulses b. 1111111111111111 pulses
c. 1001100110011001 pulses d. 9999 pulses
21. The output waveform for the given circuit and the input waveforms is given as
 a.

b.

c.

d.

22. Which among the following is not a mode of flip-flop representation?

a. Characteristic equations b. Excitation tables
c. Finite state machines (FSM) d. Variable entered mapping (VEM)
23. The following circuit performs what function
 a. Extends the rising edge of input by 2 clock pulses.
b. Extends the falling edge of input by 2 clock pulses.
c. Reproduces the input waveform at output.
d. None of the above.
24. Of what modulus, Johnson counters can be constructed from an octal D-type flip-flop IC?
a. 5 b. 10
c. 16 d. 64
25. A five-bit Johnson counter is in cascade with a five-bit ring counter. What will be the
modulus of resultant counter circuit?
a. 20 b. 30
c. 40 d. 50
26. Of what modulus ring counters can be constructed from an octal D-type flip-flop IC?
a. 2 b. 4
c. 6 d. 8
27. What can be the possible range of modulus of a five-bit binary counter?
a. 12-32 b. 13-32
c. 14-32 d. 15-32
28. An eight-bit binary ripple UP counter with a modulus of 256 is holding a count
01111111. What will be the count after 135 clock cycles?
a. 00000110 b. 00000111
c. 00001110 d. 00001111
29. The flip-flops used in a four-bit binary ripple counter have a HIGH-to-LOW and LOW-to-
HIGH propagation delay of 25 ns and 10 ns, respectively. Determine the maximum
usable clock frequency in MHz of this counter.
a. 25 ns b. 50 ns
 c. 75 ns d. 100 ns
30. A four-bit shift counter is clocked by a 10 MHz clock signal. Determine duty cycle of the
waveform appearing at the output of the output flip-flop.
a. 20 b. 30
c. 40 d. 50
31. A 100 KHz clock signal is applied to a J-K flip-flop. J = K = 1. If the J and K are active-LOW
inputs, what would be the frequency of true output in KHz assuming true output is
initially in logic ‘0’ state?
a. 0 b. 2
c. 4 d. 5
32. A 0 to 6 counter consists of three flip-flops and a combination circuit of two-input
gate(s). The combination circuit consist of
a. One AND gate b. One OR gate
c. one AND gate and one OR gate d. two AND gates
33. A four-bit ripple counter and a four-bit synchronous counter are made using flip-flops
having a propagation delay of 10 ns each. If the worst case delay in the ripple counter
and the synchronous counter be R and S, respectively, then
a. R = 10 ns, S = 40 ns b. R = 40 ns, S = 10 ns
c. R = 10 ns, S = 30 ns d. R = 30 ns, S = 40 ns
34. A master-slave flip-flop has the characteristic that
a. Change in the input is immediately reflected in the output
b. Change in the output occurs when the state of the master is affected
c. Change in the output occurs when the state of the slave is affected
d. Both the master and the slave states are affected at the same time
35. Choose the correct one from among the alternatives A, B, C and D after matching an
item from Group 1 with the most appropriate item in Group 2.

Group 1 Group 2
P. Shift register 1. Frequency division
Q. Counter 2. Addressing in memory chips
R. Decoder 3. Serial-to-parallel data conversion

a. P – 3, Q – 2, R – 1 b. P – 3, Q – 1, R – 2
c. P – 2, Q – 1, R – 3 d. P – 1, Q – 2, R – 2
36. The present output Qn of an edge-triggered J-K flip-flop is at logic 0. If J = 1, then Qn+1
a. Cannot be determined b. will be logic 0
 c. will be logic 1 d. will race around
37. The following figure shows a ripple counter using positive edge-triggered flip-flops. If the
present state of the counter is Q2Q1Q0 = 011, then its next state (Q2Q1Q0) will be

a. 010 b. 100
c. 111 d. 101
38. Two D-flip-flops, as shown in the following figure, are to be connected as a synchronous
counter that goes through the following Q1Q0 sequence 00 → 01→ 11 → 10 → 00 → …
The inputs D0 and D1, respectively, should be connected as

a. Q̅1 and Q0 b. Q̅0 and Q1

c. Q̅1Q0 and Q̅1Q0 d. Q̅1Q̅0 and Q1Q0
39. The following binary values were applied to the X and Y inputs of the NAND latch as
shown in the following figure in the sequence indicated below:
X = 0, Y = 0; X = 1, Y = 1
The corresponding stable P, Q outputs will be
 a. P = 1, Q = 0; P = 1, Q = 0; P = 1, Q = 0 or P = 0, Q = 1
b. P = 1, Q = 0; P = 0, Q = 1; P = 0, Q = 1; P = 0, Q = 1
c. P = 1, Q = 0; P = 1, Q = 1; P = 1, Q = 0 or P = 0, Q = 1
d. P = 1, Q = 0; P = 1, Q = 1; P = 1, Q = 1
40. For the circuit shown in the following figure, the counter state Q 1 Q0 follows the
sequence

a. 00, 01, 10, 11, 00, … b. 00, 01, 10, 00, 01, …
c. 00, 01, 11, 00, 01, … d. 00, 10, 11, 00, 10, …
41. Assuming that all flip-flops are in reset conditions initially, the count sequence observed
at QA in the circuit shown in the following figure is
 a. 0010111 … b. 0001011 …
c. 0101111 … d. 0110100 …
42. Five J-K flip-flops are cascaded to form the circuit shown in the figure. Clock pulses at a
frequency of 1 MHz are applied as shown. The frequency (in kHz) of the waveform at Q 3
is……

a. 52.5 b. 62.5
c. 52.2 d. 62.2
43. The circuit shown in the figure is a
 a. Toggle flip-flop b. JK flip-flop
c. SR latch d. Master-slave D flip-flop
44. A mod-n counter using a synchronous binary up-counter with synchronous clear input is
shown in the figure. The value of n is ……….

a. 2 b. 4
c. 6 d. 8
45. The figure shows a binary counter with synchronous clear input. With the decoding logic
shown, the counter works as a
 a. Mod – 2 counter b. mod – 4 counter
c. mod – 5 counter d. mod – 6 counter
46. For the circuit shown in the figure, the delay of the bubbled NAND gate is 2 ns and that
of the counter is assumed to be zero.

a. mod-5 counter b. mod-6 counter

c. mod-7 counter d. mod-8 counter
47. A 4-bit shift register circuit configured for right-shift operation, i.e. D in → A, A → B, B →
C, C → D, is shown. If the present state of the shift register is ABCD = 1101, the number
of clock cycles required to reach the state ABCD = 1111 is ……….
 a. 10.0 b. 12.0
c. 14.0 d. 16.0
48. ………. has maximum fan-out capacity.
a. MOS b. CMOS
c. ECL d. RTL
49. A charge coupled device has
a. Low density b. low cost per bit
c. high cost per bit d. None of the above

50. Generally ………. Flip-flops are used in shift registers.

a. D b. Master Slave
c. SR d. JK
51. ………. Flip-flop does not have race problem.
a. D b. SR
c. JK d. Master Slave
52. In which of the following the power dissipation is the lowest?
a. ECL b. MOS
c. TTL d. None of these
53. For a TTL gate the recommended fan-out is
a. 9 b. 10
c. 12 d. 8
54. Which of the following is the fastest unsaturated logic gate?
a. RTL b. HTL
c. TTL d. ECL
55. The current logging takes place in which of the following?
a. TTL b. HTL
c. DCTL d. RTL
56. ……….. logic is the fastest.
a. CMOS b. LSI
c. TTL d. ECL
57. Current Mode Logic (CML) is same as
a. LSI b. ECL
c. TTL d. CMOS
58. In a saturated bipolar logic circuit, transistor operate
a. In deep cut-off b. over active region
c. in saturation d. just short of saturation
59. Saturated logic circuits have inherently
a. Short saturation delay time b. low switching speed
c. higher power dissipation d. lower noise immunity
60. The chief advantage of Schotty TTL logic family is its least
a. Power dissipation b. propagation delay
c. fan-in d. noise immunity
61. The main advantage claimed for ECL family of logic gates is its
a. Very large fan-in b. use of negative power supply voltage
c. extremely low propagation times d. least power dissipation
62. The most obvious identifying feature of a TTL gate is its
a. Large fan-out b. high power dissipation
c. interconnected transistors d. multiemetter input transistor
63. A unique operating feature of ECL circuit is its
a. Very high speed b. high power dissipation
c. series base resistor d. compatibility with other logic series
64. The fan-in a logic gate refers to the number of
a. Input devices that can be connected b. input terminals
c. output terminals d. circuits output can drive
65. If three input of full adder are A, B and C, then what will be the expression of carry
obtained on its output?
a. Cout = AB̅ + A̅C + BC̅ b. Cout = ABC + ABC
c. Cout = (A +B). (A + C). (B + C) d. Cout = AB + AC + BC