5 4 3 2 1

PUSH-BUTTON BYPASS CAPACITORS LCD BIAS and CHARGE PUMP CAPACITORS OUTPUT LEDS TAMPER DETECTION UMI & RF MC1323x-IPB CONNECTORS
D2
R213 VPWR
WP7104LSRD J4
R203 10K VDD VDDA SAR_VDDA VDD 390.0 C A R210 10K 1 J201
USER_BTN KWH_LED TAMPER1

VREFH

VCAP1
VDD

VREFL
DNP

VLL1

VLL2

VLL3
2 1 2 SPI1_MISO
R200 0
3 4 SPI1_MOSI

2
D1 GND HDR 1X2 5 6 SPI1_SCK
C207 C209 C13 C8 C214 C213 C212 C204 C205 C203 C202 R216 C200 GND
WP7104LSRD DNP 7 8 UMI_SS
390.0 C A 9 10
KVARH_LED VDD UMI_INT UMI_RST
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF J3 0.1UF
R214 10K
TAMPER2 1

VCAP2
SW1 2 HDR_2X5
TL3301AF160QG D3 GND DNP
R204
GND GND GND GND GND GND GND GND GND HSMS-C170
2.0K C A GND HDR 1X2 VPWR
Place close to Place close to Place close to Place close Place close Place close USER_LED VDD J200
Place close to LCD bias and charge pump pins DNP
VDD pins VDDA pin SAR_VDDA pin to VBAT pin to VREFH pin to VREFL pin C201 0.1UF
Max current 700nA @3.3V when tamper inactive. 1 2 GND
3 4
5 6 SCI3_TX
3

D R202 R201 D
7 8 SCI3_RX
9 10 4.7K 4.7K
RF_RST
VDD VDDA VDD SAR_VDDA SCI3_RTS 11 12

VREFH
VCAP1
VCAP2
GND GND SCI3_CTS 13 14

VLL1
VLL2
VLL3
15 16

I2C1_SDA
Max current 9.7uA @3.3V when button active

I2C1_SCL
RF_IO 17 18 RF_CTRL
19 20 Populate J200 on the bottom layer

100
below LCD accordingly to the size

10
62

31

99

98
97
96

24

37

61
U7 GND of the MC1322X-IPB board.

1
MMA8491 3-AXIS LOW VOLTAGE TILT SENSOR LCD16 1
CON_2X10

VDD1
VDD2

VCAP1
VCAP2

VLL1
VLL2
VLL3

VREFH
VBAT
VDDA

SAR_VDDA
LCD15 2 PTA0/LCD23 25
3 PTA1/LCD24 XTAL32K 26 Y1
LCD14
PTA2/LCD25 EXTAL32K 32.768KHz
U5 LCD13 4 SWD CONNECTOR PHASE CURRENT SENSING
12
11

PTA3/LCD26 VDD
LCD12 5 R211 4.7M
PTA4/LCD27/LLWU_P15/NMI J2 Connect shunt resistor to the J7 connector
LCD11 6 VDD R19 22

2
NC_12
NC_11

PTA5/LCD28/CMP0OUT SDADP0 as follows:

VDD LCD10 7 30 GND 1 2 SWD_IO Pin 1. Shunt resitor output (blue wire)
C5 0.1UF 1 10 8 PTA6/LCD29/PXBAR_IN0/LLWU_P14 TAMPER0 29 C208 2200PF GND 3 4
MMA_XOUT LCD9 TAMPER1 SWD_CLK C16 Pin 2. Shunt resitor input (yellow wire)
BYP XOUT PTA7/LCD30/PXBAR_OUT0 TAMPER1 28 TAMPER2 5 6
2 9 9 TAMPER2 C215 2200PF GND C7 7 8 J7
GND MMA_YOUT LCD8 0.1UF
VDD YOUT PTB0/LCD31 0.1UF
LCD7 12 9 10 SWD_RESET RES_OUT 1
I2C0_SDA 3 8 MMA_ZOUT LCD6 13 PTB1/LCD32 33 SDADP0 VDD RES_INP 2
SDA ZOUT 14 PTB2/LCD33 SDADP0 34 GND
VBAT voltage divider: LCD5 SDADM0 R215 4.7M HDR 2X5
PTB3/LCD34 SDADM0 GND GND
MMA_EN 4 7 GND ADC input 0.8381 V @ 3.3 V LCD4 15
EN GND 16 PTB4/LCD35 35 HDR 1X2
(wait for 2s to stabilize) LCD3
GND
SCL

LCD2 17 PTB5/LCD36 SDADP1 36 R20 22 DNP

R6 4.7K PTB6/LCD37/CMP1P0 SDADM1 SDADM0
LCD1 18
R207 47K PTB7/LCD38/AFE_CLK 39 SDADP2
IR INTERFACE
VPWR
5
6

MMA8491Q SCI3_RTS 19 SDADP2/CMP1P2 40 SDADM2 R205 10K C17

R5 4.7K 20 PTC0/LCD39/SCI3_RTS/PXBAR_IN1 SDADM2/CMP1P3 VAUX
R206 330K SCI3_CTS
GND SCI3_TX 21 PTC1/LCD40/CMP1P1/SCI3_CTS 42 0.1UF
PTC2/LCD41/SCI3_TXD/PXBAR_OUT1 SDADP3/CMP1P4 R9 1.0K
I2C0_SCL

C4 SCI3_RX 22 43 SCI0_RX
C211 0.1UF 23 PTC3/LCD42/CMP0P3/SCI3_RXD/LLWU_P13 SDADM3/CMP1P5
0.1UF RF_IO

1
PTC4/LCD43 GND
PWR_MSR 44
PTC5/AD0/SCI0_RTS/LLWU_P12 C6 Q1 PLACE CLOSE TO MCU
VBAT_MSR 45
C206 0.1UF PTC6/AD1/SCI0_CTS/QT1 OP506B
GND GND SCI0_TX 46 SCI0_RX is muxed with both 2200PF
Shutdown current: 68nA @ 2.8V PTC7/AD2/SCI0_TXD/PXBAR_OUT2

2
LLWU and AWIC so wakeup
R209 1.6M SCI0_RX 47
PTD0/CMP0P0/SCI0_RXD/PXBAR_IN2/LLWU_P11 VREF
41 feature is supported. PHASE VOLTAGE SENSING
C GND KVARH_LED 48 GND GND C
PTD1/SCI1_TXD/SPI0_SS/PXBAR_OUT3/QT3 VIN
R208 4.7M SPI0_SCK 49 D4
VBAT SPI0_MOSI 50 PTD2/CMP0P1/SCI1_RXD/SPI0_SCK/PXBAR_IN3/LLWU_P10 R10 680
128kB SPI FLASH SPI0_MISO 51 PTD3/SCI1_CTS/SPI0_MOSI SCI0_TX A C
R13 R14 R15 R12
VPWR R212 330K 52 PTD4/AD3/SCI1_RTS/SPI0_MISO/LLWU_P9
VDD EEPROM_SS ~2.65mA @ 3.3V SDADP2 150K 150K 150K 150K
FLASH_SS 53 PTD5/AD4/LPTIM2/QT0/SCI3_CTS TSAL4400
C210 0.1UF 54 PTD6/AD5/LPTIM1/CMP1OUT/SCI3_RTS/LLWU_P8
GND USER_BTN IR diode and phototransistor must GND
8 PTD7/CMP0P4/I2C0_SCL/PXBAR_IN4/SCI3_RXD/LLWU_P7 be placed to have 6.5mm in between C14
R21 Max 22mW power losses and 57.5 V
U2
KWH_LED 55 390 voltage drop per resistor @ 230 V.
C12 0.1UF 56 PTE0/I2C0_SDA/PXBAR_OUT4/SCI3_TXD/CLKOUT 0.015 UF
VCC GND /RESET
SPI1_MOSI 5 2 SPI1_MISO PTE1/RESET
DI/IO0 DO/IO1 I2C1_SDA 57
R17 4.7K I2C1_SCL 58 PTE2/EXTAL1/EWM_IN/PXBAR_IN6/I2C1_SDA ISOLATED PULSE OUTPUT
SPI1_SCK 6 PTE3/XTAL1/EWM_OUT/AFE_CLK/I2C1_SCL
CLK VDD RF_RST 63 U6 GND GND
PTE4/LPTIM0/SCI2_CTS/EWM_IN USE 0.1% 50PPM MELF0204 RESISTORS
R2 10K RF_CTRL 64 SFH6106-4
1 7 R16 820 PTE5/QT3/SCI2_RTS/EWM_OUT/LLWU_P6
CS HOLD SWD_RESET SWD_IO 65
PTE6/CMP0P2/PXBAR_IN5/SCI2_RXD/LLWU_P5/SWD_IO R11 390.0
SWD_CLK 66 2 3
3 PTE7/AD6/PXBAR_OUT5/SCI2_TXD/SWD_CLK SDADM2 Phase voltage scaling:

/PULSE_OUT
WP 325.269 Vpeak equals 211.28mVpeak
GND UMI_INT 67 J1
C2 PTF0/AD7/RTCCLKOUT/QT2/CMP0OUT
FLASH_SS

/PULSE_OUT 68 1 C15
0.1UF 69 PTF1/LCD0/AD8/QT0/PXBAR_OUT6 2 R18
4 W25X10CLSN UMI_RST
PTF2/LCD1/AD9/CMP1OUT/RTCCLKOUT 390
UMI_SS 70 0.015 UF
SPI1_SCK 71 PTF3/LCD2/SPI1_SS/LPTIM1/SCI0_RXD
GND GND PTF4/LCD3/SPI1_SCK/LPTIM0/SCI0_TXD HDR 1X2
SPI1_MISO 72 VPWR 1 4 DNP
SPI1_MOSI 73 PTF5/LCD4/SPI1_MISO/I2C1_SCL/LLWU_P4 Pulse
74 PTF6/LCD5/SPI1_MOSI/I2C1_SDA/LLWU_P3 output GND
VAUX PLACE CLOSE TO MCU
PTF7/LCD6/QT2/CLKOUT
MMA_XOUT 75
4kB SPI EEPROM MMA_YOUT 76 PTG0/LCD7/QT1/LPTIM2
MMA_ZOUT 77 PTG1/LCD8/AD10/LLWU_P2/LPTIM0
VAUX I2C0_SCL 78 PTG2/LCD9/AD11/SPI0_SS/LLWU_P1 LCD DISPLAY U4
ISOLATED RS232 INTERFACE
PTG3/LCD10/SPI0_SCK/I2C0_SCL SFH6106-4
I2C0_SDA 79 DS1
MMA_EN 80 PTG4/LCD11/SPI0_MOSI/I2C0_SDA R7 390.0 2
8 PTG5/LCD12/SPI0_MISO/LPTIM1 LCD1 1 3
U1 COM4 81 1
PTG6/LCD13/LLWU_P0/LPTIM2 LCD2 2
SPI0_MOSI 5 COM3 82 2

SCI1_TX
SI VCC PTG7/LCD14 LCD3 3
R1 10K LCD4 4 3
1 COM2 83 4
CS PTH0/LCD15 LCD5 5
COM1 84 5
PTH1/LCD16 LCD6 6 VPWR
3 2 SPI0_MISO LCD22 85 6
B WP SO PTH2/LCD17 LCD7 7 B
LCD21 86 7
PTH3/LCD18 LCD8 8 1 4
7 LCD20 87 8
HOLD PTH4/LCD19 LCD9 9
LCD19 88 9 D201
PTH5/LCD20 LCD10 10 R3 4.7K
SPI0_SCK 6 89 10 A C
SCK VSS PTH6/SCI1_CTS/SPI1_SS/PXBAR_IN7 LCD11 11
USER_LED 90 11
LCD12 12

A
PTH7/SCI1_RTS/SPI1_SCK/PXBAR_OUT7
EEPROM_SS

CAT25040VE 13 12 MMSD4148T1G J202

C1 4 LCD13 R8
SCI1_RX 91 13 C3
0.1UF PTI0/CMP0P5/SCI1_RXD/PXBAR_IN8/SPI1_MISO/SPI1_MOSI LCD14 14 1.0K 1 2
SCI1_TX 92 14 D200
PTI1/SCI1_TXD/PXBAR_OUT8/SPI1_MOSI/SPI1_MISO LCD15 15 SFH6106-4 3 4
LCD18 93 15 2.2uF MMSD4148T1G
LCD16 16 5 6
SAR_VSSA

PTI2/LCD21 U3
LCD17 94 16
GND GND Standby Current: 2uA LCD17 17 7 8

C
PTI3/LCD22 R4 470
17
VREFL

LCD18 18 SCI1_RX 3 2 9 10
VSSA
VSS1
VSS2
VSS3
VSS4

LCD19 19 18
LCD20 20 19
20 HDR_2X5
LCD21 21
POWER SUPPLY TEST POINTS LCD22 22 21
11
27
59
95

32

38

60

PKM34Z128CLL5 23 22
TP2 TP4 TP3 TP5 TP6 TP1 COM1 Max. 19200 Bd
COM2 24 23 D202
VREFL

COM3 25 24 4 1 C A
COM4 26 25
GND GND GND 26
VPWR VBAT GND VDD VDDA SAR_VDDA PLACE ALL PASSIVES CLOSE TO RESPECTIVE MCU PINS MMSD4148T1G
GND
LCD MODULE

Open J5 to Revisions
monitor BT1 Rev Description Date Designer
85-265V AC-DC SMPS MODULE C216 4.7uF current.
Place close to VDDA A Initial Release June 19, 2012 Martin Mienkina
J5
3.6 V Battery HDR_1X2 pin of the MCU VDDA
JP6 D204 L200 1500uH VBAT Open J8 to monitor B Updated to achieve lower current consumption in standby mode. December 10, 2012 Martin Mienkina
R218 3.0K BT200 D5 L2 1uH
1 VIN A C 1 2 MCU + RTC currents. 1 2
3 MMSD4148T1G
C

-ve2 C Grounded Tamper0, removed R22, changed SW1 component April 23, 2013 Martin Mienkina
4

2
1

U200 1%
GND 1 A C C20 C19 C18
HDR 1X1 MRA4007T3G D203 D6 J8
1
2

2 +ve
D

FB
BP

DNP Route C217 R217 C218 -ve1 BAT54CLT1 HDR_1X2

VDD 1uF 1uF 1uF
2.0K J6 1
Keep >=5mm distance MRA4007T3G ER142503PT R24 23.7K R23 45.3K
Keep spacing between nets and 0.1uF 1% 10uF HDR_1X2 GND
S1
S2
S3
S4

between JP6 and JP3 3

A

GND in this region 40mils or VOUT VPWR GND

1
2

A more. L201 820uH U8 Freescale Semiconductor RCSC A

JP3
1

1 2 1 5 2
5
6
7
8

1
1
2

RV200 VIN VOUT C21 C22 SAR_VDDA 1. maje 1009

C

LNK302DN L1 1uH
S10K250E2 2 765 61 Roznov p. R. Czech republic, Europe
HDR 1X1 GND 1 2
+ C220 + C221 D205 C219 C23 C24 C25 C26 10UF 10UF
R219
2

DNP 4.7uF 4.7uF ES1JL 3 4 C11 C10 C9 This document contains information proprietary to Freescale Semiconductor and shall not be used for
1.6K EN ADJ
JP4 JP2 100UF JP1 JP5 10UF 10UF 10UF 10UF engineering design, procurement or manufacture in whole or in part without the express written permission
HDR 1X1 HDR 1X1 HDR 1X1 HDR 1X1 1uF 1uF 1uF of Freescale Semiconductor.
GND GND
A

SPX3819M5-L ICAP Classification: FCP: ____ FIUO: X PUBI: ____

GND GND Place close to SAR_VDDA Designer: Drawing Title:
GND GND GND GND GND GND GND GND GND GND pin of the MCU GND Martin Mienkina
KM34Z128 1-Ph Power Meter
1

VOUT = 1.65V x [ (R218+R217)/R217] (4.125 V)

Connect phase and neutral to the DNP DNP DNP DNP
Open J6 to power Drawn by: Page Title:
JP6 and JP3 headers, respectively: Martin Mienkina
JP6: Neutral (Terminal case 3, 4) Don't populate AC-DC SMPS if capacitive power supply module is used instead. board from +5V VPWR = 1.235V x [ 1 + R23/R24] (3.5956 V) Power Meter
VIN

JP3: Line input (Shunt resistor Connect input of the external capacitive power supply module to JP4 (Line Input) laboratory power 1% resistors R24=23.7k, R23=45.3k
GND and JP2 (Neutral). Output voltage of the external capacitive power supply module VOUT GND supply. Approved: Size Document Number Rev
wire; Terminal case 1)
must be connected to JP1 (Vout) and JP5 (GND). Pavel Lajsner C SCH-27249 PDF: SPF-27249 C

Date: Friday, November 08, 2013 Sheet 1 of 1

5 4 3 2 1