Performance of Different Topologies for Three Level Inverter

Based on Space Vector Pulse Width Modulation Technique

Zulkifilie Bin Ibrahim, Md. Liton Hossain, Syamim Binti Sanusi, Nik Munaji Bin Nik Mahadi, Ahmad Shukri Abu Hasim
Department of Power Electronics and Drive,
Faculty of Electrical Engineering,
Universiti Teknikal Malaysia Melaka,
Melaka, Malaysia
Email: drzulkifilie@[Link], mlhossaineee@[Link], syamimsanusi@[Link], [Link]@[Link],
asyuk31@[Link]

Keywords: DCLI; CCLI; CHBI; SVPWM; THD. inverter topologies to increase the power delivered to the load
and to improve the quality of the voltage [2]. The most
Abstract common topologies are diode clamped, capacitor clamped
and cascaded h-bridge inverter. In this paper, these three
Multilevel inverters are progressively being used in high- topologies has been modelled, simulated and analysed based
power medium voltage energy control industrial drive on space vector pulse width modulation (SVPWM) technique.
applications due to their superior performance compared to The on-time calculation is based on two level SVPWM
conventional two-level inverters. There are a number of algorithm that is simple and the equations of on-time
topologies applied in recent years. The most widely applied calculation do not change with the position of reference
topologies are Diode Clamped Inverter (DCLI), Capacitor vector like the conventional algorithm. In the space vector
Clamped Inverter (CCLI) and Cascaded H-Bridge Inverter diagram of an m-level inverter, the triangle where the
(CHBI). Three level DCLI requires additional 6 clamping reference vector is positioned is identified as integer ∆n. Any
diodes and CCLI requires 3 clamping capacitors that make switching sequence can be generated with respect to triangle
the system bulky and quite difficult to implement while ∆n, leading to an easiness and flexibility of optimizing the
increasing the number of level. CHBI requires no additional switching sequence. Three level space vector diagram is
diodes or capacitors and it is easy to implement. But it divided into six sector each containing four triangles shown in
requires 2 DC sources that increases the system cost. In this figure 1. Shantanu Chatterjee used 7 switching states for
paper, these three topologies for three level inverter using triangle 1, 4 switching states for triangle 2 and 4 and 5
space vector pulse width modulation (SVPWM) technique switching states for triangle 3 that needed more memory
has been modelled and simulated using space, more computation time and more lookup table [3]. In
MATLAB/SIMULINK and Origin 6.1 for a passive R-L load. this control technique, there have been proposed only four
From the simulation results, CHBI with separate DC source active switching states in each triangle shown in table 1 that
(CHBISEDCS) shows the better performance to the others in required less number of lookup table and computations. This
terms of THD. CHBI using single DC (CHBISDC) source is technique can be used for any m-level inverter without any
also presented and compared with CHBISEDC. CHBISDC significant increase in computations.
shows better performance without significant increase of
THD compared to CHBISEDC. Hence CHBISDC minimizes
the system cost and provides better performance.

1 Introduction
Multilevel inverters has brought attractive interest in high-
power medium voltage industrial drive applications due to
their superior performance compared to conventional two-
level inverters. Harmonic distortion is high for conventional
inverter that reduces the machine’s life time and create
synchronization problem with grid voltage. Due to the
reduction of harmonic distortion of conventional inverter, a
large size of filter is needed that makes the system very bulky.
Hence, a new family of multilevel inverters has developed as
the solution for working with higher voltage levels and lower
harmonic distortion [1]. Harmonic distortion can be reduced
significantly by using suitable topology and control
technique. Rodríguez and Lai discussed several multi-level Figure 1: Space vector diagram for three level inverter

1
 Sector Triangle No. Sequence of Active Vectors In eqn. (4) and eqn. (5), %(0 ≤ % ≤ 360) is the angle of the
0 111-211-221-222 reference vector with respect to x-axis, !(0 ≤ ! ≤ 60) is the
1 100-200-210-211 angle within the sector and (1 ≤ ≤ 6) is its sector
1 operation, int and rem are standard math function of integer
2 100-110-210-211
3 110-210-220-221 and reminder.
0 111-121-221-222 Triangle can be divided into two types for each sector. Type 1
1 110-120-220-221 triangle has its base side at the bottom and type 2 triangle has
2
2 110-120-121-221 its base side at the top. The triangle number ∆. can be
3 010-020-120-121 determined in terms of two integer variables P1 and P2, that
0 111-121-122-222 are dependent on the position of reference vector( , 0 ).
1 010-020-021-121
3
2 010-011-021-121 12 = + (6)
√4
3 011-021-022-122
1 =
0 111-112-122-222
(7)
1 011-012-022-122
4
2 011-012-112-122
3 001-002-012-112 Eqn. (6) signifies the part of the sector between the lines
0 111-112-212-222 5 + √3 = √312 and √36 = √3(12 + 1) . This forms one
1 001-002-102-112 region and Eqn. (7) signifies the part of the sector between the
5
2 001-101-102-112 lines 5 = ℎ. 12 and 5 = ℎ. (12 + 1)[5]. This forms another
3 101-102-202-212 region. Let ( , 0 ) be the coordinates of the reference
0 111-211-212-222 vector with respect to the origin of the rhombus.
1 101-201-202-212
6
2 101-201-211-212 = − 12 +. 51 (8)
3 100-200-201-211
0 = 0 −1 ℎ (9)
Table 1: Switching Sequence of Active Vectors for Three
Level Inverter In eqn. (8) and eqn. (9), ( / 0 ) is the slope of the line
between the origin of the rhombus and the reference vector
2 SVPWM algorithm and it is compared with slope of the diagonal of the rhombus
which is √3 [5].
SVPWM compensates the required volt-seconds using The slope evaluation is done by comparing inequality
discrete switching states and on-times. The classical two-level ( 0 ≤ √3 ) and to determine the small vector VZ and the
space vector pulse width modulation technique can be used
triangle number ∆. . If ( 0 ≤ √3 ) which indicates
for on-time calculation. The space vector diagram is a
hexagon consisting of six sectors. Every sector consists of triangle of type 1 and these triangles are similar to sector 1 of
equilateral triangle of unity side and h (=√3/2) is the height of two-level inverter. The triangle number ∆. is obtained from
a sector [4]. The on-time calculation is same for all sectors. eqn. (10).
The calculation of ON times,
∆. = 12 + 21 (10)

= − (1) If ( 0 > √3 ) which indicates triangle of type 2 and these

triangles are similar to sector 2 of two-level inverter. The
triangle number ∆. is obtained from eqn. (11).
= (2)
∆. = 12 + 21 + 1 (11)
= − − (3)
In eqn. (10) and eqn. (11), ∆ indicates the triangle and n is the
Where Ts = 1/2fs, fs is the switching frequency. For any given triangle number. Hence, ∆. is an integer and signifies nth
reference vector, the sector of operation and its angle within triangle in the sector. Using eqn. (10) and eqn. (11), to
the sector is determined by using Equn. (4) and equn. (5), identify triangle in a sector and the on times are calculated
respectively. using eqns. (1)–(3). The ∆. is formulated to provide a simple
way of arranging the triangle, leading to ease of identification
= +1 (4) and extension to any level. The switching sequences are
shown in table 2 for DCLI and CHBI and table 3 for CCLI.

! = "#$ (5)

2
 Switching States for Phase A
Terminal
Voltage
Sa1 Sa2 Sa3 Sa4

1 1 0 0 Vdc

0 1 1 0 Vdc/2

0 0 1 1 0

Table 2: Switching Sequence of Phase A for DCLI and CHBI

Figure 3.1 Three level diode clamped inverter

Switching States for Phase A
Terminal
Voltage
Sa1 Sa2 Sa3 Sa4

1 1 0 0 Vdc

0 1 1 0 Vdc/2

0 0 1 1 0

Table 3: Switching Sequence of Phase A for CCLI

3 Three different topologies Figure 3.2 Three level capacitor clamped inverter
The concept of multilevel converters has been presented since
1975 [6]. Since Nabea A. proposed the three-level inverter
during the IAS annual conference in 1980, the multilevel
converter has advanced rapidly and has been a hotspot for
high-power applications as a new breed of power converter
option. From previous research, it was shown that the
multilevel converter has better performance than conventional
converters in terms of harmonic distortion [7]. Different
multilevel converter topologies have been proposed during
the last two decades for this purpose [1]. The most three
common topologies for multilevel inverter are capacitor
clamped; diode clamped and cascaded half bridge topologies.
There are 6 (m-2) numbers of diodes required for m level
diode clamped inverter. Three level diode clamped inverter is
shown in figure 3.1. There are 3(m-2) capacitors required for
m level capacitor clamped inverter. Three level capacitor Figure 3.3 Three level cascaded h-bridge inverter
clamped inverter is shown in figure 3.2. With the increase of
level, more number of diode or capacitor are required that
make the system bulky and quite difficult to implement. This
problem is solved by cascaded half bridge multilevel inverter
topology that is free from clamping diodes or capacitors.
Three level cascaded h-bridge inverter is shown in figure 3.3.
But each half bridge requires separate DC source that increase
the system cost. This problem can be solved by using
conventional capacitor paralleled to single DC source. Three
level cascaded h-bridge inverter using single DC source based
on SVPWM is shown in figure 3.4. Hence, cascaded h-bridge
topology using single dc source minimizes the system cost,
make the system easy to implement without significant
reduction of the inverter output performance.
 2

C urrent ( A )
1
0
-1
-2
0 2000 4000 6000 8000 10000
Time (ms)
Figure 3.4 Complete simulation block diagram for three Figure 4.3: Measurement of three phase current for
level cascaded h-bridge inverter based on SVPWM CHBISEDCS

4 Result and discussion 2

C urrent ( A )
Simulations are performed for these three topologies based on 1
SVPWM by using MATLAB/Simulink and Origin 6.1. The
measurements of current THD are 3.96%, 2.89% and 2.69% 0
for DCLI, CCLI and CHBI respectively. CHBI shows the best
performance to the others in terms of current HD shown in -1
figure 4.1. Fundamental harmonic distortion is always 100%
that has been skipped due to simplicity of graphical -2
presentation. The measurements of voltage THD are 28.11%,
27.97% and 27.57% for DCLI, CCLI and CHBI respectively. 0 2000 4000 6000 8000 10000
Time (ms)
Figure 4.4: Measurement of three phase current for
1.0 CHBISDC
DCLI
0.8 CCLI
CHBI
HD( %)

0.6

0.4

0.2

0.0
2 4 6 8 10 12 14 16 18 20
Harmonic Order
Figure 4.1: Measurement of current HD for three topologies

Figure 4.5: Measurement of current THD for CHBISEDCS

1.5
DCLI
CCLI
1.0 CHBI
HD( %)

0.5

0.0

2 4 6 8 10 12 14 16 18 20
Harmonic Order

Figure 4.2: Measurement of voltage HD for three topologies Figure 4.6: Measurement of current THD for CHBISDC