OPA

847
OPA847

[Link] SBOS251E – JULY 2002 – REVISED DECEMBER 2008

Wideband, Ultra-Low Noise, Voltage-Feedback

OPERATIONAL AMPLIFIER with Shutdown

FEATURES DESCRIPTION
● HIGH GAIN BANDWIDTH: 3.9GHz The OPA847 combines very high gain bandwidth and large
● LOW INPUT VOLTAGE NOISE: 0.85nV/ √Hz signal performance with an ultra-low input noise voltage
● VERY LOW DISTORTION: –105dBc (5MHz) (0.85nV/√Hz) while using only 18mA supply current. Where
● HIGH SLEW RATE: 950V/µs power saving is critical, the OPA847 also includes an op-
● HIGH DC ACCURACY: VIO < ±100µV tional power shutdown pin that, when pulled low, disables the
amplifier and decreases the supply current to < 1% of the
● LOW SUPPLY CURRENT: 18.1mA
powered-up value. This optional feature may be left discon-
● LOW SHUTDOWN POWER: 2mW
nected to ensure normal amplifier operation when no power-
● STABLE FOR GAINS ≥ 12
down is required.
The combination of very low input voltage and current noise,
APPLICATIONS along with a 3.9GHz gain bandwidth product, make the
● HIGH DYNAMIC RANGE ADC PREAMPS OPA847 an ideal amplifier for wideband transimpedance
applications. As a voltage gain stage, the OPA847 is opti-
● LOW NOISE, WIDEBAND, TRANSIMPEDANCE
mized for a flat frequency response at a gain of +20V/V and
AMPLIFIERS
is stable down to gains as low as +12V/V. New external
● WIDEBAND, HIGH GAIN AMPLIFIERS compensation techniques allow the OPA847 to be used at
● LOW NOISE DIFFERENTIAL RECEIVERS any inverting gain with excellent frequency response control.
● ULTRASOUND CHANNEL AMPLIFIERS Using this technique in a differential Analog-to-Digital Con-
● IMPROVED UPGRADE FOR THE OPA687, verter (ADC) interface application, shown below, can deliver
CLC425, AND LMH6624 one of the highest dynamic-range interfaces available.

OPA847 RELATED PRODUCTS

INPUT NOISE GAIN BANDWIDTH
SINGLES VOLTAGE (nV/ √Hz ) PRODUCT (MHz)
+5V OPA842 2.6 200
OPA843 2.0 800
0.001µF 20Ω +5V
OPA846 1.2 1750
100Ω OPA847

1.7pF
INP DIFFERENTIAL OPA847 DRIVER DISTORTION
–5V
50Ω Source 2kΩ 100pF –70
39pF 850Ω 2VPP, at converter input.
1:2
–75
VCM ADS5500
< 5.1dB
Harmonic Distortion (dBc)

39pF 14-Bit
Noise 850Ω
0.1µF 125MSPS –80
Figure

+5V 2kΩ –85

INN
100Ω 1.7pF
100pF –90
0.001µF 20Ω
2nd-Harmonic
OPA847
–95
3rd-Harmonic
24.6dB Gain –100
–5V
–105
Ultra-High Dynamic Range
–110
Differential ADC Driver 10 20 30 40 50
Frequency (MHz)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Copyright © 2002-2008, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

[Link]
ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC
Power Supply ............................................................................... ±6.5VDC
Internal Power Dissipation ........................ See Thermal Analysis Section DISCHARGE SENSITIVITY
Differential Input Voltage .................................................................. ±1.2V
Input Voltage Range ............................................................................ ±VS This integrated circuit can be damaged by ESD. Texas Instru-
Storage Temperature Range: D, DBV ........................... –65°C to +125°C ments recommends that all integrated circuits be handled with
Lead Temperature (soldering, 10s) .............................................. +300°C appropriate precautions. Failure to observe proper handling
Junction Temperature (TJ ) ........................................................... +150°C
ESD Rating (Human Body Model) .................................................. 1500V and installation procedures can cause damage.
(Charge Device Model) ............................................... 1500V
ESD damage can range from subtle performance degradation
(Machine Model) ........................................................... 100V
to complete device failure. Precision integrated circuits may be
NOTE: (1) Stresses above these ratings may cause permanent damage. more susceptible to damage because very small parametric
Exposure to absolute maximum conditions for extended periods may degrade
device reliability. These are stress ratings only, and functional operation of the changes could cause the device not to meet its published
device at these or any other conditions beyond those specified is not implied. specifications.

PACKAGE/ORDERING INFORMATION(1)
SPECIFIED
PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY

OPA847 SO-8 D –40°C to +85°C OPA847 OPA847ID Rails, 100

" " " " " OPA847IDR Tape and Reel, 2500
OPA847 SOT23-6 DBV –40°C to +85°C OATI OPA847IDBVT Tape and Reel, 250
" " " " " OPA847IDBVR Tape and Reel, 3000

NOTE: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this document, or see the TI web site
at [Link].

PIN CONFIGURATIONS
Top View SO Top View SOT

Output 1 6 +VS

–VS 2 5 DIS

Noninverting Input 3 4 Inverting Input

NC 1 8 DIS

Inverting Input 2 7 +VS

Noninverting Input 3 6 Output

6

–VS 4 5 NC

NC = No Connection OATI
1

Pin Orientation/Package Marking

2
OPA847
[Link] SBOS251E
ELECTRICAL CHARACTERISTICS: VS = ±5V
Boldface limits are tested at +25°C.
RL = 100Ω, RF = 750Ω, RG = 39.2Ω, and G = +20 (see Figure 1 for AC performance only), unless otherwise noted.

OPA847ID, IDBV

TYP MIN/MAX OVER TEMPERATURE

0°C to –40°C to MIN/ TEST

PARAMETER CONDITIONS +25°C +25°C(1) 70°C(2) +85°C(2) UNITS MAX LEVEL(3)
AC PERFORMANCE (see Figure 1)
Closed-Loop Bandwidth G = +12, RG = 39.2Ω, VO = 200mVPP 600 MHz typ C
G = +20, RG = 39.2Ω, VO = 200mVPP 350 230 210 195 MHz min B
G = +50, RG = 39.2Ω, VO = 200mVPP 78 63 60 57 MHz min B
Gain Bandwidth Product (GBP) G ≥ +50 3900 3100 3000 2800 MHz min B
Bandwidth for 0.1dB Gain Flatness G = +20, RL = 100Ω 60 40 35 30 MHz min B
Peaking at a Gain of +12 4.5 7 10 12 dB max B
Harmonic Distortion G = +20, f = 5MHz, VO = 2VPP
2nd-Harmonic RL = 100Ω –74 –70 –69 –68 dBc max B
RL = 500Ω –105 –90 –89 –88 dBc max B
3rd-Harmonic RL = 100Ω –103 –96 –91 –88 dBc max B
RL = 500Ω –110 –105 –100 –90 dBc max B
2-Tone, 3rd-Order Intercept G = +20, f = 20MHz 39 37 36 35 dBm min B
Input Voltage Noise Density f > 1MHz 0.85 0.92 0.98 1.0 nV/√Hz max B
Input Current Noise Density f > 1MHz 2.5 3.5 3.6 3.7 pA/√Hz max B
Pulse Response
Rise-and-Fall Time 0.2V Step 1.2 1.75 2.0 2.2 ns max B
Slew Rate 2V Step 950 700 625 535 V/µs min B
Settling Time to 0.01% 2V Step 20 ns typ C
0.1% 2V Step 10 12 14 18 ns max B
1% 2V Step 6 8 10 12 ns max B
DC PERFORMANCE(4)
Open-Loop Voltage Gain (AOL) VO = 0V 98 90 89 88 dB min A
Input Offset Voltage VCM = 0V ±0.1 ±0.5 ±0.58 ±0.60 mV max A
Average Offset Voltage Drift VCM = 0V ±0.25 ±0.25 ±1.5 ±1.5 µV/°C max B
Input Bias Current VCM = 0V –19 –39 –41 –42 µA max A
Input Bias Current Drift (magnitude) VCM = 0V –15 –15 –40 –70 nA/°C max B
Input Offset Current VCM = 0V ±0.1 ±0.6 ±0.7 ±0.85 µA max A
Input Offset Current Drift VCM = 0V ±0.1 ±0.1 ±2 ±3.5 nA/°C max B
INPUT
Common-Mode Input Range (CMIR)(5) ±3.3 ±3.1 ±3.0 ±2.9 V min A
Common-Mode Rejection Ratio (CMRR) VCM = ±0.5V, Input-Referred 110 95 93 90 dB min A
Input Impedance
Differential VCM = 0V 2.7 || 2.0 kΩ || pF typ C
Common-Mode VCM = 0V 2.3 || 1.7 MΩ || pF typ C
OUTPUT
Output Voltage Swing ≥ 400Ω Load ±3.5 ±3.3 ±3.1 ±3.0 V min A
100Ω Load ±3.4 ±3.2 ±3.0 ±2.9 V min A
Current Output, Sourcing VO = 0V 100 60 56 52 mA min A
Current Output, Sinking VO = 0V –75 –60 –56 –52 mA min A
Closed-Loop Output Impedance G = +20, f = < 100kHz 0.003 Ω typ C
POWER SUPPLY
Specified Operating Voltage ±5 V typ C
Maximum Operating Voltage ±6 ±6 ±6 ±6 V max A
Maximum Quiescent Current VS = ±5V 18.1 18.4 18.7 18.9 mA max A
Minimum Quiescent Current VS = ±5V 18.1 17.8 17.5 17.1 mA min A
Power-Supply Rejection Ratio
+PSRR, –PSRR |VS| = 4.5V to 5.5V, Input-Referred 100 95 93 90 dB min A
POWER-DOWN (disabled low) (Pin 8 on SO-8; Pin 5 on SOT23-6)
Power-Down Quiescent Current (+VS) –200 –270 –320 –370 µA max A
On Voltage (enabled high or floated) 3.5 3.75 3.85 3.95 V min A
Off Voltage (disabled asserted low) 1.8 1.7 1.6 1.5 V max A
Power-Down Pin Input Bias Current (VDIS = 0) 150 190 200 210 µA max A
Power-Down Time 200 ns typ C
Power-Up Time 60 ns typ C
Off Isolation 5MHz, Input to Output 70 dB typ C
THERMAL
Specification ID, IDBV –40 to +85 °C typ C
Thermal Resistance, θJA Junction-to-Ambient
D SO-8 125 °C/W typ C
DBV SOT23 150 °C/W typ C

NOTES: (1) Junction temperature = ambient for +25°C specifications. (2) Junction temperature = ambient at low temperature limit: junction temperature = ambient +23°C
at high temperature limit for over temperature specifications. (3) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation.
(B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out of node. VCM is the input common-mode
voltage. (5) Tested < 3dB below minimum specified CMRR at ±CMIR limits.

OPA847 3
SBOS251E [Link]
 TYPICAL CHARACTERISTICS: VS = ±5V
TA = 25°C, G = +20V/V, RG = 39.2Ω, and RL = 100Ω, unless otherwise noted.

NONINVERTING SMALL-SIGNAL INVERTING SMALL-SIGNAL

FREQUENCY RESPONSE FREQUENCY RESPONSE
6 6
VO = 0.2VPP G = +12 VO = 0.2VPP
RG = 39.2Ω RL = 100Ω G = –20 G = –30
3 RL = 100Ω 3
RG = RS = 50Ω
RF Adjusted RF Adjusted
Normalized Gain (dB)

Normalized Gain (dB)

0 0

–3 –3
G = +20
–6 –6
G = +30
–9 –9
G = +50
G = –40
–12 –12
See Figure 1 See Figure 2 G = –50
–15 –15
1 10 100 1000 1 10 100 1000
Frequency (MHz) Frequency (MHz)

NONINVERTING LARGE-SIGNAL INVERTING LARGE-SIGNAL

FREQUENCY RESPONSE FREQUENCY RESPONSE
29 35
RG = 39.2Ω See Figure 2
VO = 200mVPP
RL = 100Ω
26 32 VO = 0.2VPP
G = +20V/V
VO = 1VPP
23 29
VO = 2VPP
Gain (dB)
Gain (dB)

20 26

17 23
VO = 1VPP VO = 5VPP
14 20
VO = 2VPP RL = 100Ω
11 17 RG = RS = 50Ω
See Figure 1 VO = 5VPP G = –40V/V
8 14
10 100 1000 10 100 1000
Frequency (MHz) Frequency (MHz)

NONINVERTING PULSE RESPONSE INVERTING PULSE RESPONSE

0.25 1.25 0.25 1.25
G = +20V/V Large Signal ± 1V Large Signal ± 1V
0.20 1.00 0.20 1.00
Right Scale Right Scale
Output Voltage (250mV/div)

Output Voltage (250mV/div)

Output Voltage (50mV/div)

0.15 0.75
Output Voltage (50mV/div)

0.15 0.75
0.10 0.50 0.10 0.50
Small Signal ± 100mV Small Signal ± 100mV
0.05 0.25 0.05 0.25
Left Scale Left Scale
0 0 0 0
–0.05 –0.25 –0.05 –0.25
–0.10 –0.50 –0.10 –0.50
–0.15 –0.75 –0.15 G = –40V/V –0.75
RG = RS = 50Ω See Figure 2
–0.20 –1.00 –0.20 –1.00
See Figure 1 RL = 100Ω
–0.25 –1.25 –0.25 –1.25
Time (5ns/div) Time (5ns/div)

4
OPA847
[Link] SBOS251E
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
TA = 25°C, G = +20V/V, RG = 39.2Ω, and RL = 100Ω, unless otherwise noted.

5MHz HARMONIC DISTORTION vs LOAD RESISTANCE 1MHz HARMONIC DISTORTION vs LOAD RESISTANCE
–70 –75
G = +20V/V G = +20V/V
–75 VO = 2VPP VO = 5VPP
–80
Harmonic Distortion (dBc)

Harmonic Distortion (dBc)

–80 2nd-Harmonic
–85 –85
–90
2nd-Harmonic –90
–95

–100 –95
3rd-Harmonic 3rd-Harmonic
–105
–100
–110
See Figure 1 See Figure 1
–115 –105
100 150 200 250 300 350 400 450 500 100 150 200 250 300 350 400 450 500
Load Resistance (Ω) Load Resistance (Ω)

HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs OUTPUT VOLTAGE

–65 –75
G = +20V/V G = +20V/V
VO = 2VPP –80 F = 5MHz
–75 RL = 200Ω Harmonic Distortion (dBc) RL = 200Ω
Harmonic Distortion (dBc)

2nd-Harmonic –85
2nd-Harmonic
–85 –90

–95
–95 –100
3rd-Harmonic 3rd-Harmonic
–105
–105
–110
See Figure 1 See Figure 1
–115 –115
0.1 1 10 100 0.1 1 10
Frequency (MHz) Output Voltage Swing (VPP)

HARMONIC DISTORTION vs NONINVERTING GAIN HARMONIC DISTORTION vs INVERTING GAIN

–75 –70

–80 –75
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)

2nd-Harmonic –80
–85 2nd-Harmonic
VO = 2VPP –85
–90 RL = 200Ω VO = 2VPP
F = 5MHz –90 RL = 200Ω
–95 RF = 750Ω F = 5MHz
RG Adjusted –95 RG = 50Ω
–100 RF Adjusted
3rd-Harmonic –100
3rd-Harmonic
–105 –105
See Figure 1 See Figure 2
–110 –110
15 20 25 30 35 40 45 50 55 50 20 25 30 35 40 45 50
Gain (V/V) Gain –V/V 

OPA847 5
SBOS251E [Link]
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
TA = 25°C, G = +20V/V, RG = 39.2Ω, and RL = 100Ω, unless otherwise noted.

INPUT VOLTAGE AND CURRENT NOISE 2-TONE, 3RD-ORDER INTERMODULATION INTERCEPT

10 50
G = +20V/V
20dB to matched load.
2.7pA/√Hz 45
Voltage Noise (nV/√Hz)
Current Voise (pA/√Hz)

Current Noise

Intercept Point (+dBm)

40

1 35
0.85nV/√Hz 50Ω PO
PI
Voltage Noise 50Ω OPA847
30
50Ω
750Ω

25
39.2Ω

0 20
101 102 103 104 105 106 107 5 10 15 20 25 30 35 40 45 50
Frequency (Hz) Frequency (MHz)

NONINVERTING GAIN FLATNESS TUNE LOW GAIN INVERTING BANDWIDTH

0.5 1
VO = 200mVPP NG = 12
Deviation from 21.58dB Gain (0.1dB)

0.4 AV = +12V/V 0
NG = 14 G = –8
0.3 NG = Noise Gain –1
Normalized Gain (1dB)

NG = 16 VO = 0.2VPP
0.2 –2
RF = 750Ω
0.1 –3
0 –4
G = –1
–0.1 –5
NG = 18
–0.2 –6
NG = 20 G = –2 G = –4
–0.3 –7
External Compensation External Compensation
–0.4 –8
See Figure 8 See Figure 6
–0.5 –9
1 10 100 1000 1 10 100 1000
Frequency (MHz) Frequency (MHz)

RECOMMENDED RS vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD

100 29
Normalized Gain to Capacitive Load (dB)

G = +20V/V RS adjusted for capacitive load.

C = 10pF
26
C = 22pF

23
C = 47pF
RS (Ω)

10 C = 100pF
RS VO
VI
20 50Ω OPA847
CL 1kΩ
750Ω

17 (1kΩ is optional.)
39.2Ω

1 14
1 10 100 1000 1 10 100 1000
Capacitive Load (pF) Frequency (MHz)

6
OPA847
[Link] SBOS251E
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
TA = 25°C, G = +20V/V, RG = 39.2Ω, and RL = 100Ω, unless otherwise noted.

COMMON-MODE REJECTION RATIO AND

POWER-SUPPLY REJECTION RATIO vs FREQUENCY OPEN-LOOP GAIN AND PHASE
120 120 0
CMRR +PSRR
110
100 –30
100 20log (AOL)
CMRR and PSRR (dB)

Open-Loop Gain (dB)

Open-Loop Phase (°)

90 80 –60
∠AOL
80 60 –90
–PSRR
70
40 –120
60
50 20 –150
40
0 –180
30
20 –20 –210
102 103 104 105 106 107 108 102 103 104 105 106 107 108 109
Frequency (Hz) Frequency (Hz)

OUTPUT VOLTAGE AND CURRENT LIMITATIONS CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY

4 10
VDIS G = +20V/V
3 ZO
RL = 100Ω
Output Impedance (Ω) OPA847
2 1

1 750Ω
RL = 50Ω
VO (V)

0 0.1
RL = 25Ω
–1 39.2Ω

–2 0.01

–3

–4 0.001
–150 –100 –50 0 50 100 150 103 104 105 106 107 108
IO (mA) Frequency (Hz)

NONINVERTING OVERDRIVE RECOVERY INVERTING OVERDRIVE RECOVERY

10 0.5 10 0.25
Input G = +20V/V G = –40V/V
8 0.4 8 0.20
Right Scale RL = 100Ω RG = 50Ω
6 0.3 6 RL = 100Ω 0.15
Input

Input Voltage (mV)

Output Voltage (V)

4 0.10
Input Voltage (mV)
Output Voltage (V)

4 0.2
Right Scale
Output 2 0.05
2 0.1
Left Scale
0 0 0 0
–2 –0.1 –2 –0.05
–4 –0.2 –4 –0.10
Output
–6 –0.3 –6 Left Scale –0.15
–8 –0.4 –8 –0.20
See Figure 1 See Figure 2
–10 –0.5 –10 –0.25
Time (40ns/div) Time (40ns/div)

OPA847 7
SBOS251E [Link]
 TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
TA = 25°C, G = +20V/V, RG = 39.2Ω, and RL = 100Ω, unless otherwise noted.

PHOTODIODE TRANSIMPEDANCE
SETTLING TIME FREQUENCY RESPONSE
0.25 89
G = +20V/V RF = 20kΩ
0.20 CD = 10pF
RL = 100Ω CF Adjusted [20log 20kΩ]

Transimpedance Gain (dBΩ)

VO = 2V Step 86
Percent of Final Value (%)

0.15 CD = 20pF
0.10 CD = 100pF CD = 50pF
83
0.05
0 80 0.01µF 20kΩ OPA847 VO

–0.05
77 20kΩ
–0.10 IO
–0.15 CDIODE CF
74 [CD]
–0.20
See Figure 1
–0.25 71
0 5 10 15 20 25 30 35 40 1 10 100
Time (ns) Frequency (MHz)

TYPICAL DC DRIFT OVER TEMPERATURE SUPPLY AND OUTPUT CURRENT vs TEMPERATURE

0.2 25.0 100 20
Input Bias and Offset Current (µA)

Supply Current
100 x IOS 90 18
Input Offset Voltage (mV)

0.1 12.5

Supply Current (mA)

Output Current (mA)

Sourcing Output Current

VIO 80 16
0 0
Sinking Output Current
70 14

–0.1 –12.5
60 12
Ib

–0.2 –25.0 50 10
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
Ambient Temperature (°C) Ambient Temperature (°C)

COMMON-MODE INPUT RANGE AND OUTPUT SWING COMMON-MODE AND DIFFERENTIAL

vs SUPPLY VOLTAGE INPUT IMPEDANCE
5 107
RL = 100Ω
4
3 106 Common-Mode
Positive Output (2.3MΩ, DC)
Input Impedance (Ω)
Voltage Range (V)

2
1 105
Positive Input
0
–1 104 Differential
Negative Input (2.7kΩ, DC)
–2
–3 103
Negative Output
–4
–5 102
102 103 104 105 106 107 108
2.50
2.75
3.00
3.25
3.50
3.75
4.00
4.25
4.50
4.75
5.00
5.25
5.50
5.75
6.00

Frequency (Hz)
Supply Voltage (±V)

8
OPA847
[Link] SBOS251E
TYPICAL CHARACTERISTICS: VS = ±5V
TA = 25°C, GD = 40V/V, RG = 50Ω, and RL = 400Ω, unless otherwise noted.

DIFFERENTIAL SMALL-SIGNAL
DIFFERENTIAL PERFORMANCE TEST CIRCUIT FREQUENCY RESPONSE
3
+5V
DIS 0
GD = +20V/V

Normalized Gain (dB)

OPA847 –3
GD = +30V/V
VO R
GD = = F
VI RG –6
RG
–5V
GD = +50V/V GD = +40V/V
50Ω RF
–9

VI RG
RF
RL VO –12
50Ω RG = 50Ω
+5V –15 VO = 400mVPP
RF Adjusted
–18
OPA847 10 100 1000
Frequency (MHz)
DIS
–5V

DIFFERENTIAL LARGE-SIGNAL
FREQUENCY RESPONSE DIFFERENTIAL DISTORTION vs LOAD RESISTANCE
35 –55
GD = 40V/V GD = 40V/V
–60
VO = 4VPP
–65
Harmonic Distortion (dBc) F = 5MHz
32 –70
VO = 400mVPP
–75
Gain (dB)

VO = 5VPP 2nd-Harmonic
–80
29
–85
VO = 8VPP –90
–95
26 3rd-Harmonic
–100
–105
23 –110
1 10 100 1000 50 100 150 200 250 300 350 400 450 500
Frequency (MHz) Resistance (Ω)

DIFFERENTIAL DISTORTION vs FREQUENCY DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE

–65 –75
GD = 40V/V GD = 40V/V
RL = 400Ω RL = 400Ω
VO = 4VPP –80
Harmonic Distortion (dBc)

–75 F = 5MHz
Harmonic Distortion (dBc)

–85
2nd-Harmonic
2nd-Harmonic
–85
–90

–95 –95

3rd-Harmonic –100
3rd-Harmonic
–105
–105

–115 –110
1 10 100 1 10
Frequency (MHz) Differential Output Voltage Swing (VPP)

OPA847 9
SBOS251E [Link]
APPLICATIONS INFORMATION voltage noise for the op amp itself. This RG is suggested as a
good starting point for design. Other values are certainly
WIDEBAND, NONINVERTING OPERATION acceptable, if required by the design.
The OPA847 provides a unique combination of a very low
input voltage noise along with a very low distortion output WIDEBAND, INVERTING GAIN OPERATION
stage to give one of the highest dynamic range op amps
There can be significant benefits to operating the OPA847 as
available. Its very high gain bandwidth product (GBP) can be
an inverting amplifier. This is particularly true when a matched
used to either deliver high signal bandwidths at high gains, or
input impedance is required. Figure 2 shows the inverting
to deliver very low distortion signals at moderate frequencies
gain of a –40V/V circuit used as a starting point for the
and lower gains. To achieve the full performance of the
Typical Characteristics showing inverting mode performance.
OPA847, careful attention to PC board layout and compo-
nent selection is required, as discussed in the following Driving this circuit from a 50Ω source, and constraining the gain
sections of this data sheet. resistor (RG) to equal 50Ω, gives both a signal bandwidth and
a noise advantage. RG, in this case, acts as both the input
Figure 1 shows the noninverting gain of a +20V/V circuit used
termination resistor and the gain setting resistor for the circuit.
as the basis for most of the Typical Characteristics. Most of
Although the signal gain for the circuit of Figure 2 is double that
the curves are characterized using signal sources with a 50Ω
for Figure 1, their noise gains are nearly equal when the 50Ω
driving impedance and with measurement equipment pre-
source resistor is included. This has the interesting effect of
senting a 50Ω load impedance. In Figure 1, the 50Ω shunt
approximately doubling the equivalent GBP for the amplifier.
resistor at the VI terminal matches the source impedance of
This can be seen by observing that the gain of –40 bandwidth
the test generator, while the 50Ω series resistor at the VO
of 240MHz shown in the Typical Characteristics implies a gain
terminal provides a matching resistor for the measurement
bandwidth product of 9.6GHz, giving a far higher bandwidth at
equipment load. Generally, data sheet voltage swing speci-
a gain of –40 than at a gain of +40. While the signal gain from
fications are at the output pin (VO in Figure 1) while output
RG to the output is –40, the noise gain for bandwidth setting
power specifications are at the matched 50Ω load. The total
purposes is 1 + RF/(2 • RG). In the case of a –40V/V gain, using
100Ω load at the output combined with the 790Ω total
an RG = RS = 50Ω gives a noise gain = 1 + 2kΩ/100Ω = 21. This
feedback network load presents the OPA847 with an effec-
inverting gain of –40V/V therefore has a frequency response
tive output load of 89Ω for the circuit of Figure 1.
that more closely matches the gain of a +20 frequency re-
Voltage-feedback op amps, unlike current-feedback designs, sponse.
can use a wide range of resistor values to set their gain. The
If the signal source is actually the low impedance output of
circuit of Figure 1, and the specifications at other gains, use an
another amplifier, RG should be increased to be greater than
RG set to 39.2Ω and RF adjusted to get the desired gain. Using
the minimum value allowed at the output for that amplifier
this guideline ensures that the noise added at the output due
and RF adjusted to get the desired gain. It is critical for stable
to the Johnson noise of the resistors does not significantly
operation of the OPA847 that this driving amplifier show a
increase the total over that due to the 0.85nV/√Hz input
very low output impedance through frequencies exceeding
the expected closed-loop bandwidth for the OPA847.
+5V
+VS
+5V
0.1µF 6.8µF +VS
+

+
0.1µF 6.8µF
50Ω Source
VDIS 50Ω Load
VDIS
VI VO 50Ω 50Ω Load
50Ω VO 50Ω
OPA847 0.01µF 95.3Ω OPA847

RF
50Ω Source RG RF
750Ω
50Ω 2kΩ
VI

RG
39.2Ω
6.8µF 0.1µF 0.1µF 6.8µF
+ +

–VS –VS
–5V –5V

FIGURE 1. Noninverting G = +20 Specification and Test Circuit. FIGURE 2. Noninverting G = –40 Specification and Test Circuit.

10
OPA847
[Link] SBOS251E
WIDEBAND, HIGH SENSITIVITY, Equation 2 gives the approximate –3dB bandwidth that
TRANSIMPEDANCE DESIGN results if CF is set using Equation 1.
The high GBP and low input voltage and current noise for the
GBP
OPA847 make it an ideal wideband transimpedance ampli- f −3dB =
2πR F C D
(Hz) (2)
fier for low to moderate transimpedance gains. Very high
transimpedance gains (> 100kΩ) will benefit from the low The example of Figure 3 gives approximately 104MHz flat
input noise current of a JFET input op amp such as the bandwidth using the 0.18pF feedback compensation capaci-
OPA657. Unity-gain stability in the op amp is not required for tor. This bandwidth easily supports an OC-3 receiver with
application as a transimpedance amplifier. Figure 3 shows exceptional sensitivity.
one possible transimpedance design example that would be If the total output noise is bandlimited to a frequency less
particularly suitable for the 155Mbit data rate of an OC-3 than the feedback pole frequency, a very simple expression
receiver. Designs that require high bandwidth from a large for the equivalent input noise current is shown as Equation 3.
area detector with relatively low transimpedance gain will
(3)
benefit from the low input voltage noise for the OPA847. The
amplifier’s input voltage noise is peaked up over frequency
 4kT 
iEQ = iN2 + 
2
+
(EN 2πCD F)2
by the diode source capacitance, and can (in many cases) 
become the limiting factor to input sensitivity. The key ele-  RF  3
ments to the design are the expected diode capacitance (CD) where:
with the reverse bias voltage (–VB) applied, the desired
iEQ = Equivalent input noise current if the output noise is
transimpedance gain (RF), and the GBP for the OPA847
bandlimited to f < 1/2πRFCF
(3900MHz). With these three variables set (including the
iN = Input current noise for the op amp inverting input
parasitic input capacitance for the OPA847 added to CD), the
feedback capacitor value (CF) can be set to control the eN = Input voltage noise for the op amp
frequency response. CD = Total Inverting Node Capacitance
f = Bandlimiting frequency in Hz (usually a post filter prior
to further signal processing)
+5V Evaluating this expression up to the feedback pole frequency
Power-supply at 74MHz for the circuit of Figure 3 gives an equivalent input
decoupling not shown.
noise current of 3.0pA/√Hz. This is slightly higher than the
100pF 0.1µF 12kΩ 2.5pA/√Hz input current noise for the op amp. This total
OPA847
equivalent input current noise is slightly increased by the last
VDIS term in the equivalent input noise expression. It is essential
in this case to use a low-voltage noise op amp. For example,
RF if a slightly higher input noise voltage, but otherwise identical,
–5V
12kΩ
λ op amp were used instead of the OPA847 in this application
(say 2.0nV/√Hz), the total input referred current noise would
CF
1pF increase to 3.7pA/√Hz. Low input voltage noise is required
0.18pF
Photodiode
for the best sensitivity in these wideband transimpedance
applications. This is often unspecified for dedicated transim-
–VB
pedance amplifiers with a total output noise for a specified
source capacitance given instead. It is the relatively high
FIGURE 3. Wideband, High Sensitivity, OC-3 Transimpedance
input voltage noise for those components that cause higher
Amplifier.
than expected output noise if the source capacitance is
higher than specified.
To achieve a maximally flat 2nd-order Butterworth frequency
response, set the feedback pole as shown in Equation 1. The output DC error for the circuit of Figure 3 is minimized by
including a 12kΩ to ground on the noninverting input. This
1 GBP reduces the contribution of input bias current errors (for total
= (1)
2πRF CF 4πRF CD output offset voltage) to the offset current times the feedback
resistor. To minimize the output noise contribution of this
Adding the common-mode and differential mode input ca-
resistor, 0.01µF and 100pF capacitors are included in paral-
pacitance (1.2 + 2.5)pF to the 1pF diode source capacitance
lel. Worst-case output DC error for the circuit of Figure 3 at
of Figure 3, and targeting a 12kΩ transimpedance gain using
25°C is:
the 3900MHz GBP for the OPA847 requires a feedback pole
set to 74MHz to get a nominal Butterworth frequency re- VOS = ±0.5mV (input offset voltage) ± 0.6µA (input offset
sponse design. This requires a total feedback capacitance of current) • 12kΩ = ±7.2mV
0.18pF. That total is shown in Figure 3, but recall that typical Worst-case output offset DC drift (over the 0°C to 70°C span) is:
surface-mount resistors have a parasitic capacitance of 0.2pF, dVOS/dT = ±1.5µV/°C (input offset drift) ± 2nA/°C (input
leaving no external capacitor required for this design. offset current drift) • 12kΩ = ±21.5µV/°C.

OPA847 11
SBOS251E [Link]
Even with bias current cancellation, the output DC errors are Considering only the noise gain (which is the same as the
dominated in this example by the offset current term. Im- noninverting signal gain) for the circuit of Figure 5, the low-
proved output DC precision and drift are possible, particularly frequency noise gain (NG1) is set by the resistor ratio, while
at higher transimpedance gains, using the JFET input the high-frequency noise gain (NG2) is set by the capacitor
OPA657. The JFET input removes the input bias current ratio. The capacitor values set both the transition frequencies
from the error equation (eliminating the need for the resistor and the high-frequency noise gain. If the high-frequency
to ground on the noninverting input), leaving only the input noise gain, determined by NG2 = 1 + CS/CF, is set to a value
offset voltage and drift as an output DC error term. greater than the recommended minimum stable gain for the
Included in the Typical Characteristics are transimpedance op amp, and the noise gain pole (set by 1/RFCF) is placed
frequency response curves for a fixed 20kΩ gain over vari- correctly, a very well controlled 2nd-order low-pass fre-
ous detector diode capacitance settings. These curves are
repeated in Figure 4, along with the test circuit. As the
+5V
photodiode capacitance changes, the feedback capacitor
must change to maintain a stable and flat frequency re-
VDIS
sponse. Using Equation 1, CF is adjusted to give the
Butterworth frequency responses shown in Figure 4. OPA847 VO

PHOTODIODE TRANSIMPEDANCE RG RF
FREQUENCY RESPONSE 200Ω 850Ω
89 VI
RF = 20kΩ
CD = 10pF CS CF
CF Adjusted [20 log(20kΩ)]
39pF 1.7pF
Transimpedance Gain (dBΩ)

86
CD = 20pF
CD = 100pF CD = 50pF –5V
83
FIGURE 5. Broadband, Low-Inverting Gain External
80
0.01µF 20kΩ OPA847 VO Compensation.
77 20kΩ
IO

74
CD CF quency response results.
To choose the values for both CS and CF, two parameters and
71 only three equations need to be solved. The first parameter is
1 10 100
the target high-frequency noise gain (NG 2), which should be
Frequency (MHz)
greater than the minimum stable gain for the OPA847. Here, a
FIGURE 4. Transimpedance Bandwidth vs CD. target of NG2 = 24 is used. The second parameter is the desired
low-frequency signal gain, which also sets the low-frequency
LOW-GAIN COMPENSATION FOR IMPROVED SFDR noise gain (NG1). To simplify this discussion, we will target a
Where a low gain is desired, and inverting operation is maximally flat, 2nd-order, low-pass Butterworth frequency re-
acceptable, a new external compensation technique can be sponse (Q = 0.707). The signal gain shown in Figure 5 sets the
used to retain the full slew rate and noise benefits of the low-frequency noise gain to NG1 = 1 + RF/RG (= 5.25 in this
OPA847, while giving increased loop gain and the associ- example). Then, using only these two gains and the GBP for the
ated distortion improvements offered by a non-unity-gain OPA847 (3900MHz), the key frequency in the compensation is
stable op amp. This technique shapes the loop gain for good set by Equation 4.
stability, while giving an easily controlled 2nd-order low-pass
GBP  NG1  NG1 
frequency response. This technique is used for the circuit on ZO = 2 
1−  − 1− 2  (4)
NG 1  NG2  NG2 
the front page of this data sheet in a differential configuration
to achieve extremely low distortion through high frequencies Physically, this ZO (4.4MHz for the values shown above) is
(< –90dBc through 30MHz). The amplifier portion of this set by 1/(2πRF(CF + CS)) and is the frequency at which the
circuit is set up for a differential gain of 8.5V/V from a rising portion of the noise gain would intersect the unity gain
differential input signal to the output. Using the input trans- if projected back to a 0dB gain. The actual zero in the noise
former shown improves the noise figure and translates from gain occurs at NG1 • ZO and the pole in the noise gain occurs
a single-ended to a differential signal. If the source is differ- at NG2 • ZO. That pole is physically set by 1/(RFCF). Since
ential already, it can be fed directly into the gain setting GBP is expressed in Hz, multiply ZO by 2π and use to get CF
resistors. To set the compensation capacitors (CS and CF), by solving Equation 5.
consider the half circuit of Figure 5, where the 50Ω source is
1
reflected through the 1:2 transformer, then cut in half, and CF = (= 1.76pF) (5)
grounded to give a total impedance to the AC ground for the 2πRF ZO NG2
circuit on the front page equal to 200Ω.

12
OPA847
[Link] SBOS251E
Finally, since CS and CF set the high-frequency noise gain,
determine CS using Equation 6 (solving for CS by using NG2 = 24): LOW GAIN INVERTING BANDWIDTH

CS = (NG2 − 1)CF
1
(6)
0
which gives CS = 40.6pF. G = –8
–1

Normalized Gain (1dB)

VO = 0.2VPP
Both of these calculated values have been reduced slightly –2
in Figure 5 to account for parasitics. The resulting closed- –3
loop bandwidth is approximately equal to Equation 7. –4
G = –1
–5
f –3dB ≅ ZO • GBP (7)
–6
G = –2 G = –4
For the values shown in Figure 5, f–3dB is approximately –7
131MHz. This is less than that predicted by simply dividing –8
the GBP product by NG1. The compensation network controls –9
the bandwidth to a lower value, while providing the full slew 1 10 100 1000
rate at the output and an exceptional distortion performance Frequency (MHz)
due to increased loop gain at frequencies below NG1 • ZO.
Using this low-gain inverting compensation, along with the +5V

differential structure for the circuit shown on the front page of VDIS
this data sheet, gives a significant reduction in harmonic
distortion. The measured distortion at 2VPP output does not OPA847 VO

rise above –95dB until frequencies > 20MHz are applied.

The Typical Characteristics show the exceptional bandwidth RF
RG –5V 750Ω
control possible using this technique at low inverting gains. VI
Figure 6 repeats the measured results with the test circuit shown.
0Ω Source CS CF
The compensation capacitors, CS and CF, are set by targeting
a high-frequency noise gain of 21 and using equations 4 through
6. This approach allows relatively low inverting gain applications
to use the full slew rate and low input noise of the OPA847. FIGURE 6. Low-Gain Inverting Performance.

LOW-NOISE FIGURE, figures in the 10dB range (for a matched 50Ω input) are
HIGH DYNAMIC RANGE AMPLIFIER easily achieved with just the OPA847, Figure 7 illustrates a
technique to reduce the noise figure even further, while
The low input noise voltage of the OPA847 and its very high
providing a broadband, high-gain HF amplifier stage using
2-tone, 3rd-order intermodulation intercept can be used to
two stages of the OPA847.
good advantage as a fixed-gain amplifier. While input noise

6.19kΩ

+5V
Input match
set by this
feedback path OPA847 PO

+5V > 55dBm

–5V intercept
50Ω Source to 30MHz
1:2 750Ω 1.5kΩ
PI
OPA847
200Ω 1.6pF
4.3dB
Noise
–5V 46pF
Figure 10pF
420Ω

PO
30.1Ω Overall Gain = 35.6dB
PI

FIGURE 7. Very High Dynamic Range HF Amplifier.

OPA847 13
SBOS251E [Link]
This circuit uses two stages of forward gain with an overall
+5V
feedback loop to set the input impedance match. The input
transformer provides both a noiseless voltage gain and a VI VDIS 50Ω
signal inversion to retain an overall noninverting signal path
50Ω 50Ω R1 OPA847 VO
from PI to PO. The second amplifier stage is inverting to
provide the correct feedback polarity through the 6.19kΩ
resistor. To achieve a 50Ω input match at the primary of the
1:2 transformer, the secondary must see a 200Ω load imped- –5V
ance. At higher frequencies, the match is provided by the RF
200Ω resistor in series with 10pF. The low-noise figure 750Ω
(4.3dB) for this circuit is achieved by using the transformer,
the low-voltage noise OPA847, and the input match set by RG
66.5Ω
the feedback at lower frequencies intended for this HF
design. The 1st-stage amplifier provides a gain of +15V/V.
The very high SFDR is provided by operating the output FIGURE 8. Low Noninverting Gain Flatness Trim.
stage at a low signal gain of –2 and using the inverting
compensation technique to shape the noise gain to hold it
The effect of this noninverting gain flatness tune is shown in
stable. This 2nd-stage compensation is set to intentionally
Figure 9. At an NG of 12, R1 is removed and only RF and RG
bandlimit the overall response to approximately 100MHz. For
are present in Figure 8. The peaking is typically 4.5dB, as
output loads > 400Ω, this circuit can give a 2-tone SFDR that
shown in the small-signal frequency response curves versus
exceeds 90dB through 30MHz. In narrowband applications,
gain curves at this setting. As R1 is decreased, the operating
the 3rd-order intercept exceeds 55dBm. Besides offering a
noise gain (NG) increases, reducing the peaking and band-
very high dynamic range, this circuit improves on standard
width until the nominal design point of +20 noise gain gives
HF amplifiers by offering a precisely controlled gain and a
a non-peaked response.
very flexible output interface capability.

NONINVERTING GAIN FLATNESS TUNE

NONINVERTING GAIN FLATNESS COMPENSATION 0.5
VO = 200mVPP NG = 12
Deviation from 21.58dB Gain (0.1dB)

Decreasing the operating gain from the nominal design point of 0.4 AV = +12V/V
+20 decreases the phase margin. This increases Q for the NG = 14
0.3 NG = Noise Gain
closed-loop poles, peaks up the frequency response, and NG = 16
0.2
extends the bandwidth. A peaked frequency response shows 0.1
overshoot and ringing in the pulse response, as well as higher 0
integrated output noise. When operating the OPA847 at a
–0.1
noninverting gain < +12V/V, increased peaking and possible NG = 18
–0.2
sustained oscillations may result. However, operation at low NG = 20
–0.3
gains may be desirable to take advantage of the higher slew
–0.4
rate and exceptional DC precision of the OPA847. Numerous
–0.5
external compensation techniques are suggested for operating 1 10 100 1000
a high-gain op amp at low gains. Most of these give zero/pole Frequency (MHz)
pairs in the closed-loop response that cause long term settling
tails in the pulse response and/or phase nonlinearity in the FIGURE 9. Frequency Response Flatness with External
frequency response. Tuning Resistor.

Figure 8 shows a resistor-based compensation technique

DIFFERENTIAL OPERATION
that allows the flatness at low noninverting signal gains to be
controlled separately from the signal gain. This approach Operating two OPA847 amplifiers in a differential inverting
retains the full slew rate to the output but gives up some of configuration can further suppress even-order harmonic terms.
the low-noise benefit of the OPA847. Including the effect of The Typical Characteristics show measured performance for
the total source impedance (25Ω in Figure 8), tuning resistor this condition. These measurements were done at the relatively
R1 can be set using Equation 8. high gain of 40V/V. Even lower distortion is possible operating
at lower gains using the external inverting compensation tech-
RF + RS A V
R1 = (8) niques, as discussed previously. For the distortion data pre-
NG − A V
sented in Figure 10, the output swing is increased to 4V PP into
where: 400Ω to allow direct comparison to the single-channel data at
AV = desired signal gain (+12V/V in Figure 8) 2VPP into 200Ω. Comparing the 2nd- and 3rd-harmonics at
20MHz in Figure 10 to the gain of +20, 2V PP, 200Ω data, shows
NG = target noise gain (adjusted in Figure 9)
the 2nd-harmonic is reduced to –76dBc (from –67dBc) and the
RS = total source impedance 3rd-harmonic is reduced from –80dBc to –85dBc. Using the two

14
OPA847
[Link] SBOS251E
 supply of +5V and up to a single supply of +12V. If shutdown
–65 is desired for single-supply operation, it is important to realize
GD = 40V/V
RL = 400Ω that the shutdown pin is referenced from the positive supply
VO = 4VPP

Harmonic Distortion (dBc)

–75 pin. Open collector (drain) interfaces are suggested for
2nd-Harmonic
single-supply operation above +5V.
–85

–95
DESIGN-IN TOOLS
3rd-Harmonic DEMONSTRATION FIXTURES
–105 Two printed circuit boards (PCBs) are available to assist in
the initial evaluation of circuit performance using the OPA847
–115 in its two package options. Both of these are offered free
1 10 100
of charge as unpopulated PCBs, delivered with a user’s
Frequency (MHz)
guide. The summary information for these fixtures is shown
in Table I.
FIGURE 10. Differential Distortion vs Frequency.

amplifiers in this configuration has significantly reduced the ORDERING LITERATURE

PRODUCT PACKAGE NUMBER NUMBER
2nd-harmonic, even after doubling the output voltage swing (to
4VPP) and the gain (to 40V/V). OPA847ID SO-8 DEM-OPA-SO-1B SBOU026
OPA847IDBV SOT23-6 DEM-OPA-SOT-1B SBOU027

SINGLE-SUPPLY OPERATION TABLE I. Demonstration Fixtures by Package.

The OPA847 can be operated from a single power supply if
system constraints require it. Operation from a single +5V to The demonstration fixtures can be requested at the Texas
+12V supply is possible with minimal change in AC perfor- Instruments web site ([Link]) through the OPA847
mance. The Typical Characteristics show the input and product folder.
output voltage ranges for a bipolar supply range from ±2.5V
to ±6.0V. The Common-Mode Input Range and Output Swing MACROMODELS AND APPLICATIONS SUPPORT
vs Supply Voltage curve shows that the required headroom
Computer simulation of circuit performance using SPICE is
on both the input and output pins remains at approximately
often a quick way to analyze the performance of the OPA847
1.5V over this entire range. On a single +5V supply, for
in its intended application. This is particularly true for video
instance, this means the noninverting input should remain
and RF amplifier circuits where parasitic capacitance and
centered at +2.5V ± 1V, as should the output pin. Figure 11
inductance can play a major role in circuit performance. A
shows an example application biasing the noninverting input
SPICE model for the OPA847 is available through the TI web
at mid-supply and running an AC-coupled input to the invert-
site ([Link]). These models do a good job of predicting
ing gain path. Since the gain resistor is blocked off for DC,
small-signal AC and transient performance under a wide
the bias point on the noninverting input appears at the output,
variety of operating conditions. They do not do as well in
centering up the output as well as on the power supply. The
predicting the harmonic distortion characteristics. These
OPA847 can support this mode of operation down to a single
models do not attempt to distinguish between the package
types in their small-signal AC performance.

+VCC
OPERATING SUGGESTIONS
+5V +12V
SETTING RESISTOR VALUES TO MINIMIZE NOISE
2RF Range
The OPA847 provides a very low input noise voltage while
Power-supply decoupling requiring a low 18.1mA of quiescent current. To take full
not shown. advantage of this low input noise, careful attention to the other
V R
0.01µF 2RF OPA847 VO = CC – VI F possible noise contributors is required. See Figure 12 for the
2 RG
VDIS op amp noise analysis model with all the noise terms included.
In this model, all the noise terms are taken to be noise voltage
or current density terms in either nV/√Hz or pA/√Hz.
RG RF
The total output spot noise voltage is computed as the
VI
square root of the squared contributing terms to the output
noise power. This computation adds all the contributing noise
FIGURE 11. Single-Supply Inverting Amplifier. powers at the output by superposition, then takes the square

OPA847 15
SBOS251E [Link]
 practice, this only holds true when the phase margin ap-
ENI proaches 90°, as it does in high-gain configurations. At low
gains (increased feedback factors), most high-speed ampli-
OPA847 EO fiers exhibit a more complex response with lower phase
RS
IBN margin. The OPA847 is compensated to give a maximally flat
2nd-order Butterworth closed-loop response at a noninverting
ERS
gain of +20 (see Figure 1). This results in a typical gain of
RF +20 bandwidth of 350MHz, far exceeding that predicted by
√4kTRS
dividing the 3900MHz GBP by 20. Increasing the gain causes
√4kTRF the phase margin to approach 90° and the bandwidth to more
RG IBI
4kT closely approach the predicted value of (GBP/NG). At a gain
4kT = 1.6E – 20J
RG
at 290°K of +50, the OPA847 very nearly matches the 78MHz band-
width predicted using the simple formula and the typical GBP
of 3900MHz.
FIGURE 12. Op Amp Noise Analysis Model.
Inverting operation offers some interesting opportunities to
increase the available GBP. When the source impedance is
root to get back to a spot noise voltage. Equation 9 shows the
matched by the gain resistor (see Figure 2), the signal gain
general form for this output noise voltage using the terms
is (1 + RF/RG), while the noise gain for bandwidth purposes
illustrated in Figure 11.
is (1 + RF/2RG). This cuts the noise gain almost in half,
(9) increasing the minimum operating gain for inverting opera-

(E )
tion under these condition to –22 and the equivalent gain
EO = 2
NI + (IBN RS )2 + 4kTRS NG2 + (IBI RF )2 + 4kTRF NG
bandwidth product to > 7.8GHz.
Dividing this expression by the noise gain (NG = 1 + RF/RG)
gives the equivalent input-referred spot noise voltage at the DRIVING CAPACITIVE LOADS
noninverting input, as shown in Equation 10. One of the most demanding, and yet very common, load
(10) conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an ADC, including additional
 I R  2 4kTRF
EN = ENI
2
+ (IBN RS )2 + 4kTRS +  BI F  + external capacitance that may be recommended to improve
 NG  NG ADC linearity. A high-speed, high open-loop gain amplifier
Putting high resistor values into Equation 10 can quickly like the OPA847 can be very susceptible to decreased
dominate the total equivalent input-referred noise. A 45Ω stability and may give closed-loop response peaking when a
source impedance on the noninverting input adds a Johnson capacitive load is placed directly on the output pin. When the
voltage noise term equal to the amplifier’s voltage noise by amplifier’s open-loop output resistance is considered, this
itself. As a simplifying constraint, set RG = RS in Equation 10 capacitive load introduces an additional pole in the signal
and assume an RS/2 source impedance at the noninverting path that can decrease the phase margin. Several external
input, where RS is the signal source impedance and another solutions to this problem are suggested. When the primary
matching RS to ground is at the noninverting input. This considerations are frequency response flatness, pulse re-
results in Equation 11, where NG > 12 is assumed to further sponse fidelity, and/or distortion, the simplest and most
simplify the expression. effective solution is to isolate the capacitive load from the
feedback loop by inserting a series isolation resistor between

(IB RS )2 + 4kT 3R2S 

5 the amplifier output and the capacitive load. This does not
EN = ENI
2
+ (11)
4 eliminate the pole from the loop response, but rather shifts it
and adds a zero at a higher frequency. The additional zero
Evaluating this expression for RS = 50Ω gives a total equiva- acts to cancel the phase lag from the capacitive load pole,
lent input noise of 1.4nV/√Hz. Note that at these higher thus increasing the phase margin and improving stability.
gains, the simplified input referred spot noise expression of
The Typical Characteristics help the designer pick a recom-
Equation 11 does not include the gain. This is a good
mended RS versus capacitive load. The resulting frequency
approximation for NG > 12, as is typically required by stability
response curves show a flat response for several selected
considerations.
capacitive loads and recommended RS combinations. Para-
sitic capacitive loads greater than 2pF can begin to degrade
FREQUENCY RESPONSE CONTROL the performance of the OPA847. Long PCB traces, un-
Voltage-feedback op amps exhibit decreasing closed-loop matched cables, and connections to multiple devices can
bandwidth as the signal gain is increased. In theory, this easily cause this value to be exceeded. Always consider this
relationship is described by the Gain Bandwidth Product effect carefully and add the recommended series resistor as
(GBP) shown in the Electrical Characteristics. Ideally, divid- close as possible to the OPA847 output pin (see the Board
ing GBP by the noninverting signal gain (also called the Layout section).
Noise Gain, or NG) predicts the closed-loop bandwidth. In

16
OPA847
[Link] SBOS251E
The criterion for setting the RS resistor is a maximum band- If the full envelope of the two frequencies needs to be 2VPP,
width, flat frequency response at the load. For the OPA847 this requires each tone to be 4dBm. The 3rd-order
operating in a gain of +20, the frequency response at the intermodulation spurious tones will then be 2(34 – 4) = 60dBc
output pin is very flat to begin with, allowing relatively small below the test-tone power level (–56dBm). If this same 2VPP
values of RS to be used for low capacitive loads. As the signal 2-tone envelope is delivered directly into the input of an ADC
gain is increased, the unloaded phase margin also increases. without the matching loss or the loading of the 50Ω network,
Driving capacitive loads at higher gains requires lower RS the intercept would increase to at least 40dBm.
values than those shown for a gain of +20. With the same signal and gain conditions, but now driving
directly into a light load, the spurious tones will then be at
DISTORTION PERFORMANCE least 2(40 – 4) = 72dBc below the 4dBm test-tone power
levels centered on 30MHz. Tests have shown that they are
The OPA847 is capable of delivering an exceptionally low
in fact much lower due to the lighter loading presented by
distortion signal at high frequencies over a wide range of
most ADCs.
gains. The distortion plots in the Typical Characteristics show
the typical distortion under a wide variety of conditions. Most
DC ACCURACY AND OFFSET CONTROL
of these plots are limited to a 110dB dynamic range. The
OPA847’s distortion driving a 200Ω load does not rise above The OPA847 can provide excellent DC signal accuracy due
–90dBc until either the signal level exceeds 2.0VPP and/or to its high open-loop gain, high common-mode rejection, high
the fundamental frequency exceeds 5MHz. Distortion in the power-supply rejection, and low input offset voltage and bias
audio band is < –130dBc. current offset errors. To take full advantage of its low ±0.5mV
input offset voltage, careful attention to the input bias current
Generally, until the fundamental signal reaches very high
cancellation is also required. The low-noise input stage for
frequencies or powers, the 2nd-harmonic dominates the dis-
the OPA847 has a relatively high input bias current (19µA
tortion with a negligible 3rd-harmonic component. Focusing
typical into the pins), but with a very close match between the
then on the 2nd-harmonic, increasing the load impedance
two input currents—typically ±100nA input offset current.
improves distortion directly. Remember that the total load
Figures 13 and 14 show typical distributions of input offset
includes the feedback network—in the noninverting configura-
voltage and current for the OPA847.
tion this is the sum of RF + RG, while in the inverting
configuration this is only RF (see Figure 2). Increasing the
1200
output voltage swing increases harmonic distortion directly. A Mean = 48µV
Standard Deviation = 110µV
6dB increase in output swing generally increases the 2nd- 1000 Total Count = 4040
harmonic 12dB and the 3rd-harmonic 18dB. Increasing the
signal gain also increases the 2nd-harmonic distortion. Finally, 800
the distortion increases as the fundamental frequency in-
Count

600
creases due to the rolloff in the loop gain with frequency.
Conversely, the distortion improves going to lower frequencies
400
down to the dominant open-loop pole at approximately 80kHz.
The OPA847 has an extremely low 3rd-order harmonic 200
distortion. This also gives a high 2-tone 3rd-order
0
intermodulation intercept, as shown in the Typical Character-
< –600
< –540
< –480
< –420
< –360
< –300
< –240
< –180
< –120
< –60
0
< 60
< 120
< 180
< 240
< 300
< 360
< 420
< 480
< 540
< 600
> 600
istics. This intercept curve is defined at the 50Ω load when
driven through a 50Ω matching resistor to allow direct com-
µV
parisons to RF devices. This matching network attenuates
the voltage swing from the output pin to the load by 6dB. If FIGURE 13. Input Offset Voltage Distribution in µV.
the OPA847 drives directly into the input of a high-imped-
ance device, such as an ADC, this 6dB attenuation is not 900
Mean = 50nA
taken. Under these conditions, the intercept as reported in 800 Standard Deviation = 120nA
the Typical Characteristics increases by a minimum of 6dBm. Total Count = 4040
700
The intercept is used to predict the intermodulation spurious
600
power levels for two closely spaced frequencies. If the two
Count

test frequencies, f1 and f2, are specified in terms of average 500

and delta frequency, fO = (f1 + f2)/2 and ∆f = f2 – f1 /2, the 400
two 3rd-order, close-in spurious tones appear at fO ± 3 • ∆f. 300
The difference between the two equal test-tone power levels 200
and these intermodulation spurious power levels is given by
100
∆dBc = 2(IM3 – PO), where IM3 is the intercept taken from
0
the Typical Characteristics and PO is the power level in dBm
< –600
< –540
< –480
< –420
< –360
< –300
< –240
< –180
< –120
< –60
0
< 60
< 120
< 180
< 240
< 300
< 360
< 420
< 480
< 540
< 600
> 600

at the 50Ω load for one of the two closely spaced test
frequencies. For instance, at 30MHz, the OPA847 at a gain
nA
of +20 has an intercept of 34dBm at a matched 50Ω load.
FIGURE 14. Input Offset Current Distribution in nA.

OPA847 17
SBOS251E [Link]
The total output offset voltage can be considerably reduced In this case, the input is brought into an inverting gain resistor
by matching the source impedances looking out of the two with the DC adjustment as an additional current summed into
inputs. For example, one way to add bias current cancella- the inverting node. The resistor values setting this offset
tion to the circuit of Figure 1 is to insert a 12.1Ω series adjustment are much larger than the signal path resistors.
resistor into the noninverting input from the 50Ω terminating This ensures that this adjustment has minimal impact on the
resistor. When the 50Ω source resistor is DC-coupled, this loop gain and, hence, the frequency response.
increases the source impedance for the noninverting input
bias current to 37.1Ω. Since this is now equal to the imped- POWER SHUTDOWN OPERATION
ance looking out of the inverting input (RF || RG) for Figure 1,
The OPA847 provides an optional power shutdown feature
the circuit cancels the gains for the bias currents to the
that can be used to reduce system power. If the V DIS control
output, leaving only the offset current times the feedback
pin is left unconnected, the OPA847 operates normally. This
resistor as a residual DC error term at the output. Using the
shutdown is intended only as a power saving feature. For-
750Ω feedback resistor, this output error is now less than
ward path isolation is very good for small signals. Large
±0.85µA • 750Ω = ±640µV over the full temperature range for
signal isolation is not ensured. Using this feature to multiplex
the circuit of Figure 1, with a 12.1Ω resistor added as
two or more outputs together is not recommended. Large
described. The output DC offset is then dominated by the
signals applied to the shutdown output stages can turn on
input offset voltage multiplied by the signal gain. For the
parasitic devices, degrading signal linearity for the desired
circuit of Figure 1, this is a worst-case output DC offset of
channel.
±0.6mV • 20 = ±12mV over the full temperature range.
Turn-on time is very quick from the shutdown condition,
A fine-scale output offset null, or DC operating point adjust-
typically < 60ns. Turn-off time is strongly dependent on the
ment, is sometimes required. Numerous techniques are
external circuit configuration, but is typically 200ns for the
available for introducing a DC offset control into an op amp
circuit of Figure 1. Using the OPA847 with higher external
circuit. Most of these techniques eventually reduce to setting
resistor values, such has high-gain transimpedance circuits,
up a DC current through the feedback resistor. One key
slows the shutdown time since the time constants for the
consideration to selecting a technique is to ensure that it has
internal nodes to discharge are longer.
a minimal impact on the desired signal path frequency
response. If the signal path is intended to be noninverting, To shutdown, the control pin must be asserted low. This logic
the offset control is best applied as an inverting summing control is referenced to the positive supply, as shown in the
signal to avoid interaction with the signal source. If the signal simplified circuit of Figure 16.
path is intended to be inverting, applying the offset control to
the noninverting input can be considered. For a DC-coupled
+VS
inverting input signal, this DC offset signal sets up a DC
current back into the source that must be considered. An
offset adjustment placed on the inverting op amp input can
also change the noise gain and frequency response flatness.
Figure 15 shows one example of an offset adjustment for a 8kΩ
DC-coupled signal path that has minimum impact on the
signal frequency response.
Q1

+5V
VCC
Power-supply decoupling
not shown.
17kΩ 120kΩ
0.1µF 48Ω OPA847 VO
IS
VDIS
Control –VS

VEE
–5V FIGURE 16. Simplified Shutdown Control Circuit.
+5V RG RF
50Ω 1kΩ In normal operation, base current to Q1 is provided through
VI
5kΩ the 120kΩ resistor, while the emitter current through the 8kΩ
resistor sets up a voltage drop that is inadequate to turn on
±200mV Output Adjustment
20kΩ the two diodes in Q1’s emitter. As V DIS is pulled low,
100Ω
additional current is pulled through the 8kΩ resistor, even-
0.1µF VO RF
=– = –20V/V
tually turning on these two diodes (≈ 180µA). At this point,
5kΩ VI RG
any further current pulled out of V DIS goes through those
diodes holding the emitter-base voltage of Q1 at approxi-
–5V mately 0V. This shuts off the collector current out of Q1,
turning the amplifier off. The supply current in the shutdown
FIGURE 15. DC-Coupled, Inverting Gain of –20 with Output
mode is only that required to operate the circuit of Figure 16.
Offset Adjustment.

18
OPA847
[Link] SBOS251E
The shutdown feature for the OPA847 is a positive-supply unintentional bandlimiting. To reduce unwanted capacitance,
referenced, current-controlled interface. Open-collector (or drain) create a window around the signal I/O pins in all of the
interfaces are most effective, as long as the controlling logic ground and power planes around these pins. Otherwise,
can sustain the resulting voltage (in open mode) that appears ground and power planes should be unbroken elsewhere on
at the V DIS pin. The V DIS pin voltage is one diode below the the board.
positive supply voltage applied to the OPA847 if the logic b) Minimize the distance (< 0.25") from the power-supply
voltage is open. For voltage output logic interfaces, the on/off pins to high-frequency 0.1µF decoupling capacitors. At the
voltage levels described in the Electrical Characteristics apply device pins, the ground and power plane layout should not
only for a +5V supply. An open-drain interface is recommended be in close proximity to the signal I/O pins. Avoid narrow
for a shutdown operation using a higher positive supply and/or power and ground traces to minimize inductance between
logic families with inadequate high-level voltage swings. the pins and the decoupling capacitors. The power-supply
connections should always be decoupled with these capaci-
THERMAL ANALYSIS tors. Larger (2.2µF to 6.8µF) decoupling capacitors, effective
The OPA847 does not require heatsinking or airflow in most at lower frequencies, should also be used on the main supply
applications. Maximum desired junction temperature sets the pins. These can be placed somewhat further from the device
maximum allowed internal power dissipation, as described and can be shared among several devices in the same area
here. In no case should the maximum junction temperature of the PC board.
be allowed to exceed 150°C. c) Careful selection and placement of external compo-
Operating junction temperature (TJ) is given by TA + PD • θJA. nents preserves the high-frequency performance of the
The total internal power dissipation (PD) is the sum of OPA847. Use resistors that have low reactance at high
quiescent power (PDQ) and additional power dissipated in the frequencies. Surface-mount resistors work best and allow a
output stage (PDL) to deliver load power. Quiescent power is tighter overall layout. Metal film and carbon composition
simply the specified no-load supply current times the total axially leaded resistors can also provide good high-fre-
supply voltage across the part. PDL depends on the required quency performance. Again, keep their leads and PCB trace
output signal and load but would, for a grounded resistive length as short as possible. Never use wirewound-type
load, be at a maximum when the output is fixed at a voltage resistors in a high-frequency application. Since the output pin
equal to half either supply voltage (for equal bipolar sup- and inverting input pin are the most sensitive to parasitic
plies). Under this worst-case condition, PDL = VS2/(4 • RL), capacitance, always position the feedback and series output
where RL includes feedback network loading. This is the resistor, if any, as close as possible to the output pin. Other
absolute highest power that can be dissipated for a given RL. network components, such as noninverting input termination
All actual applications dissipate less power in the output resistors, should also be placed close to the package. Where
stage. double-side component mounting is allowed, place the feed-
back resistor directly under the package on the other side of
Note that it is the power in the output stage and not into the
the board between the output and inverting input pins. Even
load that determines internal power dissipation.
with a low parasitic capacitance shunting the external resis-
As a worst-case example, compute the maximum TJ using an tors, excessively high resistor values can create significant
OPA847IDBV (SOT23-6 package) in the circuit of Figure 1 time constants that can degrade performance. Good axial
operating at the maximum specified ambient temperature of metal film or surface-mount resistors have approximately
+85°C and driving a grounded 100Ω load. Maximum internal 0.2pF in shunt with the resistor. For resistor values > 2.0kΩ,
power is: this parasitic capacitance can add a pole and/or zero below
PD = 10V • 18.9mA + 52/(4(100Ω || 789Ω)) = 259mW 400MHz that can effect circuit operation. Keep resistor val-
Maximum TJ = +85°C + (0.26W • 150°C/W) = 124°C ues as low as possible, consistent with load driving consid-
erations. It has been suggested here that a good starting
All actual applications will operate at a lower junction tem-
point for design would be to set RG to 39.2Ω. Doing this
perature than the 124°C computed above. Compute your
automatically keeps the resistor noise terms low, and mini-
actual output stage power to get an accurate estimate of
mizes the effect of their parasitic capacitance. Transimped-
maximum junction temperature, or use the results shown
ance applications can use much higher resistor values. The
here as an absolute maximum.
compensation techniques described in this data sheet allow
excellent frequency response control, even with very high
BOARD LAYOUT feedback resistor values.
d) Connections to other wideband devices on the board
Achieving optimum performance with a high-frequency am-
can be made with short, direct traces or through onboard
plifier like the OPA847 requires careful attention to board
transmission lines. For short connections, consider the trace
layout parasitics and external component types. Recommen-
and the input to the next device as a lumped capacitive load.
dations that will optimize performance include:
Relatively wide traces (50mils to 100mils) should be used,
a) Minimize parasitic capacitance to any AC ground for all preferably with ground and power planes opened up around
of the signal I/O pins. Parasitic capacitance on the output and them. Estimate the total capacitive load and set RS from the
inverting input pins can cause instability: on the noninverting plot of Recommended RS vs Capacitive Load. Low parasitic
input, it can react with the source impedance to cause

OPA847 19
SBOS251E [Link]
capacitive loads (< 4pF) may not need an RS, since the almost impossible to achieve a smooth, stable frequency
OPA847 is nominally compensated to operate with a 2pF response. Best results are obtained by soldering the OPA847
parasitic load. Higher parasitic capacitive loads without an RS onto the board.
are allowed as the signal gain increases from +20V/V (in-
creasing the unloaded phase margin). If a long trace is INPUT AND ESD PROTECTION
required, and the 6dB signal loss intrinsic to a doubly-
The OPA847 is built using a very high-speed complementary
terminated transmission line is acceptable, implement a
bipolar process. The internal junction breakdown voltages are
matched impedance transmission line using microstrip or
relatively low for these very small geometry devices. These
stripline techniques (consult an ECL design handbook for
breakdowns are reflected in the Absolute Maximum Ratings
microstrip and stripline layout techniques). A 50Ω environ-
table. All device pins are protected with internal ESD protec-
ment is normally not necessary onboard and, in fact, a higher
tion diodes to the power supplies, as shown in Figure 17.
impedance environment improves distortion, as shown in the
distortion versus load plots. With a characteristic board trace
impedance defined based on board material and trace di- +VCC
mensions, a matching series resistor into the trace from the
output of the OPA847 is used, as well as a terminating shunt
resistor at the input of the destination device. Remember External Internal
also that the terminating impedance is the parallel combina- Pin Circuitry

tion of the shunt resistor and the input impedance of the

destination device; this total effective impedance should be
–VCC
set to match the trace impedance. If the 6dB attenuation of
a doubly-terminated transmission line is unacceptable, a FIGURE 17. Internal ESD Protection.
long trace can be series-terminated at the source-end only.
Treat the trace as a capacitive load in this case and set the These diodes provide moderate protection to input overdrive
series resistor value as shown in the plot of Recommended voltages above the supplies as well. The protection diodes
RS vs Capacitive Load. This does not preserve signal integ- can typically support 30mA continuous current. Where higher
rity as well as a doubly-terminated line. If the input imped- currents are possible (for example, in systems with ±15V
ance of the destination device is low, there will be some supply parts driving into the OPA847), current limiting series
signal attenuation due to the voltage divider formed by the resistors should be added into the two inputs. Keep these
series output into the terminating impedance. resistor values as low as possible, since high values degrade
e) Socketing a high-speed part like the OPA847 is not both noise performance and frequency response.
recommended. The additional lead length and pin-to-pin
capacitance introduced by the socket can create an ex-
tremely troublesome parasitic network that can make it

20
OPA847
[Link] SBOS251E
 Revision History

DATE REVISION PAGE SECTION DESCRIPTION

12/08 E 2 Absolute Maximum Ratings Changed minimum Storage Temperature Range from −40°C to −65°C.
4/06 D 15 Design-In Tools Board part number changed.

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

OPA847 21
SBOS251E [Link]
 PACKAGE OPTION ADDENDUM

[Link] 2-Nov-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

OPA847ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA Samples
847
OPA847IDBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OATI Samples

OPA847IDBVT ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OATI Samples

OPA847IDBVTG4 ACTIVE SOT-23 DBV 6 250 TBD Call TI Call TI -40 to 85 Samples

OPA847IDG4 ACTIVE SOIC D 8 75 TBD Call TI Call TI -40 to 85 Samples

OPA847IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA Samples
847

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

[Link] 2-Nov-2023

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

[Link] 2-Nov-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA847IDBVR SOT-23 DBV 6 3000 180.0 8.4 3.15 3.1 1.55 4.0 8.0 Q3
OPA847IDBVT SOT-23 DBV 6 250 180.0 8.4 3.15 3.1 1.55 4.0 8.0 Q3
OPA847IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

[Link] 2-Nov-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA847IDBVR SOT-23 DBV 6 3000 210.0 185.0 35.0
OPA847IDBVT SOT-23 DBV 6 250 210.0 185.0 35.0
OPA847IDR SOIC D 8 2500 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

[Link] 2-Nov-2023

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
OPA847ID D SOIC 8 75 506.6 8 3940 4.32

Pack Materials-Page 3
 PACKAGE OUTLINE
DBV0006A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

3.0 C
2.6
1.75 0.1 C
B A
1.45
PIN 1
INDEX AREA

1
6

2X 0.95
3.05
2.75
1.9 5
2

4
3
0.50
6X
0.25
0.15
0.2 C A B (1.1) TYP
0.00
1.45 MAX
0 -10

0.25
GAGE PLANE 0.22
TYP 0 -10
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

0 -10

-10 -10

ALTERNATIVE PACKAGE SINGULATION VIEW

4214840/D 09/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.

[Link]
 EXAMPLE BOARD LAYOUT
DBV0006A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
6X (1.1)
1

6X (0.6)
6

SYMM
2 5
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214840/D 09/2023

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

[Link]
 EXAMPLE STENCIL DESIGN
DBV0006A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
6X (1.1)
1

6X (0.6)
6

SYMM
2 5
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214840/D 09/2023

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

[Link]
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

[Link]
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

[Link]
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

[Link]
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