Federal Urdu University of Arts, Science & Technology Islamabad – Pakistan Electrical Engineering

THIRD SEMESTER

ELECTRONICS - II

BASIC ELECTRICAL & ELECTRONICS LAB

DEPARTMENT OF ELECTRICAL ENGINEERING

Prepared By: Checked By: Approved By:

Engr. Saqib Riaz Engr. [Link] Khan [Link] Jafri

Lecturer (Lab) Senior Lab Engineer Dean Electrical Department

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Federal Urdu University of Arts, Science & Technology Islamabad – Pakistan Electrical Engineering

Name: ____________________________________________

Registration No: ____________________________________

Semester: _________________________________________

Batch: ____________________________________________

FEDERAL URDU UNIVERSITY OF ARTS, SCIENCE & TECHNOLOGY

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Federal Urdu University of Arts, Science & Technology Islamabad – Pakistan Electrical Engineering

PRACTICAL LIST
[Link]. PRACTICAL NAME

01 Verification of the calculated value of a BJT amplifier

02 Implementation of OR gate using BJT’s

03 Determination of Input-offset voltage of LM-741

04 Implementation of the Buffer/Non-Inverting Amplifier using LM-741

05 Implementation of the Inverting Amplifier using LM-741

06 Implementation of the Summing Amplifier using LM-741

07 Frequency Response of Active Low Pass Filter

08 Frequency Response of Active High Pass Filter

09 Plot the Drain Characteristics of a JFET

10 Plot the Transfer Characteristics of a JFET

11 JFET Self Biased Network

12 JFET Voltage Divider Bias Network

13 Implementation of Common Source Amplifier using JFET

14 Implementation of Common Drain Amplifier using JFET

15 A-stable Operation of a 555 Timer

16 Mono-stable Operation of a 555 Timer

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Experiment # 01

VERIFICATION OF THE CALCULATED VALUES OF A BJT

AMPLIFIER
OBJECTIVE:
Understand and analyze the operation of common-emitter amplifiers.
APPARATUS:
• BJT (2N3904)
• AC/DC POWER SUPPLY
• BREAD BOARD
• CAPACITORS 10UF
• RESISTORS 57K, 3K
• MULTIMETER
• CONNECTING WIRES
INITIAL CONDITIONS:

IC = 2mA & VCE= VCC/2

CIRCUIT DIAGRAM:

Vcc
+

12V

RB 57k RC 3k
C2
V2
-1m/1mV
C1 10uF
Q1
1kHz 10uF 2N3904 1k
RL

Common Emitter Amplifier

PROCEDURE:

1. Connect the circuit as shown in circuit diagram

2. Use the multimeter to find out the type of transistor and the value of beta.
3. Set the initial condition for the circuit and calculate the value of Rc and RB.

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4. Use the following relationship

RC= (VCC-VCE)/IC

RB= (VCC-VBE)/IB

IC= βIB

5. Measure the Output Voltage Vo (p-p) for different values of input voltage Vin (p-p).
6. All the readings are tabulated and voltage gain in dB is calculated by using the expression
Av=20 log10 (V0/Vi)

CALCULATIONS:

Table No. 01:

S. No. Red Wire (+) Black Wire (-) Voltage

1 A B
2 B A
3 A C
4 C A
5 B C
6 C B

From voltage table:

Side A is __________ Side B is _________ Side C is _________

Transistor is __________.

Table No. 02:

Calculated Values Actual Values

RB RC RB RC

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Federal Urdu University of Arts, Science & Technology Islamabad – Pakistan Electrical Engineering

Table No. 03:

Gain Gain in dB
Input Signal Output Signal
AV=(V0/Vi) Av=20log10 (V0/Vi)

Input Signal 01

Output Signal 01

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Federal Urdu University of Arts, Science & Technology Islamabad – Pakistan Electrical Engineering

Input Signal 02

Output Signal 02

Input Signal 03

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Federal Urdu University of Arts, Science & Technology Islamabad – Pakistan Electrical Engineering

Output Signal 03

OBSERVATIONS:

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

Teacher’s Signature: ________________. Date: ___________________.

Teacher’s Name: Engr Saqib Riaz.

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Federal Urdu University of Arts, Science & Technology Islamabad – Pakistan Electrical Engineering

Experiment # 02

IMPLEMENTATION OF OR GATE USING BJT’S

OBJECTIVE:
Understand the working of digital OR gate. See how the truth table is constructed &
also understand the outputs of the OR gate.
APPARATUS:
• BJT (2N3904)
• DC POWER SUPPLY
• BREAD BOARD
• LED’s (Red & Green)
• RESISTORS 10K, 1K, 10K & 3.3K
• MULTIMETER
• CONNECTING WIRES
CIRCUIT DIAGRAM:
VCC 5V
+

RC1 1k
RC2 1k

RBB1 RBB2
Q1 Q2
2N3904 2N3904
100k 100k

+ +
VBB1 0/5V VBB2 0/5V
RE1 100 RE2 100

RL 10k

OR Gate using BJT’s

PROCEDURE:

1. Construct the circuit as shown above.

2. Clearly mark the inputs and outputs of the circuit
3. Apply the different possible combinations of the inputs to the circuit.
4. Construct the truth table for the inputs as well as for the outputs.
5. Verify the operation of the lab circuit.

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Truth Table for an OR gate:

Input A Input B Output Y

Table of results from the circuit:

Vin1 Vin2 Vout

Question: Draw the circuit diagram of AND gate using BJT’s? Also make truth table for it.

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OBSERVATIONS:

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

_______________________.

Teacher’s Signature: ________________. Date: ___________________.

Teacher’s Name: Engr Saqib Riaz.

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Federal Urdu University of Arts, Science & Technology Islamabad – Pakistan Electrical Engineering

EXPERIMENT # 03
DETERMINATION OF INPUT-OFFSET VOLTAGE OF OPAMP
LM 741
OBJECTIVE:
To sketch and briefly explain an operational amplifier circuit symbol and identify all
terminals.
To understand the pin configurations, specifications & functioning of LM741 opamp
used in the practical applications.
To reduce the offset voltage zero at the output.

APPARATUS:
• OPAMP LM741
• RESISTORS 100K
• DC POWER SUPPLY (+15,-15)
• MULTIMETER
• CONNECTING WIRES
PIN CONFIGURATION OF LM741 OPAMP:

SPECIFICATIONS:

1. Supply voltage:

µA 741A, µA 741, µA 741E ---------------- ±22V

µA 741C ---------------- ±18 V

2. Internal power dissipation

DIP package ----------------- 310 mw.

3. Differential input voltage ---------------- ±30 V.

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4. Operating temperature range

Military (µA 741A, µA 741) --------------- -550 to +1250 C.

Commercial (µA 741E, µA 741C) --------- 00 C to +700 C.

5. Input offset voltage ------------ 1.0 mV.

6. Input Bias current ------------ 80 nA.

7. PSSR --------------30µV/V.

8. Input resistance -------------2MΩ.

9. CMMR --------------90dB.

10. Output resistance ---------------75Ω.

11. Bandwidth --------------1.0 MHz.

12. Slew rate ---------------0.5 V/µ sec.

CIRCUIT DIAGRAM 1:

V1 15V
+
R3
100k

R1
100k U1
+ UA741

R2
100k Vout

V2 15V
+

PROCEDURE:

1. Connect the circuit as shown in the figure (1).

2. Make both the inputs inverting as well as non-inverting to ground.
3. Make sure that you have powered the chip with the dual power supply.
4. Measure the DC output voltage at pin 6 using multimeter and record the result in table 1.
5. Calculate the input offset voltage using the formula and record the value in table 1.

Vin = Vout/Av

6. Replace the 100 K resistance with 220 K and repeat the above steps.

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Federal Urdu University of Arts, Science & Technology Islamabad – Pakistan Electrical Engineering

Table 1:

Resistance Vout Vin

100 K

220 K

Elimination of the OFFSET voltage:

1. Connect the circuit as shown in the figure (2).

2. To eliminate this offset voltage connects the stationary ends of 5K potentiometer between
pin 1 & 5.
3. Use the pot, to zero the output of the amplifier this is how the offset voltage is eliminated.
4. In your experiment due to pot sensitivity, you may not get a full zero volt output. A 10
mV at the output will be sufficient.
5. Record the reading of voltage drop across the variable resistance that makes output zero
in the following table 2.

CIRCUIT DIAGRAM 2:

V1 15V
+
R3
100k

R1 U2
100k + UA748

R2
100k
Vout
+V
V2 15V
+

R4 10k 40%

Table 2:

Vin Vr Vout

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OBSERVATIONS:

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

_______________________.

Teacher’s Signature: ________________. Date: ___________________.

Teacher’s Name: Engr Saqib Riaz.

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Federal Urdu University of Arts, Science & Technology Islamabad – Pakistan Electrical Engineering

EXPERIMENT # 04
IMPLEMENTATION OF NON-INVERTING/BUFFER
AMPLIFIER BY USING LM741
OBJECTIVE:
Understand the op-amp as a voltage follower or buffer.
Analyze the non-inverting configuration & understand the closed loop gain.

APPARATUS:
• OP-AMP IC LM741
• RESISTOR 22K & 100K
• AC/DC POWER SUPPLIES
• OSCILLOSCOPE
• CONNECTING WIRES
CIRCUIT DIAGRAM:

V1 15V
+

V3 U1
-2/2V + UA741

1kHz

RL 10k

V2 15V
+

PROCEDURE:

1. Construct the buffer amplifier circuit as shown in the figure.

2. Connect AC input signal at the non-inverting end of the amplifier i.e +ve end.
3. Use the oscilloscope to observe the input as well as the output signal.
4. Compute the voltage gain by the following formula.

AV = VOUT/VIN = 1 + RF/RIN

5. Sketch the observed input & output waveforms.

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Calculations:

Table

Input Signal Output Signal Calculated Measured Difference

(VP-P) (VP-P) Voltage Gain Voltage Gain
AV AV

Calculation of the waveform:

input Signal

Output Signal

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CIRCUIT DIAGRAM:

V1 15V
+

V3 U1
-2/2V + UA741

1kHz
Rf
100k
Rin 22k
RL 10k

V2 15V
+

PROCEDURE:

1. Construct the non-inverting amplifier circuit as shown in the above figure.

2. Connect AC input signal at the non-inverting end of the amplifier i.e +ve end.
3. Use the oscilloscope to observe the input as well as the output signal.
4. Compute the voltage gain by the following formula.

AV = VOUT/VIN = 1 + RF/RIN

5. Sketch the observed input & output waveforms.

Calculations:

Table

Input Signal Output Signal Calculated Measured Difference

(VP-P) (VP-P) Voltage Gain Voltage Gain
AV AV

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Input Signal

Output Signal

OBSERVATIONS:

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

Teacher’s Signature: ________________. Date: ___________________.

Teacher’s Name: Engr Saqib Riaz.

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Federal Urdu University of Arts, Science & Technology Islamabad – Pakistan Electrical Engineering

EXPERIMENT # 05
IMPLEMENTATION OF INVERTING AMPLIFIER BY USING
LM741
OBJECTIVE:
Analyze the inverting configuration & understand the voltage gain.

APPARATUS:
• OP-AMP IC LM741
• RESISTOR 22K & 100K
• AC/DC POWER SUPPLIES
• OSCILLOSCOPE
• CONNECTING WIRES
CIRCUIT DIAGRAM:

V3 V1 15V
-2/2V +
Rin
U1
22k + UA741
1kHz

Rf
100k
RL 10k
V2 15V
+

PROCEDURE:

1. Construct the inverting amplifier circuit as shown in the figure.

2. Connect AC input signal at the inverting end of the amplifier i.e -ve end.
3. Use the oscilloscope to observe the input as well as the output signal.
4. Compute the voltage gain by the following formula.

AV = VOUT/VIN = - RF/RIN

5. Sketch the observed input & output waveform

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Calculations:

Table:

Input Signal Output Signal Calculated Measured Difference

(VP-P)/Freq. (VP-P)/Freq. Voltage Gain Voltage Gain
AV AV

Input Signal

Output Signal

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Federal Urdu University of Arts, Science & Technology Islamabad – Pakistan Electrical Engineering

Input Signal

Output Signal

OBSERVATIONS:

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

Teacher’s Signature: ________________. Date: ___________________.

Teacher’s Name: Engr Saqib Riaz.

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Federal Urdu University of Arts, Science & Technology Islamabad – Pakistan Electrical Engineering

EXPERIMENT # 06
IMPLEMENTATION OF SUMMING INVERTING AMPLIFIER
BY USING LM741
OBJECTIVE:
Analyze the operation of summing amplifiers & how to achieve any specified gain
greater than unity
APPARATUS:
• OP-AMP IC LM741
• RESISTOR 10K, 22K & 100K
• AC/DC POWER SUPPLIES
• OSCILLOSCOPE
• CONNECTING WIRES
CIRCUIT DIAGRAM:
V4
-1/1V
Rin1
22k V1 15V
1kHz +

V3 U1
-1/1V + UA741
Rin
22k
1kHz
Rf
50k
RL 10k

V2 15V
+

Summing Inverting Amplifier

PROCEDURE:

1. Construct the summing inverting amplifier circuit as shown in the figure.

2. Connect at least two AC input signal at the inverting end of the amplifier i.e -ve end.
3. Use the oscilloscope to observe the input as well as the output signal.
4. Compute the voltage gain by the following formula.

AV = VOUT/VIN = - {Rf/Rin1+Rf/Rin2}

5. Sketch the observed input & output waveforms.

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Calculations:

Table:

Input Signal Output Signal Calculated Measured Difference

(VP-P)/Freq. (VP-P)/Freq. Voltage Gain Voltage Gain
AV AV

Vin1

Vin2

Calculation of the waveform:

Input Signal 1

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Federal Urdu University of Arts, Science & Technology Islamabad – Pakistan Electrical Engineering

Input Signal 2

Output Signal

OBSERVATIONS:
______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

Teacher’s Signature: ________________. Date: ___________________.

Teacher’s Name: Engr Saqib Riaz.

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Federal Urdu University of Arts, Science & Technology Islamabad – Pakistan Electrical Engineering

EXPERIMENT # 07
FREQUENCY RESPONSE OF ACTIVE LOW PASS FILTER
OBJECTIVE:
Describe the gain-versus-frequency responses of the basic filters & explain the low-pass
response.
APPARATUS:
• OP-AMP IC LM741
• RESISTOR 10K, 22K & 100K
• AC/DC POWER SUPPLIES
• OSCILLOSCOPE
• CONNECTING WIRES
CIRCUIT DIAGRAM:

V1 15V
+

V4 U1
-1/1V + UA741
R1
10k
1kHz
Rf
100k
RL 10k
C1 .1uF
V2 15V
Rin 22k +

Active Low Pass Filter

PROCEDURE:

1. Construct the active low pass filter circuit as shown in the figure.
2. Connect AC input signal at the non-inverting end of the amplifier i.e +ve end.
3. Use the oscilloscope to observe the input as well as the output signal.
4. Increase the input signal frequency in steps from 1KHz to 1MHz & Observe the
corresponding output voltage of the filter and tabulate the results.
5. Compute the voltage gain by the following formula.

AV = VOUT/VIN = (AF)/√1+(f/fc)2

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Federal Urdu University of Arts, Science & Technology Islamabad – Pakistan Electrical Engineering

Where,
AF= the pass band gain of the filter (1+Rf/Rin)
f = the frequency of the input signal
fc = the cut-off frequency (fc=1/2πRC)

6. Plot the frequency response curve of the low pass filter with the experimental results
obtained & compare it with the expected waveform.

Table:

Vin Vout GAIN

Input
Frequency(Fin) Input volatage in Output Voltage Vout / Vin 20 Log (Vout / Vin)
in Hz volts Magnitude in dB
in volts

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Calculation of the waveform:

Output Signal Frequency vs Gain in dB

OBSERVATIONS:
______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

Teacher’s Signature: ________________. Date: ___________________.

Teacher’s Name: Engr Saqib Riaz.

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Federal Urdu University of Arts, Science & Technology Islamabad – Pakistan Electrical Engineering

EXPERIMENT # 08
FREQUENCY RESPONSE OF ACTIVE HIGH PASS FILTER
OBJECTIVE:
Explain the high-pass response & determine the critical frequency of a high-pass filter.
APPARATUS:
• OP-AMP IC LM741
• RESISTOR 10K, 22K & 100K
• AC/DC POWER SUPPLIES
• OSCILLOSCOPE
• CONNECTING WIRES
CIRCUIT DIAGRAM:

V1 15V
+

V4 U1
-1/1V C1 + UA741
.1uF

10 Hz
Rf
100k
RL 10k
R1 10k
V2 15V
Rin 22k +

Active High Pass Filter

PROCEDURE:

1. Construct the active high pass filter circuit as shown in the figure.
2. Connect AC input signal at the non-inverting end of the amplifier i.e +ve end.
3. Use the oscilloscope to observe the input as well as the output signal.
4. Increase the input signal frequency in steps from 1KHz to 1MHz & Observe the
corresponding output voltage of the filter and tabulate the results.
5. Compute the voltage gain by the following formula.

AV = VOUT/VIN = AF(f/fc)/√1+(f/fc)2

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Federal Urdu University of Arts, Science & Technology Islamabad – Pakistan Electrical Engineering

Where,
AF= the pass band gain of the filter (1+Rf/Rin)
f = the frequency of the input signal
fc = the cut-off frequency (fc=1/2πRC)

6. Plot the frequency response curve of the low pass filter with the experimental results
obtained & compare it with the expected waveform.

Table:

Vin Vout GAIN

Input
Frequency(Fin) Input volatage in Output Voltage Vout / Vin 20 Log (Vout / Vin)
in Hz volts Magnitude in dB
in volts

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Calculation of the waveform:

Output Signal Frequency vs Gain in dB

OBSERVATIONS:
______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

Teacher’s Signature: ________________. Date: ___________________.

Teacher’s Name: Engr Saqib Riaz.

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Federal Urdu University of Arts, Science & Technology Islamabad – Pakistan Electrical Engineering

EXPERIMENT # 09
PLOT THE DRAIN CHARACTERISTICS OF JFET
OBJECTIVE:
Explain ohmic area, constant current area and breakdown. Also explain pinch-off voltage.
APPARATUS:
• JFET KS-192
• RESISTOR 1K & 1M
• DC POWER SUPPLIES
• MULTIMETER
• CONNECTING WIRES
CIRCUIT DIAGRAM:
Rd
1k

Rg Q1
1M 2N5457
+
10V VDD
+
VGS 0V,-2V
Rs 470 ohm

PROCEDURE:

1. Construct the circuit diagram as shown above.

2. Set VGS=0V & measured ID=VRD/RD.
3. As VGS=0V, therefore the resulting drain current is IDSS with VGS=0V.
4. Slowly increase VDD to 3V & measure VDS and ID.
5. Increase VDD to 6V & measure VDS and ID.
6. Take couple of more measurements by increasing the value of VDD.
7. Plot the resulting curve between VDS & ID.
8. Repeat the same procedure with VGS = -2V.

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Table for VGS = 0V:

VDD(V) Calculated Measured VDS(V)

ID(mA) ID(mA)

03

06

09

12

15

Table for VGS = -2V:

VDD(V) Calculated Measured VDS(V)

ID(mA) ID(mA)

03

06

09

12

15

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Calculations:

VDS vs ID

OBSERVATIONS:
______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

Teacher’s Signature: ________________. Date: ___________________.

Teacher’s Name: Engr Saqib Riaz.

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Federal Urdu University of Arts, Science & Technology Islamabad – Pakistan Electrical Engineering

EXPERIMENT # 10
PLOT THE TRANSFER CHARACTERISTICS OF JFET
OBJECTIVE:
Analyze a JFET transfer characteristic curve & Use the equation for the transfer
characteristic to calculate ID also calculate transconductance.
APPARATUS:
• JFET KS-192
• RESISTOR 1K & 1M
• DC POWER SUPPLIES
• MULTIMETER
• CONNECTING WIRES
CIRCUIT DIAGRAM:
Rd
1k

Rg Q1
1M 2N5457
+
10V VDD
+
VGS 0V,-2V
Rs 470 ohm

PROCEDURE:

1. Construct the circuit diagram as shown above.

2. Set VGS=0V & VDD = 10V at this point measure the drain current ID.
3. Slowly increase VGS to -1V & VDD = 10V measure ID.
4. Take couple of more measurements by increasing the value of VGS.
5. Measures drain current & transconductance by using following equation.

ID = IDSS (1 – VGS/VGS (off)) 2……………. (1)

gm = ∆ID/∆VGS ……………. (2)

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Table for VDD = 10V:

VGS(V) Measured

ID(mA)

-1

-2

-3

-4

-5

Calculations:

VGS vs ID

OBSERVATIONS:
______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

Teacher’s Signature: ________________. Date: ___________________.

Teacher’s Name: Engr Saqib Riaz.

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Federal Urdu University of Arts, Science & Technology Islamabad – Pakistan Electrical Engineering

EXPERIMENT # 11
JFET SELF BIASED NETWORK
OBJECTIVE:
Analyze JFET bias circuits & self-biased JFET circuit. Set the self-biased Q-point
APPARATUS:
• JFET KS-192
• RESISTOR 1K, 220Ω & 10M
• DC POWER SUPPLIES
• MULTIMETER
• CONNECTING WIRES
CIRCUIT DIAGRAM:

RD
1k

+ VDD
Q1 15V
2N5457

RG 10M
RS
220

PROCEDURE:

1. Construct the circuit diagram as shown above.

2. Set VGS=0V & VDD = 15V at this point measure the drain current ID.
3. Slowly decrease the value of VDD = 10V measure ID.
4. Take couple of more measurements by decreasing the value of VDD.
5. Calculate VS by the following formula:

VS = IDRS

6. Calculate drain-source voltage by the following formula.

VDS = VDD – ID (RD+RS)

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Table at VGS = 0V:

Drain Drain Calculated Calculated Measured

Voltage Current Source Drain-Source Drain-
Measured Voltage Voltage Source
VDD Voltage
ID VS VDS
VDS

15

10

Calculations:

VGS vs ID

OBSERVATIONS:

______________________________________________________________________________

______________________________________________________________________________

Teacher’s Signature: ________________. Date: ___________________.

Teacher’s Name: Engr Saqib Riaz.

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Federal Urdu University of Arts, Science & Technology Islamabad – Pakistan Electrical Engineering

EXPERIMENT # 12
JFET VOLTAGE DIVIDER BIASED NETWORK
OBJECTIVE:
Analyze JFET bias circuits & the effect of parallel resistance on JFET circuit.
APPARATUS:
• JFET KS-192
• RESISTOR 1M, 2.2K, 3.3K & 10M
• DC POWER SUPPLIES
• MULTIMETER
• CONNECTING WIRES
CIRCUIT DIAGRAM:

RD
3.3k
R1 6.8M

+ VDD
Q1 15V
2N5457

R2 1M
RS
2.2k

PROCEDURE:

1. Construct the circuit diagram as shown above.

2. Set VGS=0V & VDD = 15V at this point measure the drain current ID.
3. Calculate VS by the following formula:

VS = IDRS

4. Calculate gate voltage VG & VGS by the following formula:

VG = (R2/ (R1 + R2)) * VDD

VGS = VG - VS

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Table at VGS = 0V:

Gate- Drain Drain Calculated Calculated Gate Calculated

Source Voltage Current Source Voltage Gate-Source
Voltage Measured Voltage Voltage
VDD VDS
VGS ID VS VGS

0 15

OBSERVATIONS:
______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

Teacher’s Signature: ________________. Date: ___________________.

Teacher’s Name: Engr Saqib Riaz.

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Federal Urdu University of Arts, Science & Technology Islamabad – Pakistan Electrical Engineering

EXPERIMENT # 13
COMMON SOURCE AMPLIFIER OF JFET
OBJECTIVE:
Explain and analyze the operation of common-source FET amplifiers.
APPARATUS:
• JFET KS-192
• RESISTOR 1M, 2.2K, 1K & 10K
• CAPACITOR 0.01uF, 1uF & 10uF
• AC/DC POWER SUPPLIES
• MULTIMETER
• CONNECTING WIRES
CIRCUIT DIAGRAM:

RD 2.2k

C2

1uF + V2
C1 10V
Q1
V1 2N5457
-1/1V 0.01uF

R1
1k RL 10k
1kHz

C3 10uF
RS 1k

PROCEDURE:

1. Construct the circuit diagram as shown above.

2. Set VIN=1Vp-p & VDD = 12V.
3. Measure the Output Voltage Vo (p-p) for different values of input voltage Vin (p-p).
4. Voltage gain of the common source amplifier is given by:
AV = gm RD
5. The output signal voltage VDS at the drain is:

Vout = VDS = AVVGS

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Table :

Gain Gain in dB
Input Signal Output Signal
AV=(V0/Vi) Av=20log10 (V0/Vi)

Calculation of the waveform:

Input Signal 01

Output Signal 01

Output Signal 01

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Input Signal 02

Output Signal 02

OBSERVATIONS:

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

Teacher’s Signature: ________________. Date: ___________________.

Teacher’s Name: Engr Saqib Riaz.

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Federal Urdu University of Arts, Science & Technology Islamabad – Pakistan Electrical Engineering

EXPERIMENT # 14
COMMON DRAIN AMPLIFIER OF JFET
OBJECTIVE:
Explain and analyze the operation of common-drain FET amplifiers.
APPARATUS:
• JFET KS-192
• RESISTOR 1M, 2.2K, 1K & 10K
• CAPACITOR 0.01uF & 10uF
• AC/DC POWER SUPPLIES
• MULTIMETER
• CONNECTING WIRES
CIRCUIT DIAGRAM:

RD 2.2k

+ V2
C1 10V
Q1
V1 2N5457
-1/1V 0.01uF
C3
R1
1k 1uF
100kHz
RL 10k
RS 1k

PROCEDURE:

1. Construct the circuit diagram as shown above.

2. Set VIN=1Vp-p & VDD = 12V.
3. Measure the Output Voltage Vo (p-p) for different values of input voltage Vin (p-p).
4. Voltage gain of the common source amplifier is given by:
AV = gm RS / 1 + gm RS

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Table :

Gain Gain in dB
Input Signal Output Signal
AV=(V0/Vi) Av=20log10 (V0/Vi)

Calculation of the waveform:

Input Signal 01

Output Signal 01

Input Signal 01

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IntPut Signal 02

Output Signal 02

Output Signal 02

OBSERVATIONS:

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

Teacher’s Signature: ________________. Date: ___________________.

Teacher’s Name: Engr Saqib Riaz.

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Federal Urdu University of Arts, Science & Technology Islamabad – Pakistan Electrical Engineering

EXPERIMENT # 15
A-STABLE OPERATION OF 555 TIMER
OBJECTIVE:
To investigate the operation of 555 timer in the A-Stable mode
APPARATUS:
• LM 555
• RESISTORS
• CAPACITORS
• DC POWER SUPLLY
• DIGITAL MULTIMETER
• OSCILLOSCOPE
OPERATION:
A-stable circuit produces a 'square wave’; this is a digital waveform with sharp
transitions between low (0V) and high (+Vs). Note that the durations of the low and high states
may be different. The circuit is called an A-stable because it is not stable in any state the output
is continually changing between 'low' and 'high'.
The time period (T) of the square wave is the time for one complete cycle, but it is
usually better to consider frequency (f) which is the number of cycles per second.

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T = time period in seconds (s)

f = frequency in hertz (Hz)
R1 = resistance in ohms (Ω)

T = 0.7 × (R1 + 2R2) × C1 and f = 1.4 (R1 + 2R2) × C1

R2 = resistance in ohms ( )
C1 = capacitance in farads (F)
The time period can be split into two parts: T = Tm + Ts

Mark time: (output high): Tm = 0.7 × (R1 + R2) × C1

Space time: (output low): Ts = 0.7 × R2 × C1

Many circuits require Tm and Ts to be almost equal; this is achieved if R2 is much larger
than R1. For a standard a-stable circuit Tm cannot be less than Ts, but this is not too restricting
because the output can both sink and source current. For example an LED can be made to flash
briefly with long gaps by connecting it (with its resistor) between +Vs and the output.
This way the LED is on during Ts, so brief flashes are achieved with R1 larger than R2,
making Ts short and Tm long. Tm must be less than Ts a diode can be added to the circuit as
explained under duty cycle below.

Choosing R1, R2 and C1:

R1 and R2 should be in the range 1k to 1M. It is best to choose C1 first because
capacitors are available in just a few values.
Choose C1 to suit the frequency range you require (use the table as a guide).
Choose R2 to give the frequency (f) you require. Assume that R1 is much smaller than
R2 (so that Tm and Ts are almost equal), then you can use:

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R2 = 0.7
f × C1

Choose R1 to be about a tenth of R2 (1k min.) unless you want the mark time Tm to be
significantly longer than the space time Ts. If you wish to use a variable resistor it is best to
make it R2. If R1 is variable it must have a fixed resistor of at least 1k in series (this is not
required for R2 if it is variable). A-stable operation
With the output high (+Vs) the capacitor C1 is charged by current flowing through R1 and R2.
The threshold and trigger inputs monitor the capacitor voltage and when it reaches 2/3Vs
(threshold voltage) the output becomes low and the discharge pin is connected to 0V.
The capacitor now discharges with current flowing through R2 into the discharge pin.
When the voltage falls to 1/3Vs (trigger voltage) the output becomes high again and the
discharge pin is disconnected, allowing the capacitor to start charging again.
This cycle repeats continuously unless the reset input is connected to 0V which forces the
output low while reset is 0V. A-stable can be used to provide the clock signal for circuits such as
counters.
A low frequency A-stable (< 10Hz) can be used to flash an LED on and off, higher
frequency flashes are too fast to be seen clearly. Driving a loudspeaker or piezo transducer with a
low frequency of less than 20Hz will produce a series of 'clicks' (one for each low/high
transition) and this can be used to make a simple metronome.
An audio frequency A-stable (20Hz to 20 kHz) can be used to produce a sound from a
loudspeaker or piezo transducer. The sound is suitable for buzzes and beeps. The natural
(resonant) frequency of most piezo transducers is about 3 kHz and this will make them produce a
particularly loud sound.

OBSERVATIONS:

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

Teacher’s Signature: ________________. Date: ___________________.

Teacher’s Name: Engr Saqib Riaz.

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Federal Urdu University of Arts, Science & Technology Islamabad – Pakistan Electrical Engineering

EXPERIMENT # 16
MONOSTABLE OPERATION OF 555 TIMER
OBJECTIVE:
To investigate the operation of 555 timer in the Mono-Stable mode
APPARATUS:
• LM 555
• RESISTORS
• CAPACITORS
• DC POWER SUPLLY
• DIGITAL MULTIMETER
• OSCILLOSCOPE
OPERATION:
A Mono-stable circuit produces a single output pulse when triggered. It is called a Mono-
stable because it is stable in just one state: 'output low'. The 'output high' state is temporary. The
duration of the pulse is called the time period (T) and this is determined by resistor R1 and
capacitor C1: time period,
T = 1.1 × R1 × C1
T = time period in seconds (s)
R1 = resistance in ohms (Ω)
C1 = capacitance in farads (F)
The maximum reliable time period is about 10 minutes. Why 1.1? The capacitor charges
to 2/3 = 67% so it is a bit longer than the time constant (R1 × C1) which is the time taken to
charge to 63%.
Choose C1 first (there are relatively few values available).
Choose R1 to give the time period you need. R1 should be in the range 1k to 1M, so use a
fixed resistor of at least 1k in series if R1 is variable. Beware that electrolytic capacitor values
are not accurate; errors of at least 20% are common. Beware that electrolytic capacitors leak
charge which substantially increases the time period if you are using a high value resistor - use
the formula as only a very rough guide!
For example the Timer Project should have a maximum time period of 266s (about 4½
minutes), but many electrolytic capacitors extend this to about 10 minutes!

The timing period is triggered (started) when the trigger input (555 pin 2) is less than 1/3
Vs, this makes the output high (+Vs) and the capacitor C1 starts to charge through resistor R1.
Once the time period has started further trigger pulses are ignored. The threshold input (555 pin
6) monitors the voltage across C1 and when this reaches 2/3 Vs the time period is over and the
output becomes low. At the same time discharge (555 pin 7) is connected to 0V, discharging the
capacitor ready for the next trigger. The reset input (555 pin 4) overrides all other inputs and the
timing may be cancelled at any time by connecting reset to 0V, this instantly makes the output
low and discharges the capacitor. If the reset function is not required the reset pin should be
connected to +Vs.

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Power-on reset or trigger:

It may be useful to ensure that a mono-stable circuit is reset
or triggered automatically when the power supply is connected or
switched on. This is achieved by using a capacitor instead of (or in
addition to) a push switch as shown in the diagram. The capacitor
takes a short time to charge, briefly holding the input close to 0V
when the circuit is switched on. A switch may be connected in
parallel with the capacitor if manual operation is also required.
This arrangement is used for the trigger in the Timer Project.

Edge-triggering:
If the trigger input is still less than 1/3 Vs at the end of the
time period the output will remain high until the trigger is greater
than 1/3 Vs. This situation can occur if the input signal is from an
on-off switch or sensor. The Mono-stable can be made edge
triggered, responding only to changes of an input signal, by
connecting the trigger signal through a capacitor to the trigger
input. The capacitor passes sudden changes (AC) but blocks a
constant (DC) signal. For further information please see the page
on capacitance. The circuit is 'negative edge triggered' because it
responds to a sudden fall in the input signal. The resistor between
the trigger (555 pin 2) and +Vs ensures that the trigger is
normally high (+Vs).

OBSERVATIONS:

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

______________________________________________________________________________

Teacher’s Signature: ________________. Date: ___________________.

Teacher’s Name: Engr Saqib Riaz.

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