ISSN 2249-6343

International Journal of Computer Technology and Electronics Engineering (IJCTEE)

Volume 2, Issue 2

Implementation of Module Based Partial

Reconfigurable Multiplier
Sameer Ashtekar, Pravin Kshirsagar, Roshan Bhaiswar

Abstract – A reconfigurable structure allows us to provide a Media (video, audio, graphics, and communication)
large number of resources that can be used in different ways by processing applications have recently received significant
different applications. This paper presents the design attentions. To achieve real time processing of media signal
methodology of reconfigurable array multipliers. An 8-bit processing, efficient reconfigurable computational elements
reconfigurable multiplier can execute one 8-bit and two 4-bit
such as adders, multipliers, and multiplier-accumulators
multiplications depending upon three control signals. The
hardware overhead includes 192 two-input AND gates and 3 (MACS) are needed [4]. An 8-bit reconfigurable
control signals. Comparing with the original 8-bit array computational element can execute one 8-bit & two 4-bit
multiplier which requires 4032 Full Adders and 4096 two-input computations depending upon partitioning signals. Based on
AND gates, the hardware overhead is very small. With fast addition algorithms, a number of Reconfigurable adders
additional metal lines for interconnections, the hardware and array multipliers have been proposed. This paper
overhead will not increase the chip area. In other words, the presents the design methodology of reconfigurable array
high re-configurability of the developed circuit is achieved with multipliers. It should be mentioned that a configurable
negligible hardware overhead and virtually no performance multiplier blocks was developed for embedding in FPGAs [2,
overhead. The reconfigurable structure continues to use the
6, 7]. Each block is a 4 x 4 array multip1ier:An array of these
conventional array multiplier with minor changes.
Index Terms : Reconfiguration, Multiplier, FPGA. blocks is capable of being configured to perform 4m bit x 4n
bit signed unsigned binary multiplication. Since each block is
I. INTRODUCTION a 4 x 4 array multiplier, it inherent has a ripple carry adder. In
Conventionally there are two ways to performed computation addition, additional gates are needed to achieve the
Hardware based computation and Software based configurations and additional control signals are also needed.
[Link] based method uses application In other words, the programmability is achieved at the cost of
specific integrated circuits (ASICs) and application specific higher gate count and more delay degradation [5, 8]. In this
instruction set processors (ASIPs) to perform critical approach, a larger multiplier is cascaded from smaller blocks,
[Link] the other hand second method uses general purpose while our approach goes the other way around, i.e., a larger
processor or microcontroller based [Link] from multiplier is partitioned into a number of smaller multiplier.
performance point of view in term of area,speed and power Therefore, the developed approach offers three salient
they are far away from ASICs/[Link] features: (a) low area overhead; (b) virtually no performance
computing blends the benefits of both hardware and software. degradation; and (c) low power dissipation for executing
smaller multipliers. In the next section, module based partial
FPGAs are programmable logic devices that permit the reconfiguration is discussed. Section 3 presents basics of
implementation of digital systems. They provide an array of array multiplier. Implementation strategy is presented in
logic cells that can be configured to perform a given section 4. Section 5 gives the conclusion of the concept and
functionality by means of a configuration bit stream. Many of work.
FPGA systems can only be statically configured. Static
reconfiguration means to completely configure the device II. MODULE -BASED P ARTIAL RECONFIGURATION
before system execution. If a new reconfiguration is required,
it is necessary to stop system execution and reconfigure the 2.1 Reconfiguration module overview
device it over again. Some FPGAs allow performing partial
reconfiguration, where a reduced bit stream reconfigures only Partial reconfiguration involves defining distinct portions of
a given subset of internal components. Dynamic Partial an FPGA design to be reconfigurable
Reconfiguration (DPR) allows the part of device be modified While remaining portion of the device remain active. These
while the rest of the device (or system) continues to operate portions are referred to as reconfigurable modules
and unaffected by the reprogramming [1]. Reconfigurable modules have some following properties

88
 ISSN 2249-6343
International Journal of Computer Technology and Electronics Engineering (IJCTEE)
Volume 2, Issue 2
1) The reconfigurable module height is always the full height
of the device. 1) The floorplanning of module areas:

2) The Reconfigurable module width ranges from a minimum a) A four slice minimum width.
of four slices to maximum full device width, in four-device b) A set width that is always a multiple of four slices.
width, in four-slice increments.
2) The floorplanning of alls IOBs:
3) Horizontal placement must always be on a four-slice a) Shall be wholly contained within the “columnar space” of
boundary; the leftmost placement being x=0, 4, 8…. their associated reconfigurable module. No intermixing
between columnar regions is allowed.
4) Clocking logic (BUFGMUX, CLKIOBs) is always b) All IOBs must be locked down to exact sites.
separate from from the reconfigurable module clocks have 3) The floorplanning of all globle logic:
separate bit stream frames.
a) Logic that is not part of a lower level module must be
5) IOBs immediately above the top edge and below the constrained to specific sites in the device via LOC
bottom edge of a reconfigurable module are part of the [Link] floorplanning tool can be used.
specific reconfigurable module‟s resources.
b) There must be no unconstrained top-level logic.
6) A reconfigurable boundary cannot be changed,
communicate with other module by using special bus Macro. 2) Active module implementation: In this phase, the team
members implement the reconfigurable modules, that is the
7) To help minimize problems related to design design has been synthesized, floorplanning, and constrained.
complexity,the number of reconfigurable modules should be Each module will be implemented separately, but always in
minimized. the context of the top-level logic and constrained. Bitstreams
will be generated for all reconfigurable modules
8) The implementation must be designed so that the static
portions of the design do not rely on the state of module 3) Final assembly: In the phase, the team leader assembles
under reconfiguration while reconfiguration is taking and implements the top-level design using each submodule
[Link] implementation should ensure proper operation of and generates top-module bit stream [9, 10].This is the
the design during the reconfiguration process. process of combining each of the individual modules back in
a complete FPGA [Link] placement and routing
2.2 Modular Design achieved during the active implementation phase for each
module will be preserved, there by maintaining the
The modular design flow allows the designer to split the performance of each module.
whole system into modules. For each module, the designer
generates a configuration bit stream starting from an HDL 2. 2 Module-Based Partial Reconfiguration
description and going through the synthesis, mapping,
placement, and routing procedures, independently of other Module-based partial reconfiguration method is a special
modules [2]. The modular design flow consists of „Modular case of modular design [3]. And this method can reconfigure
Design Entry / Synthesis‟ and „Modular Design only a given subset of internal components during device is
Implementation‟. „Modular Design Entry and Synthesis‟ step activating. A complete initial bit stream must be generated,
must be done for top-level design and the modules. Top-level and then, partial bit steams generated for each reconfigurable
design is designed by team leader and consists of „black box‟ module. Fig. 1 shows the design flow of module-based partial
for each sub-modules and „wiring‟ for interconnection of reconfiguration. Hardwired Bus Macros must be included in
each sub-modules. „Modular Design Implementation‟ step design as shown in Fig. 2. These macros guarantee that each
comprises following three phases. time partial reconfiguration is performed routing channels
between modules remain unchanged, avoiding contentions
1) Initial budget phase: In this phase, the team leader assigns inside the FPGA and keeping correct intermodule
top-level constraints to the top-level design. Top-level connections [6, 8].
constraint needs to area constraint and bus macro
[Link] initial budgeting phase has the following
main steps:

89
 ISSN 2249-6343
International Journal of Computer Technology and Electronics Engineering (IJCTEE)
Volume 2, Issue 2
The operation of a 4-bit multiplication is shown below,
where the two operands are A and B. The operation
contains all 16 partial product bits of the form properly
aligned. The partial product in the first row is added to that in
the second row, and so on. The final product is P [9, 12].
Following is the dot notation for the Wallace tree
multiplication and partial product matrix for two 4 bit
numbers X and Y.

Figure 3: 4x4 Multipler Dot-Notation

Where Zij = XiYj

Figure 1: Design flow of module-based partial reconfiguration

Figure 4: 4x4 Array Multiplier

IV. IMPLEMENTATION

4.1 HDL Coding and Synthesis

This step is composed to following two phases [14]:
• Top module design:
In this phase, designer must consider each sub-module
interconnection, area assignment and bus macro assignment.
• Reconfigurable sub-module design:
This phase is same to traditional HDL design method.
Figure 2: Hardwired Bus Macros But designer must consider Input and Output assign rule for
Section III partial reconfiguration.
4.2 Implementation
Array Multipliers • Initial Budget:

90
 ISSN 2249-6343
International Journal of Computer Technology and Electronics Engineering (IJCTEE)
Volume 2, Issue 2
This step is a sequence of top module design. In this step, • Final module assemble: In this step, designer assembles one
designer must do bus macro manual setting, sub module area system from partially generated modules. All partial modules
constraint by using floor planner and top module IOB generated in active module implementation step are
assignment. Fig. 5 describes area constraint though floor combined to the top-level module [11].
planner. Bus macro is limited by target size. Through
equation (1), designer can estimate maximum usable bus V. CONCLUSIONS
macro. MaxBus = 4 * row CLB (1) We have presented a novel Reconfigurable Multiplier Array
If designer needs area optimization, optimized area can be organization. The proposed unit can be implemented on a
estimated in a synthesis step. VLSI intended to be used as a run time configurable unit, and
An optimized width equation is described by it can also be used in a reconfigurable technology as a run
time reconfigurable unit. The whole array is configured using
multiplexors, which can be replaced with faster connections
on a partially reconfigurable environment. Several units are
been coded and synthesized to have a wide comparison
environment, furthermore, a brief analysis of the obtained
results in terms of area used and time delay are presented
given a maximum work frequency of 50 MHz for the
calculus for a 4x4 macro-block and multiplier operations in a
SPARTAN XC3S400 device using a 3% of the available
slices of the chosen FPGA.

REFERENCES
[1] A. D. Booth. A Signed Binary Multiplication Technique.
Quarterly Journal of Mechanics and Applied Mathematics,
4(2):236–240, June 1951.
[2] Nan Y S, Chen O T .Low-power multipliers by minimizing
Figure 5: Tap Diagram for 4x4 multiplier
switching activities of partial products. IEEE International
Symposium on Circuits and Systems[C]. Arizona,USA. IEEE
Circuits and Systems Society ,2002.
[3] H. Ling. High-Speed Binary Adder. IBMJournal of Research
and Development, 25(2and 3):156–166, May 1981.
[4] L. Dadda. Some Schemes for Parallel Multipliers. Alta
Frequenza, 1965.
[5] Magnus Sjalander, Per Larsson Edefors, Multiplication
Acceleration Through Twin Precision. IEEE Trans. VLSI., vol.
17, pp.1233–1246, Sep. 2009.
[6] H. Eriksson, P. Larsson-Edefors, M. Sheeran, M. Själander, D.
Johansson, and M. Schölin, “Multiplier reduction tree with
logarithmic logic depth and regular connectivity,” in Proc. IEEE
Int. Symp. Circuits Syst. (ISCAS), May 2006, pp. 4–8
[7] whitney J. Townsend, Earl [Link], and jocob
Figure 6: Floor planning for multiplier [Link] “A Comparison of Dadda and Wallace multiplier
delays”.
Where slice is a maximum slice number estimated in a [8] C. R. Baugh and B. A. Wooley, “A two‟s complement parallel
synthesis step and row is a target row size. array multiplication algorithm,” IEEE Trans. Comput., vol. 22,
pp. 1045–1047, Dec. 1973.
• Active module implementation: [9] [Link]älander, [Link], and [Link]-Edefors, “An efficient
In this step, partially reconfigurable sub-modules are twin precision multiplier,” in Proc. 22nd IEEE Int. Conf.
generated by top module and .ucf file. Each sub module Comput. Des., Oct. 2004, pp. 30–33.
[10]M. Själander, HMS Multiplier Generator. Feb. 2008
generates a partial bit stream during this step is a post-PAR
[Online].Available:
(placement and routing) diagram for reconfigurable tap-3 [Link]
module generated by this step. Wire connection shown in Fig [11] M. Tremblay, M. O‟Connor, V. Narayanan, and L. He, “VIS
is a bus macro for partial module interconnection. speeds new media processing,” IEEE Micro, vol. 16, no. 4, pp.
10–20, Aug. 1996.”

91
 ISSN 2249-6343
International Journal of Computer Technology and Electronics Engineering (IJCTEE)
Volume 2, Issue 2
[12]A. D. Booth, “A signed binary multiplication technique,”
Quarterly [Link]. Appl. Math., vol. 4, no. 2, pp. 236–240,
1951.] M. Tremblay, M. O‟Connor, V. Narayanan, and L. He,
“VIS speeds new media processing,” IEEE Micro, vol. 16, no. 4,
pp. 10–20, Aug.1996.”
[13]J,Ohban, [Link], and K. Inoue, “Multiplier energy
reduction through bypassing of partial products,” 2002 Asia-
Pacific Conference on Circuits and Systems(APCCAS‟02),Vol
2, pp,13-17,oct,2002.
[14]Brebner, G., and Diessel, O.: „Chip-based reconfigurable task
management‟. Field-programmable logic and application,
August 2001, (Springer-Verlag), pp. 182–191
[15]Burns, J., Donlin, A., Hogg, J., Singh, S., and de Wit, M.: „A
dynamic reconfiguration run-time system‟. IEEE Symp. on
FPGAs for Custom Computing Machines, April 1997, (IEEE
Computer Society), pp. 66–75 3 Mignolet, J-Y., Nollet, V.,
Coene, P., Verkest, D., Vernalde, S., and Lauwereins, R.:
„Infrastructure for design and management of relocatable tasks
in a heterogeneous reconfigurable System-on- Chip‟. Design,
Automation and Test in Europe, March 2003, (IEEE Computer
Society), pp. 986–991
[16] Steiger, C., Walder, H., and Platzner, M.: „Heuristics for online
scheduling real-time tasks to partially reconfigurable devices‟.
Field-Programmable Logic and Applications, September 2003,
(Springer-Verlag), pp. 575–584

92