Project Assignment #2 – Single stage amplifier
FAC 2024-2, Prof.: Eduardo Caballero
This activity corresponds to a max of 40% of the total project.
1. Goals
• To implement a single-ended voltage amplifier using a step-by-step procedure.
2. Policies
• Deadline: Nov 02, 2024. 8:00 PM.
• Project teams can consist of 3 students. You must provide only one report for a group.
• Delivery format: PDF document in IEEE format meeting all the requirements detailed in
Deliverables section. Max number of pages: 4. (Eng or Spanish).
3. Resources
• SPICE model file for the 2N7000 transistor: 2n7000_sbckt.txt
• Simulation guide with LTspice: [Link]/media/en/simulation-models/spice-
models/[Link]
4. Instructions and Guidelines
Please complete the following activities and use them to collect the data for your report. Use LTspice
when a simulation is required.
PART 1
• For the amplifier shown in Fig. 1 design the Ibias current to get a maximum gm for the M1
transistor. The maximum power budget for the project is 75mW. You should spend a
maximum of 33% of the total power in the core branch given by M1 and R1.
• Design RG1 and RG2 to spend less than 5% of the power spent on the core section, and, to
define a bias voltage of 5V in the G node, that is VG=5V.
• Design RD value to get a small-signal voltage gain vout/v1 ≥ 20V/V. Check all bias points are
OK. You can assume that C1 and C4 are coupling capacitances.
• Run a TRAN simulation and plot v1 and vout signals. What is the obtained gain? What
happened?
Fig. 1. Single stage amplifier configuration.
Fig. 2. Decoupling capacitor.
• Add a decoupling capacitor C2 as illustrated in Fig. 2.
• Run a TRAN simulation again and plot v1 and vout signals. Show that the effective voltage
gain can be demonstrated in this simulation. Explain why it is working in this situation?
• Please, respond: What happens if RD is increased? Explain considering the effects on voltage
gain and DC operation points.
PART 2
• Implement the current mirror in Fig. 3 in a LTspice schematic and use Vout_dc = 2V.
• Use the simplified model below for the 2N7000 and find Rpot to obtain Iout flowing to M2 as
the same current Ibias obtained in PART 1.
Simplified model for 2N7000: Vth=2.1 V, unCox = 0.35 A/V2, λ = 0.001, W=L=1um.
• Run an OP simulation and obtain Rpot via simulation for the same Iout = Ibias form PART 1.
• Obtain and report the errors obtained between hand calculations and simulation. Find errors
to MOS currents, Rpot value, and V(nbias) value.
Fig. 3. Simple current mirror.
• With the Rpot obtained, change the Vth parameter for M3 to be 2V and for M2 to be 2.2V and
repeat the OP simulation. What are the new ID3 and ID2 obtained? How much (in %) does
they deviate from the initial case when Vth was 2.1V?
• Add Rs=330Ω resistors as shown in Fig. 4 and repeat the OP simulation. What are the new
ID3 and ID2 obtained? How much (in %) does they deviate from the initial case when Vth was
2.1V? What can you conclude about the Rs implementation?
Fig. 4. Rs implementation in the current mirror.
• Change the Vth values to 2.1V again for both M2 and M3 and adjust Rpot to obtain Iout=Ibias
obtained in PART 1.
PART 3
• Now, with the circuits obtained in PART 1 and PART 2, build the amplifier shown in Fig. 5 in
LTspice.
Fig. 5. Complete single-ended amplifier.
• Run an OP simulation and check all bias points. They must be very similar to the obtained in
previous parts. Adjust (if needed).
• Run a TRAN simulation again and plot v1 and vout signals. Show that the effective voltage
gain can be demonstrated in this simulation. Adjust (if needed).
• Check for the total power of the circuit.
• Adjust (if needed) to meet the DC, power, and voltage gain specifications. Report the final
values for these specifications.
• Report all resistors values, VGS, ID, and saturation margins VDS – Vdsat for the devices. Use
a table for this.
PART 4
• Perform the assembly of the circuit shown in Fig. 5 using a breadboard and real values for
components. Be sure to measure the component values (like resistors) before you
assemble them.
• Once the design and assembly are done, measure all currents in the branches and voltages
in the nodes of your assembly (use a multimeter for this).
• Capture a photo/image of your assembly in a breadboard and add it to your report. Please,
do a good assembly.
An example of a GOOD assembly is: An example of a BAD assembly:
• Report all resistors values (real values), VGS, ID, and saturation margins VDS – Vdsat for
the devices. Use a table for this.
• Report the obtained specifications for the final circuit implementation: total power, and
voltage gain.
• Write your conclusions.
5. Evaluation
The evaluation for this activity depends solely on the report you provide considering the following
criteria:
• Design and simulation results (60%)
• Results comparison between simulation, experimental and hand calculations (20%)
• Conclusions (20%)