Pranjali Borch ate
TU3F2223039
Theoretical Computey science A32.
Assiqnment No. -1
in bab
Deslgn ESM in which input is yalid i it ends
Sol Step) Deination o ESM
Fsm compiises. o¥ state which accept Finite state o*
(o
iaput () to produce Finite set oF output
It datines two Tunction s
state Function:SX I’S
Machine Function: s XI’O
stepa) logic
S:
step&) Implementation
SX I ’ S
ba 40 43
bab
Sx I ’ o
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Step 4) Simulation:
d( 9o abba)
d 6, abbab)
f(9o, bba)
TT
(92,b) 42|| yajectod.
Accepted
Step 5) Diagram
b
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pue-)Desiqn FSM to 1eco qnize a lanquage in which eyrya
Iollowpd bu b's
Ans
L- fab,abbs bab, bbabb,
2) logic:
a
q1
92
3) piagram
4) Simulation.
S(9obab)
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12
Hences Final state eachad
a ccapted
(gobaa)
Hehce Fiaal state noteached
Rejected
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Que-Dasign sr to imple ment bin avs adder ove
Ans stepi) DeFinatiDn 0F FSM
accept Finite set
FsM comprises oF state which
oFinput Dto praduce Finita set o outprt
step ) Logic
-fo,o1, (o,), (ho),(s)
Here, 46 No carry
Carry
Step 3) Implementation:
(o,0) (o1) |,o) (u,!)
To 40
C
SX I ’ 0
H
(oneY (o,!) (1,o) (1,!
ALcqo
C
step 4):
stmulation
&(2o (l000, Iooo))
t o(4o, (loo, l00))
Fo(9 (o9,0! )).
Tdureu FOR EDUEATHON SE
F 9(carrs qenerata d)
Rejected (Carry not qenerated)
Step 5) state diagram.
to,o tro)
(o)
(4,)
(Oo)
(o,1)
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ue-)Desin Fsn in ubichioput is vali dir it dces not cont ans.
bb5 oVQYSi(aub)
Anis’ Step 1) Deiaation 0¥ FsM
ioput
FSM compris es o state which accept inite sat oF
(I) to produca Finite set oF Output.
step 2) logic.
7
step s) Implementation
a b
Contain
b
bb 92 9o
bbb 43
As, in example, input is valid i it does not
Coataips 'bbb!
Hence, except 4g al axe Fínal states.
Step 4) Simulation
&(90 Qbb)
S(4osbb)
Aecepted Rejacted Accaptsd
it contain bbb' whichis_not valíd hence yeject
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Step 5) statediagram
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5
Que- 5) Con vert the ull NEn wth e to d complete oA
hccepting staBe)
E- cloGure
2’
4’4
NEA without g
M
b
2,34 ?
3
3
ram FOR EDUCATIONAL USE
NEA t o DFA
2,3,4 (?
(2,3,4}3,4] {13, 4}
{3.47 3.43 13,4
lft3.43 f2,3,4} {i39
Diaqram
b
134
E,3,4?
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5
gues) Design melay_machine to Find out o's complement
o¥ a binars number
Hhs) A melay_machine is a Finite state machine where autput
depend on both the current state and the curYant
input
3) Lagic
) Diagram
/6
2ue-)Design ponIe machine or the laogtage
(o +1)* (oo+)_ apd conyert jtto mlay machine
Ans DIt is a EA with as Fisa state and it pxoduces the
0utput Sequance Aor the given input sequence
It 0s Iepresented by Gtuple
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2 logic
S\I
ends in R R
2 R
43 R A
42
43 93 R A
3) Implementation:
fAR}
4s R R
A R
R
Diaqram:
o/R
o/R
/R
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4) Mela s to
moore
9sIR)
(9oA JA
(oR/R
4, AA
(91RIR
Due-e) Design tmelay machine to olp even and odd dependin q on
the Dumbe} s aye [Link] odd over
ns i) Lt isq FA with no Finalstate and itproduces the out
put sequence or the given input sequence For the
gvan input soquance. In thisolp symbal 's assaciated
witheach transiton.
2) Logie f Implemantation
p
E
Diagtam
o}E
/E
(e)