Project Report

Course Title: Digital Logic Design

Courser Code: EEE205
Section: 01

Submitted By: Group 01

1. Md. Sazzadur Rahman ID: 2022-3-80-041
2. Faisal Hasan ID: 2022-2-80-007
3. Niaz Morshed Razon ID: 2022-2-80-008

Submitted To:
Dr. Mohammad Ryyan Khan
Associate Professor
Department of Electrical and Electronic Engineering

31 May 2024
th

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 Part-A

Problem Statement:

o We have a single push button (key) that users can press.

o The duration of the key press varies each time.
o We want to synchronize this user input with the system for further analysis.

Objective: Convert the variable-length user key press (Ain) into a single-cycle pulse (AP) that
aligns with the system clock.

Approach:

o We’ll use a positive edge-triggered synchronous system as an example.

o When the user presses the key, we want to generate a single-cycle pulse (AP) that
indicates the key press.
o The pulse should be synchronized with the rising edge of the clock signal.

Solution:

To solve this problem, we can used two D flip-flop to capture the rising edge of the clock. When
the user presses the key (Ain), we’ll sample its state (pressed or not) at the rising edge of the clock.
If the key is pressed at that moment, we set the output (AP) to high (1) for one clock cycle.
Otherwise, the output remains low (0).

State Diagram:

▪ State 0: No key press (AP = 0).

▪ State 1 (Key Press Detected): Key press detected (AP = 1).
▪ Transition: On the rising edge of the clock, transition from State 0 to State
1 if Ain is high (key pressed).

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 Figure-1: State Diagram

state table.
Present state Input Next state Output
Q1(t) Q2(t) W Q1(t+1) Q2(t+1) Z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 1 0 1

0 1 1 1 1 1

1 0 0 0 0 0

1 0 1 0 1 0

1 1 0 1 0 0

1 1 1 1 1 0

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State equation.
Q1(t+1) = Q2(t)
Q2(t+1) = W(t)

Z = ̅̅̅̅̅̅̅
Q1(t) Q2(t)

Circuit diagram.

Figure-2: State Table (Part-A)

Implementation:

o Used D flip-flop to capture the rising edge of the clock.

o Connect Ain to the D input of the flip-flop.
o Connect the Q output of the flip-flop to AP.

Summary: We’ve designed a simple synchronization system that converts variable-length key
presses into single-cycle pulses. The system ensures that the pulse aligns with the clock edge.

Circuit And Result Pictures:

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Figure-3: Constructed Circuit

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 Figure-4: Output Result

Part-B
Design of a 4-Key Security System

Introduction
In this project, we will design a security system that uses four keys (α, β, γ, δ) and provides feedback for
correct and incorrect entries. The system includes a level-to-pulse converter for each key and has a reset
functionality controlled by an administrator.

Objective:
To design a security system that:
1. Activates upon the correct entry of a predefined password using four keys.

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2. Provides feedback via two output signals: FC1 for correct entries and FW1 for incorrect entries.
3. Can be reset by an administrator, turning off FC1 and FW1.

Components:1
1. Keys (α, β, γ, δ): Push-button inputs that represent the password keys.
2. Output Signals: FC1 (indicates correct entry) and FW1 (indicates wrong entry).
3. Reset Button: Used to reset the system.
4. Logic Gates: AND, OR, NOT gates for processing inputs.
5. Flip-Flops: D-type flip-flops to store the system state.
6. Level-to-Pulse Converter: Converts the steady input from keys to pulses.
7. LEDs: Indicate the system status for FC1 and FW1.

Design Explanation:
In this project, we designed a security system with four keys (α, β, γ, δ) that requires users to enter a preset
password to gain access. The system verifies the input sequence and provides feedback via two output
signals: FC1, which lights up when the correct password is entered, and FW1, which lights up when an
incorrect password is entered. Additionally, the system features a reset button that clears the current state
and turns off both output signals.

We utilized D-type flip-flops (D-FF) in our design because they are ideal for implementing state machines
due to their simplicity and reliability in storing binary state information. D-FFs capture and hold the input
state on the rising edge of a clock signal, ensuring that the system transitions between states only when
specific conditions are met. This characteristic is crucial for our sequential logic design, where the system
must accurately follow the sequence of key presses.

Each key is connected to a level-to-pulse converter, which ensures that a key press is registered as a single
pulse, preventing multiple entries from a single press. The state machine transitions through states S0 to S4
as the correct sequence of keys is pressed. The state transitions are controlled by combinational logic
implemented using AND, OR, and NOT gates, which check the inputs and current state to determine the
next state.

The state table defines the behavior of the system, specifying the conditions under which the system
transitions from one state to another and the corresponding outputs. When the correct sequence (α → β →
γ → δ) is entered, the system reaches state S4, turning on the FC1 signal. Any deviation from the correct
sequence activates the FW1 signal, indicating an incorrect entry.

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The system is reset by pressing the reset button, which clears the states of all D-FFs, returning the system
to the initial state (S0) and turning off both FC1 and FW1. This design ensures a robust and reliable security
system that can be easily reset and reconfigured as needed. The project demonstrates the effective use of
digital logic and sequential circuit design to implement a practical security solution.

Design Methodology:
We will use a state machine approach to handle the sequence of key presses and determine the correctness
of the password entered. The design involves the following steps:
1. Define the States and Transitions:
- States: S0 (Idle), S1 (after α), S2 (after β), S3 (after γ), S4 (after δ, correct entry), and incorrect state.
- Transitions: Defined based on the input sequence and reset functionality.
2. State Table:
The state table captures the transitions based on the inputs and reset signal.

State Table:

Current Next FC1

α β γ δ Reset
State State (Correct) FW1
(Wrong)
S0 1 0 0 0 0 S1 0 0

S1 0 1 0 0 0 S2 0 0

S2 0 0 1 0 0 S3 0 0

S3 0 0 0 1 0 S4 1 0

Any x x x x 1 S0 0 0

Incorrect x x x x 0 - 0 1

Calculation Steps and Explanations

1. Define Password and Inputs
- Preset password: "α, β, γ, δ"

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 - Each key and reset button is a digital input that can be HIGH (1) or LOW (0).

2. State Machine Design:

- We use D-type flip-flops to store the current state of the system.
- The output of each state is determined by the combination of current inputs and previous state.
- We will need five states (S0, S1, S2, S3, S4) plus an implicit incorrect state.

3. State Transitions:
- From S0: If α is pressed, transition to S1. Any other input keeps the system in S0.
- From S1: If β is pressed, transition to S2. Any other input moves to the incorrect state.
- From S2: If γ is pressed, transition to S3. Any other input moves to the incorrect state.
- From S3: If δ is pressed, transition to S4 (correct entry). Any other input moves to the incorrect state.
- From S4 (Correct Entry): System stays in S4 until reset.
- Reset: Any state transitions to S0 when reset is pressed.

4. Output Logic:
- FC1: Turns on when the system transitions to S4 and stays on until reset.
- FW1: Turns on if any incorrect sequence is detected and stays on until reset.

Circuit Design

1. Input Handling:
- Use digital debouncing circuits or logic toggles for each key (α, β, γ, δ) to ensure clean pulse
generation.

2. State Machine Implementation:

- Flip-Flops: Use D-type flip-flops to store states.
- Logic Gates:
- Use AND gates to detect specific sequences.
- Use OR gates to handle incorrect sequences and reset functionality.

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3. Reset Logic:
- Connect the reset button to the reset inputs of all flip-flops.
- Ensure that pressing the reset button clears FC1 and FW1 and returns the system to S0.

Proteus Simulation:

Figure-5: Porteous Circuit Simulation

Here’s a high-level conceptual representation of the circuit in Proteus:

1. Level-to-Pulse Conversion:
- Each key (α, β, γ, δ) connects to a debounce circuit.
- Outputs are fed into the state machine logic.

2. State Machine Logic:

- Flip-Flops: Connect flip-flops to store the state.
- Logic Gates: Use AND, OR, and NOT gates to manage transitions and detect the correct sequence.

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 - State Transitions:
- S0 to S1 on α pulse
- S1 to S2 on β pulse
- S2 to S3 on γ pulse
- S3 to S4 on δ pulse
- Incorrect Sequence Detection: Use OR gates to handle any incorrect input and activate FW1.

3. Output Indicators:
- FC1: Connect to an LED to indicate a correct entry (S4).
- FW1: Connect to an LED to indicate a wrong entry.

4. Reset Mechanism:
- The reset button connects to the reset inputs of flip-flops.
- Ensure the reset functionality clears the state and turns off FC1 and FW1.

Conclusion:
This report details the design and implementation of a 4-key security system, including a state machine for
password checking, correct and incorrect entry indicators, and a reset function. The state table and
calculations ensure a thorough understanding of the system’s behavior. The Proteus simulation file, along
with the Arduino example code, demonstrates the system's operation, providing a comprehensive solution
for the given problem.

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