Department of Electronics and Telecommunication

Digital VLSI

TE Semester - V
Subject In charge
Mrs. Dipti Kale
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Subject Code: ECC 503
Digital VLSI

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Module 1:Review of MOSFET operations and
Fabrication

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Overview of VLSI Design Flow

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Module 1:Review of MOSFET operations and Fabrication

• IC- Integrated microelectronic circuit have active and passive components

fabricated on extremely single tiny silicon chip
• Very-large-scale integration (VLSI) is the process of creating an integrated
circuit (IC) by combining thousands of transistors into a single chip.
• VLSI began in the 1970s when complex semiconductor and communication
technologies were being developed. eg. microprocessor
• The electronics industry has achieved a phenomenal growth over the last few
decades, mainly due to the rapid advances in large scale integration
technologies and system design applications.
• With the advent of VLSI designs, the number of applications of integrated
circuits (ICs) in high-performance computing, controls, telecommunications,
image and video processing, and consumer electronics has been rising at a very
fast pace.
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 Evolution of IC from SSI, MSI, LSI to VLSI
• Firstly, between 1961-1965 in SSI (small scale integration) transistors were fabricated
about 10 to 100 on a single chip. This technology is used for making logic gates, flip
flops.
• In 1966-1970 in MSI (medium scale integration) transistors were fabricated about 100
to 1000 on a single chip. This technology is used for making counters, multiplexers,
decoders.
• In 1971-1979 in LSI (large scale integration) transistors were fabricated about 1000 to
20000 on a single chip. This technology is used for making microprocessor, RAM, ROM
• In 1980-1984 in VLSI (very large scale integration) transistors were fabricated about
20000 to 50000 on a single chip. This technology is used for making DSP (digital signal
processing) IC’s, RISC microprocessor, 16-bit and 32-bit microprocessors.
• From 1985- present technology is ULSI (ultra large scale integration), in which
transistors are fabricated about greater than 50000 to billions on a single chip. This
technology is used for making 64-bit microprocessors

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 Evolution of IC from SSI, MSI, LSI to VLSI
HOW TRANSISTOR REQUIREMENT INCREASES WITH TIME
• In 1965 Moore’s gave a law, in which he observed the number of transistors
in a dense integrated circuit doubles about every year.

Today’s processors like Intel i3, i5 and i7 have more than 4 billion transistors on chip. In
microcontroller ATMEGA328 approximately 50000 transistors were fabricated on chip.

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 Silicon IC Technology
• IC technology broadly categorized in two main technologies: Bipolar and
MOS

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 Comparison of VLSI IC design Technologies
BIPOLAR NMOS CMOS

Bipolar technology uses BJT for design NMOS use only field effect transistors for CMOS uses both MOS transistors and
design. PMOS for design

High power dissipation Higher power dissipation than CMOS but Low power dissipation
lower than bipolar.

Low input impedance High input impedance

Medium noise margin Medium noise margin High noise margin

High speed of operation Medium speed of operation

Unidirectional Unidirectional Bidirectional

NMOS propagates only logic 1 that is VDD CMOS propagates both logic 0 and 1

Non ideal switching device Ideal switching device

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 VLSI Design Flow: Y Chart Representation

• The Gajski-Kuhn Y-chart is a model, which captures the considerations in designing

semiconductor devices.
• The three domains of the Gajski-Kuhn Y-chart are on radial axes. Each of the domains
can be divided into levels of abstraction, using concentric rings.
• At the top level (outer ring), we consider the architecture of the chip; at the lower
levels (inner rings), we successively refine the design into finer detailed
implementation −
• Creating a structural description from a behavioral one is achieved through the
processes of high-level synthesis or logical synthesis.
• Creating a physical description from a structural one is achieved through layout
synthesis.

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VLSI Design Flow: Y Chart Representation

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 VLSI Design Flow
• The VLSI IC circuits design flow. The various levels of design are numbered and the
blocks show processes in the design flow.
• Specifications comes first, they describe abstractly, the functionality, interface, and
the architecture of the digital IC circuit to be designed.
• Behavioral description is then created to analyze the design in terms of functionality,
performance, compliance to given standards, and other specifications.
• RTL description is done using HDLs. This RTL description is simulated to test
functionality. From here onwards we need the help of EDA tools.
• RTL description is then converted to a gate-level netlist using logic synthesis tools. A
gatelevel netlist is a description of the circuit in terms of gates and connections
between them, which are made in such a way that they meet the timing, power and
area specifications.
• Finally, a physical layout is made, which will be verified and then sent to fabrication.

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VLSI Design Flow

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 VLSI Design Flow: Y Chart Representation

• Hierarchy: Dividing complex design into various modules and sub-modules

• Abstraction: At each design level internal details for complex module abstracted
away and replaced by black box model.
• Regularity: Dividing hierarchy into set of similar building blocks
• Modularity: designing various functional blocks which makes up larger systems
well defined functions and interfaces so that they can be implemented and tested
separately.
• Locality: Locality ensures that the internals of modules are visible to any
exterior interfaces enabling outside world to treat each module as a black box
with well defined inputs and outputs.

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Review of MOSFET operation and Fabrication

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 Basic MOSFET Structure
• MOSFET stands for Metal Oxide Silicon Field Effect Transistor
• IT operates in both depletion and enhancement modes of
operation.
• In construction of a MOSFET an oxide layer is deposited on the
substrate to which the gate terminal is connected. This oxide
layer acts as an insulator
• In the construction of MOSFET, a lightly doped substrate, is
diffused with a heavily doped region. Depending upon the
substrate used, they are called as P-type and N-type MOSFETs.
• The voltage at gate controls the operation of the MOSFET.
• Both positive and negative voltages can be applied on the gate
as it is insulated from the channel. With negative gate bias
voltage, it acts as depletion MOSFET while with positive gate
bias voltage it acts as an Enhancement MOSFET.

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Classification of MOSFETs

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 Construction of N- Channel DMOSFET

• N-channel MOSFET has lightly doped P-type substrate is taken into which two heavily doped N-type
regions are diffused, which act as source and drain. Between these two N+ regions, there occurs diffusion
to form an N channel, connecting drain and source.
• A thin layer of Silicon dioxide (SiO2) is grown over the entire
surface and holes are made to draw ohmic contacts for drain
and source terminals.
• A conducting layer of aluminum is laid over the entire
channel, upon this SiO2 layer from source to drain which
constitutes the gate.
• The SiO2 substrate is connected to the common or
ground terminals. Because of its construction, the MOSFET
has a very less chip area than BJT.

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 Construction of P- Channel DMOSFET

• A lightly doped n-substrate is taken into which two

heavily doped P+ regions are diffused.
• These two P+ regions act as source and drain. A thin
layer of SiO2 is grown over the surface. Holes are cut
through this layer to make contacts with P+ regions, as
shown in the figure.

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 Construction of P- Channel EMOSFET

• The body of any P-channel MOSFET is made up of N-

type material. 2 P-type materials are diffused at the
top. A depletion region will be formed in the PN
junction.
• A metal contact is made at the bottom of the N-type
substrate and a terminal is taken out called the body
or substrate.
• Metal contact is made at the top of both the P-type
materials, and two terminals are taken out as Drain
and source.
• A Silicon dioxide layer is drawn in between the two
P-type wells at the top. A metal contact is made at
the top of it and a terminal is taken out called a Gate
terminal.
• It is a 4-terminal device.

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 Construction of N- Channel EMOSFET

• The body of any N-channel MOSFET is made up of P-

type material. 2 N-type materials are diffused at the
top. A depletion region will be formed in the PN
junction.
• A metal contact is made at the bottom of the P-type
substrate and a terminal is taken out called the body
or substrate.
• Metal contact is made at the top of both the N-type
materials, and two terminals are taken out as Drain
and source.
• A Silicon dioxide layer is drawn in between the two N-
type wells at the top. A metal contact is made at the
top of it and a terminal is taken out called a Gate
terminal. It is a 4-terminal device.

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 N-Channel Enhancement MOSFET Working

• Drain current flows when channel available for the free movement of electrons.
• To create a channel we have to apply a voltage between the gate and the source terminal
VGS keeping the Gate at a higher potential. Now the gate is at higher potential.
• The free electrons will move toward the gate terminal as Silicon Dioxide layer at the top.
Hence these free electrons will accumulate near the Gate region and will not escape.
• The silicon dioxide layer also acts as a dielectric. It will allow more free electrons to
accumulate near the gate terminal in less applied voltage at the gate terminal.
• on increasing VGS further, a high electric field is developed forcing atoms inside the P
substrate to break.
• The free electrons generated will fill the holes near the gate region. This way holes are
pushed away from the gate terminal increasing N-type behavior near the gate terminal.
A time will come when an N-channel is created between the two N wells.

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 N-Channel Enhancement MOSFET Working

• The VGS voltage at which the channel is created is called the threshold voltage or
VT. When VGS > VT an N channel is induced near the gate terminal

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 N-Channel Enhancement MOSFET Working

• A channel is created but current will flow when voltage between source and drain
VDS applied keeping the drain at a higher potential.
• On applying this voltage current will start flowing from drain to source. This
current is called drain current or ID.
• When VGS > VT and VDS > 0, the current ID flows from drain to source as shown in
the figure below.

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 N-Channel Enhancement MOSFET Working
• On increasing VDS a reverse bias is formed at the PN junction near the drain terminal. This
will result in a thick depletion region near the PN junction. So channel near the drain
terminal is becoming narrow.
• The drain current will face more resistance near the drain terminal. The drain current
becomes constant and will not increase further called the pinch-off situation and the drain
current is called the saturation current.
• The voltage at which we will get saturation current is called saturation voltage. pinch-off is
reached when VGS > 0 (constant) and VDS = VDS(SAT), ID = ID(SAT) as shown in the figure
below.

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 N-channel Enhancement MOSFET V-I Characteristic
• It is plot of VDS vs ID for various values of VGS.
• From the graph, it is clear that the current ID will become constant at a specific value of
VDS. current ID increases only when the value of VGS is increased.

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 N-Channel Enhancement MOSFET Transfer Characteristics
• Transfer characteristics define the change in the value of VDS with the change
in ID and VGS in both depletion and enhancement modes. The below transfer
characteristic curve is drawn for drain current versus gate to source voltage.

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