DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING
TECH TALK SERIES 3.0
AI in VLSI Design Advances and Challenges: Living in the
Complex Nature of Integrated Devices
MENTOR BY: PRESENTED BY:
Mr. G. Abdul Kalam Azad, AP/CSE Kishore Kumar S III-CSE B
Mrs. B. Ashwini, AP/CSE Nandeswar A III-CSE B
Mrs. E. Kiruthika, AP/CSE Maheswaran K III-CSE B
Abstract
This article investigates vital VLSI configuration progress, including nanotechnology, 3D
coordination, high-level materials, Framework on-Chip (SoC) plan, and state-of-the-art bundling
advancements. Security concerns about equipment weaknesses and the consistent apparition of
financial and mechanical oldness further confuse the scene. Looking forward, the article frames
arising patterns in VLSI configuration, including simulated intelligence joining, quantum
processing structures, neuromorphic figuring, and photonics combination. It proposes expected
arrangements, like cooperative environments, advancements in warm administration, security-by-
plan standards, coordinated techniques, and expanded interest in schooling. The end considers
the ramifications for the future, stressing the requirement for consistent variation,
interdisciplinary joint effort, and a groundbreaking way to deal with bridling the maximum
capacity of coordinated gadgets in the mind-boggling universe of the VLSI plan.
VLSI Design Flow
• System Specification
• Architectural Design
• High-level Synthesis
• Logic Synthesis
• Physical Design
• Fabrication
• Packaging & Testing
High-level Synthesis
High-level Synthesis Steps
Preprocessing
Preprocessing
Scheduling
Register Allocation
Data Path Synthesis
Operation Delay
Controller Synthesis
Scheduling Possibilities
Scheduling Possibilities
Challenges in VLSI
• Power Consumption
• Resource Allocation
• Latency Problems (Propagation Delay, Communication Latency)
• Heat Generation
Conclusion
Use machine learning algorithms to improve the synthesis steps
• Million of gates
• Synthesis steps are heuristic based.
• May not work well with new scenarios
• Use EDA to improve execution of machine learning algorithms
• Use EDA tools to develop AI/ML specific processor
• Arm Machine Learning Processor
• A tensor processing unit (TPU) is an AI accelerator application-specific integrated
circuit (ASIC) developed by Google.
• Automatic synthesis of ML algorithms to FPGA
• FPGA implementations of ML applications can often run much faster that software
implementations and can consume significantly less power.
• Quite promising area of research.
Thank You