MULTIPLEXER AND DEMULTIPLEXER

Multiplexer

A multiplexer (MUX) is a data selector which takes several inputs and gives a single
output. In which we have 2n Input lines and 1 output lines where n is the number of
selection lines. The function of a multiplexer is
to select the input of any ‘n’ input lines and
feed that to one output line like a digital
switch, controlled by select lines. Both digital
and analogue applications can be handled by
multiplexers. In digital applications,
multiplexers are constructed from ordinary
logic gates, while in analogue applications,
they are composed of relays and transistor switches. Fig. 1. Multiplexer

Digital multiplexers are classified into four types:

1.) 2x1 MUX – There are just two inputs (A 0 and A1), one selection line (S0), and one
output (Y). One of these two inputs will be connected to the output based on the
combination of inputs present at the selection line. Y= S0•A0+S0•A1.

Fig. 1.1.1 2x1 MUX Logic Expression Fig. 1.1.2. 2x1 MUX Truth Table

2.) 4x1 MUX - there are four inputs (A0, A1, A2, and A3), two selection lines (S0 and S1),
and one output (Y). Depending on the input combination at selection lines S0 and S1,
one of these four inputs is connected to the output.
Y=S1' S0' A0+S1' S0 A1+S1 S0' A2+S1 S0 A3

Fig. 1.2.1. 4x1 MUX Truth Table Fig. 1.2.2. 4x1 MUX Logic Expression
 3.) 8x1 MUX - The 8 to 1 multiplexer has three selection lines (S 0, S1, and S2), one
output (Y), and eight inputs (A 0, A1, A2, A3, A4, A5, A6, and A7). The output is
connected to one of these eight inputs based on the combination of inputs present at
the selection lines S0, S1, and S2.

Y=S0'.S1'.S2'.A0+S0.S1'.S2'.A1+S0'.S1.S2'.A2+S0.S1.S2'.A3+S0'.S1'.S2 A4+S0.S1'.S2 A5+S0

'.S1.S2 .A6+S0.S1.S3.A7

Fig. 1.3.1. 8x1 MUX Truth Table Fig. 1.3.2. 8x1 MUX Logic Circuit Expression

However, 8×1 multiplexer can be

constructed using two 4×1 multiplexers and
one 2×1 multiplexer. Each 4×1 multiplexer has
four inputs, one output, and two selection lines,
while the 2×1 multiplexer has one selection line
and two inputs. To handle eight data inputs, we
use two 4×1 multiplexers to process four inputs
each, producing two outputs. These outputs
are then fed into the 2×1 multiplexer, which
selects the final output. This setup allows us to
achieve an 8×1 multiplexer configuration by
cascading lower-order multiplexers.
Fig. 1.3.3. 8x1 MUX Block Diagram
using lower-order MUX

4.) 16x1 MUX - A total of 16 inputs (A0, A1, …, A16), 4 selection lines (S0, S1, S2, and S3),
and 1 output (Y) are present. Depending on the input combination at selection lines
S0, S1, and S2, one of these 16 inputs will be connected to the output.
 Fig. 1.4.1. 16x1 MUX Truth Table
Fig. 1.4.2. 16x1 MUX Logic Circuit Expression

A lower order multiplexer can be used to

implement the 16x1 multiplexer. Two 8x1
multiplexers and one 2x1 multiplexer are required to
implement the 8x1 multiplexer, which has three
selection lines, four inputs, and one output,
whereas the 2x1 multiplexer only has one
selection line.

Fig. 1.4.3. 16x1 MUX using lower MUX

Demultiplexer

De-multiplexer (de-MUX) is opposite to the multiplexer which is a combinational

circuit that has only 1 input line and 2N output lines. Unlike encoder and decoder, there are
n selection lines and 2n outputs. So, there is a total of 2n possible combinations of inputs.

Digital demultiplexers are classified into four types:

1.) 1x2 De-MUX - There are just two outputs (Y0 and Y1), one selection line (S0), and
one input (A). The input will be linked to one of the outputs based on the selected
value. Y0=S0'.A : Y1=S0.A

Fig. 2.1.1. 1x2 De-MUX Truth Table Fig. 2.1.2. 1x2 De-MUX Logic Circuit
2.) 1x4 De-MUX - Four outputs in total—Y0, Y1, Y2, and Y3—two selection lines—S0 and
S1—and one input—A—are present. The input is connected to one of the outputs
based on the combination of inputs that are present at the selection lines.

Y0=S1' S0' A, Y1=S1' S0 A, Y2=S1 S0' A, Y3=S1 S0 A

Fig. 2.2.1. 1x4 De-MUX Truth Table

Fig. 2.2.2. 1x2 De-MUX Logic Circuit

3.) 1x8 De-MUX - There are three

selection lines (S0, S1, and S2), eight
outputs (Y0, Y1, …, Y7), and one input
(A). The input will be connected to one
of these outputs based on the
combination of inputs present at the
selection lines. The Circuit Diagram of
1 x 8 multiplexer can be designed
through 8 AND logic gates & 3 NOT
logic gates. Fig. 2.3.1. 1x8 De-MUX Truth Table

4.) 1x16 De-MUX - In total, there are 16

outputs (Y0, Y1, …, Y16), 4 selection lines
(S0, S1, S2, and S3), and 1 input (A). The
mix of inputs present at selection lines
S0, S1, and S2 will determine which of
these outputs the input is connected to.
It can be constructed by 16 AND logic
gates, and 4 NOT logic gates are
required. Various select line
combinations within a given time can
enable one AND logic gate so that the
input data appears as the output.

Fig. 2.4.1. 1x8 De-MUX Truth Table

Difference between Multiplexer and Demultiplexer

Multiplexer Demultiplexer

Multiplexer processes the digital Demultiplexer receives digital information

information from various sources into a from a single source and converts it into
single source. several sources

It is known as Data Selector It is known as Data Distributor

Multiplexer is a digital switch Demultiplexer is a digital circuit

It follows combinational logic type It also follows combinational logic type

It has 2n input data lines It has single input line

It has a single output data line It has 2n output data lines

It works on many to one operational It works on one-to-many operational

principle principle

In time division Multiplexing, multiplexer is In time division Multiplexing, demultiplexer

used at the transmitter end is used at the receiver end

COMPARATOR

A comparator is an electronic circuit, which compares the two inputs that are
applied to it and produces an output. The output value of the comparator indicates which of
the inputs is greater or lesser. Please note that comparator falls under non-linear
applications of ICs.

Types of Comparators:

1.) Inverting Comparator - an op-amp based comparator for which a reference voltage
is applied to its non-inverting terminal and the input voltage is applied to its inverting
terminal. This comparator is called as inverting comparator because the input
voltage, which has to be compared is applied to the inverting terminal of op-amp.
 The output value of an inverting
comparator will be −Vsat, for which the
input Vi voltage is greater than the
reference voltage Vref.
  The output value of an inverting comparator will be +Vsat, for which the
input Vi is less than the reference voltage Vref.

2.) Non-inverting Comparator - A non-inverting Fig. 3.1. Inverting

comparator is Comparator
an op-amp based
comparator for which a reference voltage is applied to its inverting terminal and the
input voltage is applied to its non-inverting terminal. This op-amp based comparator
is called as non-inverting comparator because the input voltage, which has to be
compared is applied to the non-inverting terminal of the op-amp.
 The output value of a non-inverting
comparator will be +Vsat, for which the input
voltage Vi is greater than the reference
voltage +Vref.
 The output value of a non-inverting
comparator will be −Vsat, for which the input
voltage Vi is less than the reference
voltage +Vref. Fig. 3.2. Non-inverting Comparator

READ ONLY MEMORY (ROM)

Read-Only Memory (ROM) is a non-volatile form of

memory that stores data permanently and cannot be written
over or erased. It can only be read from, which makes it ideal
for use in computers because it allows them to access
information quickly without having to constantly write and
rewrite data. This makes ROM an incredibly efficient form of
storage that can hold instructions and other types of data with
very little effort or maintenance.

ROM functions via using integrated circuits known as

"memory cells." These cells contain transistors that are connected in series, enabling the
passage of electrical current upon application of power. The data from the memory cell is
stored in a magnetic field created by current flowing through these transistors until it is
cleared by another signal passing through the transistor. These cells' contents cannot be
altered or removed unless a computer processor or hard drive controller specifically
instructs them to do so.

Types of ROM;

 PROM chips, or programmable read-only memory, can only be written to once;

they cannot be deleted or overwritten. Basic input/output system (BIOS) settings and
other modest pieces of code or data are usually stored in them.
  Erasable Programmable Read-Only Memory, or EPROM, is a type of chip that
can be repeatedly rebuilt by exposing it to ultraviolet light through an eraser window
on the packaging. Game consoles and PC motherboards frequently employ this kind
of chip to save BIOS settings.
 EEPROM (Electrically Erasable Programmable Read-Only Memory) rather than
being exposed to UV light, EEPROM chips may be repeatedly reprogrammed using
an electric charge. Flash drives and mobile phones frequently contain this kind of
chip, which may require regular upgrades.
 Flash Memory: Unlike PROM or EPROM chips, which require erasing beforehand,
flash memory can be written to repeatedly and holds both user data and program
code. Since flash memory doesn't require any special tools to write or erase its
contents, it is frequently found in digital cameras and USB devices.

PROGRAMMABLE ARRAY LOGIC (PAL)

Fig. 4. PAL Block Diagram

Programmable Array Logic (PAL) is a commonly used programmable logic device

(PLD). It has programmable AND array and fixed OR array. Because only the AND array is
programmable, it is easier to use but not flexible as compared to Programmable Logic Array
(PLA). PAL’s only limitation is number of AND gates

This architecture allows the AND array's connections to be configured while the OR
array stays static, allowing the building of specialized logic functions. Digital systems
frequently use PALs to efficiently create specialized logic circuits. Small programmable
read-only memory (PROM) and extra output logic make up PAL, which is utilized to
implement a certain required logic function with a limited number of components.

Programmable AND Array - The AND array consists of the multiple AND gates
whose connections can be programmed by the designer. This allows for the creation of the
various logic functions by the combining different input signals.
 Fixed OR Array - The OR array is a set of fixed OR gates that combine the outputs
from programmable AND gates. The outputs from the AND gates feed into the OR gates
allowing for the final logic outputs.

Inputs and Outputs - The PAL devices have a number of inputs that feed into the
AND array and a defined number of the outputs that represent the result of the logic
operations.

Programming Mechanism - The PALs are programmed using the hardware

description language (HDL) or through the special programming tools. This programming
defines how the inputs are connected to the AND gates.

Advantages of PAL

1. Highly efficient
2. Low production cost as compared to PLA
3. Highly secure
4. High Reliability
5. Low power required for working.
6. More flexible to design.

Disadvantages of PAL

1. Limited Flexibility
2. Size Constraints
3. Propagation Delay

INTRODUCTION TO SEQUENTIAL LOGIC

Sequential circuits are digital systems designed to retain and utilize past state
information to determine their future state. Unlike combinational circuits, which generate
outputs solely based on present input values, sequential circuits rely on both current inputs
and stored state information from memory elements.

Sequential Circuit

A sequential circuit is a type of digital logic circuit composed of input variables (X),
logic gates (combinational circuit), and output variables (Z). Unlike combinational circuits,
which generate outputs based solely on current inputs, sequential circuits produce outputs
based on both current inputs and previous outputs. This functionality is achieved through
memory elements capable of storing binary information, which represents the circuit's state
at a given time.

For instance, a latch can store a single bit of binary information. As illustrated, a
sequential circuit involves two types of inputs to the combinational logic:

1. External inputs - Independent inputs that are

not influenced by the circuit itself.
2. Internal inputs- Derived from the previous
output state of the circuit.

Additionally, the secondary inputs (state

variables) are outputs from the memory elements,
while the secondary outputs act as inputs to excite
the storage elements. This feedback mechanism
enables sequential circuits to retain and process state Fig. 5. Sequential Circuit
information dynamically.

Latches and Flip-flops

A Latch is an electronic device, which changes its output immediately based on the
applied input. It is used to store either 1 or 0 at any specified time. It consists of two inputs
namely “SET” and “RESET” and two outputs, which are complement to each other.

A flip-flop is a fundamental digital memory circuit capable of storing a single bit of

information. As the basic building blocks of most sequential circuits, flip-flops are also
referred to as bistable multivibrators, binary storage devices, or one-bit memory elements.
They play a crucial role in storing state information in sequential systems.

In sequential circuits, outputs can be derived from flip-flops, combinational circuits, or a

combination of both. The state of a flip-flop changes only during the active phase of a clock
pulse and remains stable when the clock pulse is inactive.

Flip-flops can be classified based on their clocking mechanism:

 Clocked flip-flops: Used as memory elements in synchronous sequential

circuits, where changes occur in sync with the clock signal.

 Un-clocked flip-flops (latches): Serve as memory elements in asynchronous

sequential circuits, responding to changes in input signals without a clock.

This distinction between clocked and un-clocked flip-flops enables their application in a
wide range of digital systems.

Fig. 5.2. Flip-flop

 Fig. 5.1. Latch

Four types of Flip-flops;

1.) JK Flip-flop - This flip-flop functions similarly to an enhanced S-R flip-flop. J and K
are its two inputs, and Q and Q' are its two outputs. The output becomes 1 when J is
1 and K is 0. The output is zero when J is zero and K is one. It remains in its initial
condition if J and K are both 0. The unique characteristic is that the flip-flop switches
states, going from 1 to 0 or 0 to 1, when both J and K are 1.
2.) Set-Reset (S-R) Flip-flop - Set (S) and Reset (R) are its two inputs, while Q and Q'
(not Q) are its two outputs. The output Q changes to 1 when S is activated. Q turns
to zero when R is activated. The flip-flop remains in its previous state if S and R are
both 0. However, as it can result in unpredictable behavior, it is generally avoided to
have both S and R equal 1 at the same time.
3.) Toggle (T) Flip-flop - This flip-flop has two outputs, Q and Q', and one input, T.
Nothing changes when T is 0. However, the flip-flop changes states when T equals
1. It turns into 0 if Q was 1, and into 1 if Q was 0. In digital circuits, this is helpful for
dividing frequencies or creating counters.
4.) Data or Delay (D) Flip-flop - It has two outputs, Q and Q', and one input, D. It's
easier to use this flip-flop. When the flip-flop is activated, the value that is on the D
input—0 or 1—is copied to the Q output. In digital systems, it's frequently used to
synchronize signals or temporarily store data.

Register Design

Registers act as small, fast memory units that can store binary data in the form of
bits. Usually, flip-flops—basic components of digital circuits—are used in their construction.
Because of their close proximity to the processor, registers offer faster access to data than
main memory in a computer system.

Registers serve as temporary storage for data that is being processed or

transferred within a circuit. The circuit's design and operation may call for the manipulation,
modification, or transfer of data from registers to other registers. These temporary memory
banks facilitate effective data processing by ensuring that data flows smoothly within a
digital circuit.

Common types of register

:

 Shift Registers: These registers allow for the sequential shifting of data, enabling
data transfer and serial-to-parallel conversion.
  Parallel Load Registers: Registers of this type enable the simultaneous loading of
data in parallel, providing efficient data transfer capabilities.

 Buffer Registers: These registers act as temporary storage buffers between

different sections of a circuit, ensuring smooth data flow.

Counter Design

Counter is a sequential circuit implemented via flip flops. They are used to count
the number of clock signals or pulse. A mod n counter will count from 0 to n-1. Counters
can be synchronous or unsynchronous. In synchronous counter, a single common clock is
used for all the flip flops. Whereas in asynchronous counter,
only a clock is given as input for first flip flop. For an
intermediate or final flip flops, its clock pulse will be the output
of previous flip flop.

Problem – Design synchronous counter for sequence: 0 → 1

→ 3 → 4 → 5 → 7 → 0, using T flip-flop.

T flip-flop – If value of Q changes either from 0 to 1 or from 1

to 0 then input for T flip-flop is 1 else input value is 0.
Fig. 5.3. Counter Design

ALU Function

Arithmetic circuits are fundamental blocks in digital systems and are used
for arithmetic operations such as addition, subtraction, multiplication and division. Arithmetic
circuits can perform seven different arithmetic operations using a single composite circuit.
It uses a full adder (FA) to perform these operations. A multiplexer (MUX) is used to provide
different inputs to the circuit in order to obtain different arithmetic operations as outputs.

Sequential Circuit Design Procedure

Step 1: Make a state table based on the problem statement. The table should
show the present states, inputs, next states and outputs. (It may be easier to find a state
diagram first, and then convert that to a table).

If you have n states, your binary codes will have at least ⎡log 2 n ⎤ digits, and your circuit
Step 2: Assign binary codes to the states in the state table, if you haven’t already.

will have at least [log2 n] flip-flops.

Step 3: For each flip-flop and each row of your state table, find the flip-flop input
values that are needed to generate the next state from the present state. You can use flip-
flop excitation tables here.
 Step 4: Find simplified equations for the flip-flop inputs and the outputs.

Step 5: Build the circuit!

Excitation Table

Fig. 5.4. Excitation Table for all Flip- Flops

State Diagram

In addition to graphical symbols, tables or

equations, flip-flops can also be represented
graphically by a state diagram. In this diagram, a
state is represented by a circle, and the
transition between states is indicated by directed
lines (or arcs) connecting the circles.

Fig. 5.5. State Diagram of all Flip-Flops

State Table

The state table representation of a sequential circuit consists of three sections

labelled present state, next state and output. The present state designates the state of flip-
flops before the occurrence of a clock pulse. The next state shows the states of flip-flops
after the clock pulse, and the output section lists the value of the output variables during the
present state.

Synchronous and Asynchronous Circuits Analysis and Design, Excitation Function,

Flow Table

Synchronous Circuits

In synchronous sequential circuits, the state transitions occur only on the rising or
falling edge of the clock signal, ensuring all changes are synchronized with the clock. This
synchronization makes the circuit's behavior predictable, simplifies its design and
debugging, and prevents issues like race conditions by ensuring all components update
simultaneously.

These circuits are implemented using flip-flops, which store binary values and retain
their state even when the inputs vary. The flip-flop outputs depend on both the current
inputs and the previously stored state, while the next state is determined by a state
transition function—a Boolean function that defines the circuit's operation.

In summary, synchronous sequential circuits rely on clock signals to manage the

timing of operations. They are widely used in digital systems for applications like counters,
timers, and memory elements, making them fundamental in digital system design.

Fig. 5.6. Block Diagram of Sequential Circuit

Asynchronous Circuit

Asynchronous sequential circuits operate without a clock signal, relying instead on

latches or propagation delays in the combinational circuit path for memory and timing. The
inherent delay in the circuit provides sufficient feedback, eliminating the need for explicit
delay elements. However, designing such circuits is challenging due to timing issues in the
feedback path, requiring the circuit to reach a stable state before inputs change. To avoid
uncertainty caused by simultaneous input changes, only one input variable is allowed to
change at a time, with sufficient delay between changes to ensure stability.