Band Gap Reference
“Banba Topology”
Presented by Ahmed Tawfiq.
[Link]@[Link] Ahmed Tawfiq 1
Project Abstract
Analog ICs Design Project [BGR]
Alhamdulillah, I've finished Low Voltage BGR "Banaba Topology" Design and for spreading knowledge I've prepared
this Hand-Analysis and useful Design Estimation.
My role in the project was designing Full BGR circuit [ BGR Core, PMOS-Single Ended Folded Cascode OTA, Self Bias
Circuit, Startup Circuit].
Providing:
- some Corner process and Temp. Results [tt, ss, ff, sf, fs]x[-40,125].
- some Monte Carlo Results [Process and Mismatch] 1000 -max- run.
- some Layout Guidance to get better Results.
And- Alhamdulillah, I get Better Result in [ Iq, PSR, PM, GM, Accuracy, Startup Time].
My Design aims to meet the specs with Lowest Power consumption [Iq] and can run against PVTs and Mismatch.
And Inshallah, I will publish Full-Layout Design with my Layout Team Partner :
Eng.\ Mohammed Abdel Nasser
Eng.\ Ziad Ahmed.
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BGR Specification
Designed System Over all Characteristics
Vin 2.5~3.3
Inaccuracy @27.12MHz 3%
Iq 50 uA
PM 55
GM 6 dB
PSR -40 dB
Startup Time 1 uS
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BGR Full System
- Process: CMOS 0.13u
- Design Methodology: gm/id Methodology
- Band Gap Reference
o “Banba Topology ”: For flexible Vref, Iref.
- Differential Amplifier:
o “PMOS Input Pair- Single ended Folded Cascode OTA” for suitable CMIR.
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BGR Hand Analysis
• Generating ZTAT Current = PTAT + CTAT.
𝐼1
• n: num of Q2, 𝑚 = , n`=m*n
𝐼2
∆𝑉𝐵𝐸 𝑘
• 𝐼𝑃𝑇𝐴𝑇 = =𝑇 ln 𝑛` =𝑎𝑇
𝑅2 𝑞𝑅2
𝑉𝐵𝐸 𝑉𝑇 𝐼𝑐 (𝑉𝐵𝐺 −𝑏𝑇)
• 𝐼𝐶𝑇𝐴𝑇 = = ln = = 𝐼𝐵𝐺 − 𝑏`𝑇
𝑅3 𝑅3 𝐼𝑠 𝑅3
• 𝐼𝑍𝑇𝐴𝑇 = 𝐼𝐵𝐺 − 𝑏`𝑇 + 𝑎𝑇 ∶ 𝑆𝑒𝑡 𝑎 = 𝑏`
• Offset effect:
1 1
▪ 𝐼𝑜𝑠 = 𝑉𝑜𝑠 +
𝑅2 𝑅3
o Increasing n and m.
o Offset correction design techniques.
o Layout Matching.
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Design Estimation
▪ Design Assumption:
o 𝑛 = 24, 𝑚 = 1
o 𝑏` = 𝑎
𝑚𝑣
1.5~2 𝑘 0.086∗ln 24
o =
𝑅3 𝑅2
o 𝑅3 = (5~6) ∗ 𝑅2
𝑉𝐵𝐺 1.2
o 𝐼𝐵𝐺 = = = 5 𝑢𝐴
𝑅3 𝑅3
o 𝑅3 = 240 𝑘Ω, 𝑅2 = 48𝑘Ω
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Stability Analysis
▪ 2 Loops +ve and -ve
▪ For Stability: 𝛽𝑁 ≥ 𝛽𝑃
▪ Unstable 𝐹𝐵𝑁 → PM~22 not enough
▪ Compensation PM at least 55.
▪ 𝐶𝐶 , 𝑅𝑒𝑠𝑟
∆𝑉𝑅𝐸𝐹
▪ 𝑃𝑆𝑅𝑅 =
∆𝑉𝐷𝐷
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Hand Analysis < FC OTA >
❑ 𝑅𝑜𝑢𝑡,𝑢𝑝,𝐷𝑖𝑓𝑓 = 𝑔𝑚3 𝑟𝑜3 𝑟𝑜4
1
❑ 𝑅𝑜𝑢𝑡,𝑢𝑝,𝐶𝑀 = 𝑔𝑚
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❑ 𝑅𝑜𝑢𝑡,𝑑𝑜𝑤𝑛 = 𝑔𝑚2 + 𝑔𝑚𝑏2 𝑟𝑜2 (𝑟𝑜1 ||𝑟𝑜5 )
❑ 𝑅𝑜𝑢𝑡,𝐷𝑖𝑓𝑓 = 𝑅𝑜𝑢𝑡,𝑢𝑝,𝐷𝑖𝑓𝑓 ∥ 𝑅𝑜𝑢𝑡,𝑑𝑜𝑤𝑛
❑ 𝑅𝑜𝑢𝑡,𝐶𝑀 = 𝑅𝑜𝑢𝑡,𝑢𝑝,𝐶𝑀 ∥ 𝑅𝑜𝑢𝑡,𝑑𝑜𝑤𝑛
❑ 𝐺𝑚,𝐷𝑖𝑓𝑓 = −𝑔𝑚5
𝑔𝑚5
❑ 𝐺𝑚,𝐶𝑀 = − 1+ 𝑔
𝑚5 +𝑔𝑚𝑏5 2𝑅𝑠𝑠
❑ 𝐴𝑣 = 𝐺𝑚 𝑅𝑜𝑢𝑡
1
❑ 𝐵𝑊 = 2𝜋𝑅
𝑜𝑢𝑡 𝐶𝑜𝑢𝑡
❑ 𝐺𝐵𝑊 = 𝐴𝑣,𝐷𝑖𝑓𝑓 ∙ 𝐵𝑊
𝐴𝑣,𝐷𝑖𝑓𝑓
❑ 𝐶𝑀𝑅𝑅 = 𝐴𝑣,𝐶𝑀
❑ 𝐶𝑀𝐼𝑅 ≈ 𝑉𝐶𝑁 − 𝑉𝑡ℎ5 − 𝑉𝑔𝑠2 : 𝑉𝑔𝑠5 +𝑉𝑑𝑠𝑎𝑡0
❑ 𝑂𝑢𝑡𝑝𝑢𝑡 𝑠𝑤𝑖𝑛𝑔 ≈ 𝑉𝐶𝑁 − 𝑉𝑡ℎ4 ∶ 𝑉𝐶𝑃 + 𝑉𝑡ℎ3
❑ 𝑉𝐶𝑁 ≈ 𝑉𝑔𝑠2 + 𝑉𝑑𝑠𝑎𝑡1 , 𝑉𝐶𝑃 ≈ 3 − 𝑉𝑑𝑠𝑎𝑡4 − 𝑉𝑔𝑠3
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Self Bias Circuit
o Challenges in Biasing Circuit
▪ Save Current as possible.
▪ M5:VCP is limited: CMIR, Mismatch
▪ M1d: VIN- Detection.
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Startup VDD
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Startup 𝑉𝐷𝐷𝑇𝑟𝑎𝑛
TSt𝑎𝑟𝑡𝑢𝑝 = 850n, 𝐴𝑐𝑐𝑢𝑟𝑎𝑐𝑦 = 1.5%
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Monte Carlo DC Result
𝑰𝒓𝒆𝒇 = 𝟒. 𝟕 𝒖𝑨 𝑽𝒓𝒆𝒇 = 𝟏 𝑽
𝑰𝒒 = 𝟑𝟎 𝒖𝑨
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Monte Carlo AC Result
𝑷𝑴 = 𝟖𝟐 𝑮𝑴=18
𝑷𝑺𝑹𝑹 = −𝟓𝟏. 𝟓 𝒅𝑩
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Design-Layout Considerations
- We want good matching in Mq1, Mq2, M1a,b, R1, R3.
- Mq1, Mq2, R1, R3: to avoid any problem in BGR Function.
- M1a,b: to avoid offset effect.
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Designed System Characteristics
Designed System Over all Characteristics
Performance Parameters Result Spec
Vin 2.45~3.3 Spec: 2.5~3.3
𝑉𝑟𝑒𝑓 1V -
𝑉𝑟𝑒𝑓 (Inaccuracy)@27.12MHz 1.5% 3%
𝐼𝑟𝑒𝑓 4.7u -
Iq 30 uA 50 uA
PM 82 55
GM 18 dB 6 dB
PSR -52 dB -40 dB
Startup Time 0.85 uS 1u
We will Publish Full Banba BGR Layout, Inshallah !
o Mohammed Abdel Nasser
o Ziad Ahmed
o Ahmed Tawfiq
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References
▪ Behzad Razavi, The Design of a Low-Voltage Bandgap Reference [The Analog Mind], IEEE DOI: 10.1109/MSSC.2021.3088963
▪ Behzad Razavi, The Bandgap Reference [A Circuit for All Seasons], IEEE DOI: 10.1109/MSSC.2016.2577978
▪ Mostafa N. Sabry, Hesham Omran, and Mohamed Dessouky, “Systematic design and optimization of operational transconductance
amplifier using gm/ID design methodology”, May 2018, DOI: 10.1016/[Link].2018.02.002
▪ Christopher Saint, Judy Saint,” IC Layout Basics”, 2002 | Published: November 5, 2001.
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