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Clock Signal Toggling in Verilog

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rohobak328
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4 views1 page

Clock Signal Toggling in Verilog

Uploaded by

rohobak328
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd

`timescale 1ns / 1ps

module task3(output reg y);


initial begin
y = 0; // Initialize the output signal
end

integer counter; // Declare a counter


parameter MAX_CYCLES = 100; // Set the maximum number of cycles

always begin
#5 y = ~y; // Toggle the clock signal every 5 ns (100 MHz)
counter = counter + 1; // Increment the counter
if (counter >= MAX_CYCLES) begin
$finish; // Terminate the simulation when the max cycles is reached
end
end

initial begin
counter = 0; // Initialize the counter
end
endmodule

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