Engineering Sector

Digital Electronics Verification Diploma

Eng. Kareem Waseem

Digital Electronics Verification

Diploma

UVM Environment for FIFO Project

BY: Youssef Ekramy

Group: 1

Under the supervision of:

Eng. Kareem Waseem

Table of Contents
1 Project Specifications..................................................................................................................... 4
1.1 Parameters ........................................................................................................................................... 4
1.2 Ports ..................................................................................................................................................... 4
2 UVM Structure............................................................................................................................... 5
3 UVM Data Flow ............................................................................................................................ 6
3.1 Flow Components Description ............................................................................................................ 6
1. Top Module: ........................................................................................................................................... 6
2. UVM Test: .............................................................................................................................................. 6
3. UVM Sequence: ..................................................................................................................................... 6
4. UVM Sequence Item: ............................................................................................................................. 7
5. UVM Environment: ................................................................................................................................ 7
6. UVM Agent: ........................................................................................................................................... 7
7. UVM Sequencer: .................................................................................................................................... 7
8. UVM Driver: .......................................................................................................................................... 7
9. UVM Monitor: ........................................................................................................................................ 8
10. UVM Analysis Components:................................................................................................................ 8
3.2 Flow Summary .................................................................................................................................... 8
4 Verification Plan ............................................................................................................................ 9
4.1 Assertions ............................................................................................................................................ 9
4.2 Covergroups ...................................................................................................................................... 10
4.3 Test Cases .......................................................................................................................................... 11
5 Reported Bugs .............................................................................................................................. 12
6 SystemVerilog Assertions ............................................................................................................ 12
7 UVM System Codes .................................................................................................................... 13
7.1 Design Module Code ......................................................................................................................... 13
7.2 SVA Code ......................................................................................................................................... 15
7.3 Interface Code ................................................................................................................................... 17
7.4 Shared Package ................................................................................................................................. 18
7.5 Configuration Object Package .......................................................................................................... 19
7.6 Sequence Item Package ..................................................................................................................... 20
7.7 Sequences Package ............................................................................................................................ 22
7.8 Sequencer Package ............................................................................................................................ 25
7.9 Driver Package .................................................................................................................................. 26
7.10 Monitor Package ............................................................................................................................ 28
7.11 Scoreboard Package ....................................................................................................................... 30
7.12 Coverage Collector Package .......................................................................................................... 34
7.13 Agent Package ............................................................................................................................... 36
7.14 Test Package .................................................................................................................................. 38
7.15 Top Module ................................................................................................................................... 40
8 Questa Sim Automation ............................................................................................................... 42
8.1 Automation TCL Code ...................................................................................................................... 42
8.2 Source Files List ................................................................................................................................ 43
9 QuestaSim Waveforms ................................................................................................................ 44
9.1 Whole Simulation Waveform............................................................................................................ 44
9.2 Read Only Waveform........................................................................................................................ 44
9.3 Write Only Waveform ....................................................................................................................... 45
9.4 Read-Write Waveform ...................................................................................................................... 45
10 UVM Report Summary Transcript ........................................................................................... 46
11 QuestaSim Verification Snippets ............................................................................................. 47
11.1 Assertions Snippets........................................................................................................................ 47
11.2 Cover Directives Snippets ............................................................................................................. 47
11.3 Covergroups Snippets .................................................................................................................... 48
11.3.1 Coverpoints ................................................................................................................................ 48
11.3.2 Cross Coverpoints ...................................................................................................................... 49
11.4 Cover Directives ............................................................................................................................ 50
11.5 Assertions ...................................................................................................................................... 50
12 Code Coverage Report ............................................................................................................. 51
12.1 Toggle Coverage............................................................................................................................ 51
12.2 Assertions Coverage ...................................................................................................................... 53
12.3 Branch Coverage ........................................................................................................................... 54
12.4 Condition Coverage ....................................................................................................................... 55
12.5 Directive Coverage ........................................................................................................................ 56
13 Functional Coverage Report ..................................................................................................... 57
13.1 Summary........................................................................................................................................ 57
13.2 Details ............................................................................................................................................ 58
14 Assertions Coverage Report ..................................................................................................... 59
1 Project Specifications
1.1 Parameters

• FIFO_WIDTH: DATA in/out and memory word width (default: 16)

• FIFO_DEPTH: Memory depth (default: 8)

1.2 Ports

Port Direction Function

data_in Write Data: The input data bus used when writing the FIFO.
wr_en Write Enable: If the FIFO is not full, asserting this signal causes data (on
data_in) to be written into the FIFO
rd_en Input Read Enable: If the FIFO is not empty, asserting this signal causes data
(on
data_out) to be read from the FIFO
clk Clock signal
rst_n Active low asynchronous reset
data_out Read Data: The sequential output data bus used when reading from the
FIFO.
full Full Flag: When asserted, this combinational output signal indicates that
the FIFO is full. Write requests are ignored when the FIFO is full,
initiating a write when the FIFO is full is not destructive to the contents
of the FIFO.
almostfull Almost Full: When asserted, this combinational output signal indicates
that only one more write can be performed before the FIFO is full.
empty Empty Flag: When asserted, this combinational output signal indicates
that the FIFO is empty. Read requests are ignored when the FIFO is
Output empty, initiating a read while empty is not destructive to the FIFO.
almostempty Almost Empty: When asserted, this output combinational signal indicates
that only one more read can be performed before the FIFO goes to
empty.
overflow Overflow: This sequential output signal indicates that a write request
(wr_en) was rejected because the FIFO is full. Overflowing the FIFO is
not destructive to the contents of the FIFO.
underflow Underflow: This sequential output signal Indicates that the read request
(rd_en) was rejected because the FIFO is empty. Under flowing the FIFO
is not destructive to the FIFO.
wr_ack Write Acknowledge: This sequential output signal indicates that a write
request (wr_en) has succeeded.

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2 UVM Structure

Figure 1 : UVM Structure UML Diagram

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3 UVM Data Flow

Figure 2 : UVM Data Flow Illustration through UML Sequence Diagram

3.1 Flow Components Description

1. Top Module:

The simulation begins here. The Top Module is the root of the hierarchy, responsible for initializing the
verification process. It performs key tasks such as:

• Generating clocks and setting up the environment for the simulation.

• Instantiating the DUT (Design Under Test).
• Importing necessary test packages and binding assertions for error checking.
• Setting up the virtual interface in the UVM configuration database, which ensures the interface is
accessible throughout the test.
• Ultimately, it runs the test by invoking the UVM Test, marking the start of the verification process.

2. UVM Test:

The UVM Test acts as the orchestrator, responsible for setting up and managing the entire environment:

• Building the environment: It initializes various verification components such as the UVM agent,
scoreboard, and coverage collector.
• Handling configuration: The test retrieves the virtual interface from the database and applies the
configuration object.
• Starting sequences: It triggers the execution of stimulus by instructing the UVM Sequencer to
begin processing sequences.

3. UVM Sequence:

The UVM Sequence forms the core of the stimulus generation process:

• Generating Sequence Items: It generates a series of transactions (called sequence items) which
drive the verification of the DUT. These items represent various test scenarios and input data for the
DUT.

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4. UVM Sequence Item:

The Sequence Item contains the data required for communication with the DUT:

• These items are typically generated randomly, based on predefined constraints, to explore different
corner cases and conditions within the design.

5. UVM Environment:

The UVM Environment sets up the larger structure that connects various verification components:

• Building components: It creates the UVM agent, scoreboard, and coverage collector.
• Connecting agents: It ensures that the components communicate properly, particularly the monitor,
driver, and analysis components.

6. UVM Agent:

The UVM Agent is responsible for organizing key verification components:

• Building the monitor, sequencer, and driver: These components are essential for observing the
DUT, generating transactions, and driving signals.
• Managing connections: It connects the sequencer and driver, ensuring the sequencer sends
transactions to the driver.
• Setting up interfaces: The agent retrieves the configuration object from the database and assigns the
virtual interface to both the monitor and driver.

7. UVM Sequencer:

The UVM Sequencer acts as a FIFO (First In, First Out) buffer:

• Managing sequence items: It holds the sequence items generated by the sequence and forwards
them to the driver when ready. This ensures a controlled flow of transactions.

8. UVM Driver:

The UVM Driver handles the execution of transactions on the DUT:

• Pulling sequence items: It retrieves the sequence items from the sequencer and translates them into
real input signals.
• Driving signals: The driver assigns the input signals to the virtual interface, which directly interacts
with the DUT to apply the test stimuli.

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9. UVM Monitor:

The UVM Monitor observes the DUT’s responses:

• Gathering signals: It collects signals from the DUT via the virtual interface.
• Translating signals: The monitor converts these signals into sequence items, representing the
observed behavior of the DUT.
• Broadcasting data: It sends the sequence items to the analysis components (the scoreboard and
coverage collector) for evaluation.

10. UVM Analysis Components:

There are two key analysis components in the UVM structure:

• UVM Scoreboard: This component compares the actual outputs from the DUT (collected by the
monitor) with the expected outputs from a reference model. If mismatches are found, it flags
functional errors.
• Functional Coverage Collector: This component samples the data received from the monitor and
tracks how much of the DUT's functionality has been verified. It helps ensure that all corner cases
have been tested.

3.2 Flow Summary

The Top Module initiates the test by setting up the environment, including the DUT and the virtual
interface. The UVM Test builds the setup, triggers the UVM Sequence, and starts the flow of transactions.
The Sequencer generates sequence items (transactions) and forwards them to the Driver, which applies
these stimuli to the DUT. The Monitor observes the responses from the DUT, sending them to the
Scoreboard for comparison and to the Coverage Collector for tracking test progress. Throughout this
process, the Agent manages the interaction between components, ensuring smooth execution of the test
sequence.

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4 Verification Plan
4.1 Assertions

Label Design Requirement Stimulus Generation Functional Functionality

Description Coverage Check
Overflow_Cond This sequential output Randomization Cover all the Concurrent
ition signal indicates that a triggered under the signals and the assertion for this
write request constraint of limiting property for property to test
(wr_en) was rejected signal (rst_n) to be not this assertion. the signal
because the FIFO is active 98% assignment
full. Overflowing the
FIFO is not destructive
to the contents of the
FIFO.
Underflow_Con This sequential output Randomization Cover all the Concurrent
dition signal Indicates that the triggered under the signals and the assertion for this
read request (rd_en) constraint of limiting property for property to test
was rejected because signal (rst_n) to be not this assertion. the signal
the FIFO is empty. active 98% assignment
Under flowing the FIFO
is not destructive to the
FIFO.
Full_Condition When asserted, this Randomization Cover all the Concurrent
combinational output triggered under the signals and the assertion for this
signal indicates that the constraint of limiting property for property to test
FIFO is full. Write signal (rst_n) to be not this assertion. the signal
requests are ignored active 98% assignment
when the FIFO is full,
initiating a write when
the FIFO is full is not
destructive to the
contents of the FIFO.
AlmostFull_Co When asserted, this Randomization Cover all the Concurrent
ndition combinational output triggered under the signals and the assertion for this
signal indicates constraint of limiting property for property to test
that only one more signal (rst_n) to be not this assertion. the signal
write can be performed active 98% assignment
before the FIFO is full.
Empty_Conditi When asserted, this Randomization Cover all the Concurrent
on combinational output triggered under the signals and the assertion for this
signal indicates that the constraint of limiting property for property to test
FIFO is empty. Read signal (rst_n) to be not this assertion. the signal
requests are ignored active 98% assignment
when the FIFO is
empty, initiating a read
while empty is not
destructive to the FIFO.
AlmostEmpty_ When asserted, this Randomization Cover all the Concurrent
Condition output combinational triggered under the signals and the assertion for this
signal indicates constraint of limiting property for property to test
that only one more read signal (rst_n) to be not this assertion. the signal
can be performed active 98% assignment

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 before the FIFO goes to
empty.
WR_ack_Condi This sequential output Randomization Cover all the Concurrent
tion signal indicates that a triggered under the signals and the assertion for this
write request (wr_en) constraint of limiting property for property to test
has succeeded. signal (rst_n) to be not this assertion. the signal
active 98% assignment

4.2 Covergroups

Label Covergroup Target Signals Functionality Check

Description
WRITE_cp Cover the target signals Wr_en The built-in QuestaSim
with all possible values coverage check system
READ_cp Cover the target signals Rd_en The built-in QuestaSim
with all possible values coverage check system
WRITE_ACK_cp Cover the target signals Wr_ack The built-in QuestaSim
with all possible values coverage check system
UNDERFLOW_cp Cover the target signals Underflow The built-in QuestaSim
with all possible values coverage check system
FULL_cp Cover the target signals Full The built-in QuestaSim
with all possible values coverage check system
EMPTY_cp Cover the target signals Empty The built-in QuestaSim
with all possible values coverage check system
ALMOSTFULL_cp Cover the target signals Almostfull The built-in QuestaSim
with all possible values coverage check system
ALMOSTEMPTY_cp Cover the target signals Almostempty The built-in QuestaSim
with all possible values coverage check system
OVERFLOW_cp Cover the target signals overflow The built-in QuestaSim
with all possible values coverage check system
WRITE_ACK_cross Cover the target signals Wr_en, rd_en, wr_ack The built-in QuestaSim
with all possible values coverage check system
UNDERFLOW_cross Cover the target signals Wr_en, rd_en, The built-in QuestaSim
with all possible values underflow coverage check system
FULL_cross Cover the target signals Wr_en, rd_en, full The built-in QuestaSim
with all possible values coverage check system
EMPTY_cross Cover the target signals Wr_en, rd_en, empty The built-in QuestaSim
with all possible values coverage check system
ALMOSTFULL_cross Cover the target signals Wr_en, rd_en, almostfull The built-in QuestaSim
with all possible values coverage check system
ALMOSTEMPTY_cross Cover the target signals Wr_en, rd_en, The built-in QuestaSim
with all possible values almostempty coverage check system
OVERFLOW_CROSS Cover the target signals Wr_en, rd_en, overflow The built-in QuestaSim
with all possible values coverage check system

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4.3 Test Cases

Label Design Stimulus Functional Functionality

Requirement Generation Coverage Check
Description
FIFO_1 When the reset is Directed at the start Cover all the bins Immediate
asserted, the output of simulation to of the output flags assertion to check
flags should be low prepare the system the reset
functionality
FIFO_2 According to the Randomization Cover all the bins Task built-in the
system description triggered under the with additional testbench to check
detailed in Section constraint of cross coverage bins the data after
1 limiting signal comparing with the
(rst_n) to be not reference model
active 98% and function outputs
Write only
constraint
FIFO_3 According to the Randomization Cover all the bins Task built-in the
system description triggered under the with additional testbench to check
detailed in Section constraint of cross coverage bins the data after
1 limiting signal comparing with the
(rst_n) to be not reference model
active 98% and function outputs
Read only
constraint
FIFO_4 According to the Randomization Cover all the bins Task built-in the
system description triggered under the with additional testbench to check
detailed in Section constraint of cross coverage bins the data after
1 limiting signal comparing with the
(rst_n) to be not reference model
active 98% and function outputs
Read Write
constraint

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5 Reported Bugs
Bug Label Problem Solution
Bug_1 Overflow case once occurred and set We add a reset for the overflow at the reset
the flag , the design is stuck at this condition and the write condition with a
case count less than FIFO_DEPTH
Bug_2 Underflow case once occurred and set We add a reset for the underflow at the reset
the flag , the design is stuck at this condition and the write condition with a
case count greater than ZERO
Bug_3 Overflow is set as a combinational We add it as a sequential output set inside
output in the given design the always block of write block
Bug_4 Underflow is set as a combinational We add it as a sequential output set inside
output in the given design the always block of read block
Bug_5 The count integer isn’t updated We add line for the decrement of the read
according to the design requirement priority when the memory is full
according to wr_en, rd_en and full
flags
Bug_6 The count integer isn’t updated We add line for the increment of the write
according to the design requirement priority when the memory is full
according to wr_en, rd_en and empty
flags
Bug_7 The almost full flag is set at wrong We edit the condition to be set when
condition for the count = condition is FIFO_DEPTH - 1
FIFO_DEPTH-2

6 SystemVerilog Assertions
Feature Assertion
Overflow condition when FIFO is full and write is `@(posedge clk) (full && wr_en) -> ##1 (overflow
enabled == 1))`
Underflow condition when FIFO is empty and read is `@(posedge clk) (empty && rd_en) -> ##1
enabled (underflow == 1))`
FIFO is full when the count reaches FIFO depth `@(posedge clk) (count == FIFO_DEPTH) -> (full ==
1))`
FIFO is almost full when the count reaches depth - 1 `@(posedge clk) (count == FIFO_DEPTH-1) ->
(almostfull == 1))`
FIFO is empty when the count is 0 `@(posedge clk) (count == 0) -> (empty == 1))`
FIFO is almost empty when the count is 1 `@(posedge clk) (count == 1) -> (almostempty == 1))`
Write acknowledge (wr_ack) occurs when write is `@(posedge clk) (wr_en && count < FIFO_DEPTH) -
enabled and FIFO is not full > ##1 (wr_ack == 1))`

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7 UVM System Codes
7.1 Design Module Code

module fifo_dut(data_in, wr_en, rd_en, clk, rst_n, full, empty, almostfull, almostempty,
wr_ack, overflow, underflow, data_out);
parameter FIFO_WIDTH = 16;
parameter FIFO_DEPTH = 8;
input [FIFO_WIDTH-1:0] data_in;
input clk, rst_n, wr_en, rd_en;
output reg [FIFO_WIDTH-1:0] data_out;
output reg wr_ack, overflow, underflow;
output full, empty, almostfull, almostempty;

localparam max_fifo_addr = $clog2(FIFO_DEPTH);

reg [FIFO_WIDTH-1:0] mem [FIFO_DEPTH-1:0];

reg [max_fifo_addr-1:0] wr_ptr, rd_ptr;

reg [max_fifo_addr:0] count;

always @(posedge clk or negedge rst_n) begin

if (!rst_n) begin
wr_ptr <= 0;
overflow <= 0; /* added */
wr_ack <= 0;
end
else if ( wr_en && count < FIFO_DEPTH) begin
mem[wr_ptr] <= data_in;
wr_ack <= 1;
wr_ptr <= wr_ptr + 1;
overflow <= 0; /* added */
end
else begin
wr_ack <= 0;
if (full && wr_en)
overflow <= 1;
else
overflow <= 0;
end
end

always @(posedge clk or negedge rst_n) begin

if (!rst_n) begin
rd_ptr <= 0;
underflow <= 0; /* added */
end
else if (rd_en && count != 0) begin
data_out <= mem[rd_ptr];
rd_ptr <= rd_ptr + 1;
underflow <= 0; /* added */
end

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 else begin
/* Sequential Raise for underflow */
if (empty && rd_en) begin
underflow <= 1;
end else begin
underflow <= 0;
end
end
end

always @(posedge clk or negedge rst_n) begin

if (!rst_n) begin
count <= 0;
end
else begin
if ( ({wr_en, rd_en} == 2'b10) && !full)
count <= count + 1;
else if ( ({wr_en, rd_en} == 2'b01) && !empty)
count <= count - 1;
else if (({wr_en, rd_en} == 2'b11) && full) // priority for write operation
count <= count - 1;
else if (({fifo_if.wr_en, fifo_if.rd_en} == 2'b11) &&empty) // priority for
read operation
count <= count + 1;
end
end

assign full = (count == FIFO_DEPTH)? 1 : 0;

assign empty = (count == 0)? 1 : 0;

/* assign fifo_if.underflow = (fifo_if.empty && fifo_if.rd_en)? 1 : 0; Should be

sequential */

/* almost full is raised when fifo_if.count = FIFO_DEPTH -1 not -2 */

assign almostfull = (count == FIFO_DEPTH-1)? 1 : 0;

assign almostempty = (count == 1)? 1 : 0;

endmodule

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7.2 SVA Code

/* File Description : This file should has the assertions using

SystemVerilog and the assertion coverage details */

module fifo_SVA #(parameter FIFO_WIDTH = 16, FIFO_DEPTH = 8)

(
input logic clk,
input logic rst_n,
input logic [FIFO_WIDTH-1:0] data_in,
input logic wr_en,
input logic rd_en,
input logic [FIFO_WIDTH-1:0] data_out,
input logic wr_ack,
input logic overflow,
input logic underflow,
input logic full,
input logic empty,
input logic almostfull,
input logic almostempty,
input logic [$clog2(FIFO_DEPTH):0] count
);

/* ------------------------- Overflow ---------------------------- */

property Overflow_Condition;
@(posedge clk) disable iff(!rst_n) (((full) && (wr_en)) |-> ##1 (overflow == 1));
endproperty

Overflow_Condition_label: assert property(Overflow_Condition)

else $error("full = %0d, wr_en = %0d, overflow = %0d", full, wr_en, overflow);

cover property(Overflow_Condition);

/* ------------------------- Underflow ---------------------------- */

property Underflow_Condition;
@(posedge clk) disable iff(!rst_n) (((empty) && (rd_en)) |-> ##1 (underflow ==
1));
endproperty

Underflow_Condition_label: assert property(Underflow_Condition)

else $error("empty = %0d, rd_en = %0d, underflow = %0d", empty, rd_en, underflow);

cover property(Underflow_Condition);

/* --------------------------- Full ------------------------------- */

property Full_Condition;
@(posedge clk) disable iff(!rst_n) (((count == FIFO_DEPTH)) |-> (full == 1));
endproperty

Full_Condition_label: assert property(Full_Condition)

else $error("count = %0d, full = %0d", count, full);

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 cover property(Full_Condition);

/* ------------------------- Almost Full --------------------------- */

property AlmostFull_Condition;
@(posedge clk) disable iff(!rst_n) (((count == FIFO_DEPTH-1)) |-> (almostfull ==
1));
endproperty

AlmostFull_Condition_label: assert property(AlmostFull_Condition)

else $error("count = %0d, almostfull = %0d", count, almostfull);

cover property(AlmostFull_Condition);

/* -------------------------- Empty ------------------------------- */

property Empty_Condition;
@(posedge clk) disable iff(!rst_n) (((count == 0)) |-> (empty == 1));
endproperty

Empty_Condition_label: assert property(Empty_Condition)

else $error("count = %0d, empty = %0d", count, empty);

cover property(Empty_Condition);

/* ----------------------- AlmostEmpty ---------------------------- */

property AlmostEmpty_Condition;
@(posedge clk) disable iff(!rst_n) (((count == 1)) |-> (almostempty == 1));
endproperty

AlmostEmpty_Condition_label: assert property(AlmostEmpty_Condition)

else $error("count = %0d, almostempty = %0d", count, almostempty);

cover property(AlmostEmpty_Condition);

/* ------------------------ Wr_ack flag --------------------------- */

property WR_ack_Condition;
@(posedge clk) disable iff(!rst_n) (((wr_en && count < FIFO_DEPTH)) |-> ##1
(wr_ack == 1));
endproperty

WR_ack_Condition_label: assert property(WR_ack_Condition)

else $error("count = %0d, wr_en = %0d, wr_ack = %0d", count, wr_en, wr_ack);

cover property(WR_ack_Condition);

endmodule

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7.3 Interface Code

import shared_pkg::*;

interface fifo_interface(clk);
/* The input of interface is the CLK only */
input bit clk;

/* ------------------------- Parameters --------------------- */

/* FIFO_WIDTH: DATA in/out and memory word width (default: 16)*/

parameter FIFO_WIDTH = 16;

/* FIFO_DEPTH: FIFO depth (default: 8) */

parameter FIFO_DEPTH = 8;

/* --------------------------- Inputs ----------------------- */

/* Write Data: The input data bus used when writing the FIFO. */
logic [FIFO_WIDTH-1:0] data_in;

/* Active low asynchronous reset */

logic rst_n;

/* Write Enable: If the FIFO is not full, asserting this signal

causes data (on data_in) to be written into the FIFO */
logic wr_en;

/* Read Enable: If the FIFO is not empty, asserting this signal

causes data (on data_out) to be read from the FIFO */
logic rd_en;

/* --------------------------- Outputs ---------------------- */

/* Read Data: The sequential output data bus used when reading
from the FIFO. */
logic [FIFO_WIDTH-1:0] data_out;

/* Write Acknowledge: This sequential output signal indicates

that a write request (wr_en) has succeeded. */
logic wr_ack;

/* Underflow: This sequential output signal Indicates that the

read request (rd_en) was rejected because the FIFO is empty.
Under flowing the FIFO is not destructive to the FIFO. */
logic underflow;

/* Full Flag: When asserted, this combinational output signal

indicates that the FIFO is full. Write requests are ignored
when the FIFO is full, initiating a write when the FIFO is full
is not destructive to the contents of the FIFO. */

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 logic full;
/* Empty Flag: When asserted, this combinational output signal
indicates that the FIFO is empty. Read requests are ignored when
the FIFO is empty, initiating a read while empty is not destructive
to the FIFO. */
logic empty;

/* Almost Full: When asserted, this combinational output signal

indicates that only one more write can be performed before the
FIFO is full. */
logic almostfull;

/* Almost Empty: When asserted, this output combinational signal

indicates that only one more read can be performed before the FIFO
goes to empty. */
logic almostempty;

/* Overflow: This sequential output signal indicates that a write

request (wr_en) was rejected because the FIFO is full. Overflowing
the FIFO is not destructive to the contents of the FIFO. */
logic overflow;

endinterface //FIFO_Interface(clk)

7.4 Shared Package

package shared_pkg;
/* Integers to follow the count of the errors
and passed tests in TB */
int error_count = 0;
int correct_count = 0;

/* Signal that raises a flag when the test is

finished */
bit test_finished = 0;

endpackage

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7.5 Configuration Object Package

/* File Description: Configuration Object refers to an object

that holds configuration settings and
parameters for UVM components */

package fifo_config_pkg;
/* ---------------- Import UVM packages -------------- */
`include "uvm_macros.svh"
import uvm_pkg::*;

class fifo_config_obj extends uvm_object;

/* Add the UVM object to the UVM factory */
`uvm_object_utils(fifo_config_obj)

/* Create a virtual interface for configuration object */

virtual fifo_interface fifo_config_vif;

/* Configuration Object Constructor */

function new(string name = "fifo_config_obj");
[Link](name);
endfunction
endclass
endpackage

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7.6 Sequence Item Package

/* File Description : UVM Sequence Item should contain::

- Data Fields to communicate with the DUT
- Random stimulus is generated
- Functions can be added to compare/copy/display
different sequence item fields */

package fifo_sequence_item_pkg;
/* ---------------- Import UVM packages -------------- */
`include "uvm_macros.svh"
import uvm_pkg::*;

import shared_pkg::*;
/* ------------------------- Parameters --------------------- */
parameter FIFO_WIDTH = 16;
parameter FIFO_DEPTH = 8;

class fifo_sequence_item extends uvm_sequence_item;

/* Add the UVM object to the UVM factory */
`uvm_object_utils(fifo_sequence_item)

/* The randomized inputs and their outputs */

/* --------------------------- Inputs ----------------------- */
rand logic [FIFO_WIDTH-1:0] data_in;
rand logic rst_n, wr_en, rd_en;

/* --------------------------- Outputs ---------------------- */

logic [FIFO_WIDTH-1:0] data_out;
logic wr_ack, overflow;
logic full, empty, almostfull, almostempty, underflow ;

/* --------------------- Transaction Integers ---------------- */

integer RD_EN_ON_DIST = 30;
integer WR_EN_ON_DIST = 70;

/* ============================================================ */

/* ------------------------- Constraints ---------------------- */

/* Constraint for rst_n to be deasserted */

constraint reset_c {
rst_n dist { 0 := 2, 1:=98};
}

/* Constraint the write enable to be high / low according to

distribution of the value WR_EN_ON_DIST */
constraint WR_EN_c {
wr_en dist { 1 := WR_EN_ON_DIST ,
0 := 100 - WR_EN_ON_DIST};
}

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 /* Constraint the write enable to be high / low according to
distribution of the value RD_EN_ON_DIST */
constraint RD_EN_c {
rd_en dist { 1 := RD_EN_ON_DIST ,
0 := 100 - RD_EN_ON_DIST};
}

/* Constraint the write only to enable write and disable read */

constraint WR_ONLY {
wr_en == 1'b1 && rd_en == 1'b0;
}

/* Constraint the write only to enable write and disable read */

constraint RD_ONLY {
rd_en == 1'b1 && wr_en == 1'b0;
}

/* Sequence Item Constructor */

function new(string name = "fifo_sequence_item");
[Link](name);
endfunction

/* Return the data passed to DUT and GM */

function string convert2string();
return $sformatf("%s reset = %0b, data_in = %0b, wr_en = %0b, rd_en = %0b,
data_out = %0d",// data_out_GM = %0d,
super.convert2string(), rst_n, data_in, wr_en, rd_en, data_out);//,
data_out_GM);
endfunction

function string convert2string_stimulus();

return $sformatf("%s reset = %0b, data_in = %0b, wr_en = %0b, rd_en = %0b",
super.convert2string(), rst_n, data_in, wr_en, rd_en);
endfunction

endclass
endpackage

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7.7 Sequences Package

/* File Description : UVM Sequence should contain::

- Core stimulus of any verification plan
- Made up of several Sequence items
- Main stimulus is written within body() task */

package fifo_sequence_pkg;
/* ---------------- Import UVM packages -------------- */
`include "uvm_macros.svh"
import uvm_pkg::*;

/* -------------- Import Hierarchy packages ---------- */

import fifo_sequence_item_pkg::*;
import shared_pkg::*;

/* ----------------- RESET Sequence Class ----------- */

class fifo_reset_sequence extends uvm_sequence #(fifo_sequence_item);
/* Add the UVM object to the UVM factory */
`uvm_object_utils(fifo_reset_sequence)

/* Create the sequence item */

fifo_sequence_item fifo_seq_item;

/* Sequence Constructor */
function new(string name = "fifo_reset_sequence");
[Link](name);
endfunction

/* Main body() task */

task body();
/* Create the sequence item in the factory */
fifo_seq_item = fifo_sequence_item::type_id::create("fifo_seq_item");

start_item(fifo_seq_item);
/* Edittable area in the sequence body() task */
fifo_seq_item.rst_n = 0;
fifo_seq_item.wr_en = 0;
fifo_seq_item.rd_en = 0;
finish_item(fifo_seq_item);
endtask
endclass

/* ----------------- Write Only Sequence Class ----------- */

class fifo_writeOnly_sequence extends uvm_sequence #(fifo_sequence_item);
/* Add the UVM object to the UVM factory */
`uvm_object_utils(fifo_writeOnly_sequence)

/* Create the sequence item */

fifo_sequence_item fifo_seq_item;

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 /* Sequence Constructor */
function new(string name = "fifo_writeOnly_sequence");
[Link](name);
endfunction

/* Main body() task */

task body();
/* Edittable area in the sequence body() task */
repeat(1000) begin
/* Create the sequence item in the factory */
fifo_seq_item = fifo_sequence_item::type_id::create("fifo_seq_item");

fifo_seq_item.reset_c.constraint_mode(1);
fifo_seq_item.WR_EN_c.constraint_mode(0);
fifo_seq_item.RD_EN_c.constraint_mode(0);
fifo_seq_item.WR_ONLY.constraint_mode(1);
fifo_seq_item.RD_ONLY.constraint_mode(0);

start_item(fifo_seq_item);
assert(fifo_seq_item.randomize());
finish_item(fifo_seq_item);
end

endtask
endclass

/* ----------------- Read Only Sequence Class ----------- */

class fifo_readOnly_sequence extends uvm_sequence #(fifo_sequence_item);
/* Add the UVM object to the UVM factory */
`uvm_object_utils(fifo_readOnly_sequence)

/* Create the sequence item */

fifo_sequence_item fifo_seq_item;

/* Sequence Constructor */
function new(string name = "fifo_readOnly_sequence");
[Link](name);
endfunction

/* Main body() task */

task body();
/* Edittable area in the sequence body() task */
repeat(1000) begin
/* Create the sequence item in the factory */
fifo_seq_item = fifo_sequence_item::type_id::create("fifo_seq_item");

fifo_seq_item.reset_c.constraint_mode(1);
fifo_seq_item.WR_EN_c.constraint_mode(0);
fifo_seq_item.RD_EN_c.constraint_mode(0);
fifo_seq_item.WR_ONLY.constraint_mode(0);
fifo_seq_item.RD_ONLY.constraint_mode(1);

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 start_item(fifo_seq_item);
assert(fifo_seq_item.randomize());
finish_item(fifo_seq_item);
end

endtask
endclass

/* ----------------- Read Write Sequence Class ----------- */

class fifo_readWrite_sequence extends uvm_sequence #(fifo_sequence_item);
/* Add the UVM object to the UVM factory */
`uvm_object_utils(fifo_readWrite_sequence)

/* Create the sequence item */

fifo_sequence_item fifo_seq_item;

/* Sequence Constructor */
function new(string name = "fifo_readWrite_sequence");
[Link](name);
endfunction

/* Main body() task */

task body();
/* Edittable area in the sequence body() task */
repeat(15000) begin
/* Create the sequence item in the factory */
fifo_seq_item = fifo_sequence_item::type_id::create("fifo_seq_item");

fifo_seq_item.reset_c.constraint_mode(1);
fifo_seq_item.WR_EN_c.constraint_mode(1);
fifo_seq_item.RD_EN_c.constraint_mode(1);
fifo_seq_item.WR_ONLY.constraint_mode(0);
fifo_seq_item.RD_ONLY.constraint_mode(0);

start_item(fifo_seq_item);
assert(fifo_seq_item.randomize());
finish_item(fifo_seq_item);
end

endtask
endclass
endpackage

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7.8 Sequencer Package

/* File Description: UVM SEQUENCER should contain::

- Generates transactions as class objects
- Sends it to the driver for execution */

package fifo_sequencer_pkg;
/* ---------------- Import UVM packages -------------- */
`include "uvm_macros.svh"
import uvm_pkg::*;

/* -------------- Import Hierarchy packages ---------- */

import fifo_sequence_item_pkg::*;

class fifo_sequencer extends uvm_sequencer #(fifo_sequence_item);

/* Add the UVM component to the UVM factory */
`uvm_component_utils(fifo_sequencer)

/* SEQUENCER constructor */
function new(string name = "fifo_sequencer", uvm_component parent = null);
[Link](name, parent);
endfunction
endclass
endpackage

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7.9 Driver Package

/* File Description: UVM DRIVER should contain::

- Pulls the next sequence item from sequencer
- Drives the sequence item in the run_phase task using
virtual interface */

package fifo_driver_pkg;
/* ---------------- Import UVM packages -------------- */
`include "uvm_macros.svh"
import uvm_pkg::*;

/* -------------- Import Hierarchy packages ---------- */

// import fifo_config_pkg::*;
import fifo_sequencer_pkg::*;
import fifo_sequence_item_pkg::*;

class fifo_driver extends uvm_driver #(fifo_sequence_item);

/* Add the UVM component to the UVM factory */
`uvm_component_utils(fifo_driver)

virtual fifo_interface drv_vif;

// fifo_config_obj fifo_config_obj_driver;
fifo_sequence_item stim_seq_item;

function new(string name = "fifo_driver",uvm_component parent = null);

[Link](name,parent);
endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);
endfunction

function void connect_phase (uvm_phase phase);

super.connect_phase(phase);
endfunction

task run_phase(uvm_phase phase);

super.run_phase(phase);

/* Connect the randomized sequence item to the virtual if */

forever begin
stim_seq_item = fifo_sequence_item::type_id::create("stim_seq_item");
seq_item_port.get_next_item(stim_seq_item);

/* Connect the driver with the stimulus sequence item */

drv_vif.rst_n = stim_seq_item.rst_n ;
drv_vif.data_in = stim_seq_item.data_in ;
drv_vif.wr_en = stim_seq_item.wr_en ;
drv_vif.rd_en = stim_seq_item.rd_en ;

@(negedge drv_vif.clk);

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 seq_item_port.item_done();

`uvm_info("run_phase",stim_seq_item.convert2string_stimulus(),UVM_HIGH);
end
endtask //run_phase
endclass

endpackage

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7.10 Monitor Package

/* File Description : UVM MONITOR should contain::

- Capture Signal Information from DUT ports
- Translate it to sequence items
- Send sequence items to analysis components */

package fifo_monitor_pkg;
/* ---------------- Import UVM packages -------------- */
`include "uvm_macros.svh"
import uvm_pkg::*;

/* -------------- Import Hierarchy packages ---------- */

import fifo_sequence_item_pkg::*;
import fifo_driver_pkg::*;

class fifo_monitor extends uvm_monitor;

/* Add the UVM component to the UVM factory */
`uvm_component_utils(fifo_monitor)

virtual fifo_interface mon_vif;

fifo_sequence_item rsp_seq_item;
uvm_analysis_port #(fifo_sequence_item) mon_ap;

/* MONITOR Constructor */
function new(string name = "fifo_monitor",uvm_component parent = null);
[Link](name,parent);
endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);
mon_ap = new("mon_ap", this);
endfunction

task run_phase(uvm_phase phase);

super.run_phase(phase);
forever begin
rsp_seq_item = fifo_sequence_item::type_id::create("rsp_seq_item");

@(negedge mon_vif.clk);
/* Connect inputs */
rsp_seq_item.rst_n = mon_vif.rst_n;
rsp_seq_item.data_in = mon_vif.data_in;
rsp_seq_item.wr_en = mon_vif.wr_en;
rsp_seq_item.rd_en = mon_vif.rd_en;

/* Connect outputs */
rsp_seq_item.data_out = mon_vif.data_out;
rsp_seq_item.wr_ack = mon_vif.wr_ack;
rsp_seq_item.underflow = mon_vif.underflow;
rsp_seq_item.overflow = mon_vif.overflow;
rsp_seq_item.full = mon_vif.full;

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 rsp_seq_item.empty = mon_vif.empty;
rsp_seq_item.almostfull = mon_vif.almostfull;
rsp_seq_item.almostempty = mon_vif.almostempty;

mon_ap.write(rsp_seq_item);
`uvm_info("run_phase", rsp_seq_item.convert2string(), UVM_HIGH)
end
endtask

endclass

endpackage

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7.11 Scoreboard Package

/* File Description: UVM SCOREBOARD should contain::

- Receives sequence items from the monitor
- Runs the inputs to reference model
- Compare DUT output with expected output */

package fifo_scoreboard_pkg;
/* ---------------- Import UVM packages -------------- */
`include "uvm_macros.svh"
import uvm_pkg::*;

/* -------------- Import Hierarchy packages ---------- */

import fifo_sequence_item_pkg::*;

class fifo_scoreboard extends uvm_scoreboard;

/* Add the UVM component to the UVM factory */
`uvm_component_utils(fifo_scoreboard)

uvm_analysis_export #(fifo_sequence_item) sb_export;

uvm_tlm_analysis_fifo #(fifo_sequence_item) sb_fifo;
fifo_sequence_item seq_item_sb;

/* reference outputs signals */

bit[FIFO_WIDTH-1:0] GM_model[$];
logic [FIFO_WIDTH-1:0] data_out_GM;
logic wr_ack_GM, overflow_GM, full_GM, empty_GM, almostfull_GM, almostempty_GM,
underflow_GM;

int error_count = 0;
int correct_count = 0;
int count_sb = 0;
/* -------------------------------- */

/* SCOREBOARD constructor */
function new(string name = "fifo_scoreboard", uvm_component parent = null);
[Link](name, parent);
endfunction

/* Build the scoreboard connections */

function void build_phase(uvm_phase phase);
super.build_phase(phase);
sb_export = new("sb_export", this);
sb_fifo = new("sb_fifo", this);
endfunction

/* Connect the scoreboard with others */

function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
sb_export.connect(sb_fifo.analysis_export);
endfunction

Digital Electronics Verification Diploma Page 30 of 59 UVM FIFO Full Environment

 /* Run the checkers in the scoreboard */
task run_phase(uvm_phase phase);
super.run_phase(phase);

forever begin
/* get sequence item */
sb_fifo.get(seq_item_sb);
/* run the reference model */
reference_model(seq_item_sb);

if (seq_item_sb.data_out != data_out_GM) begin

`uvm_error("run_phase", $sformatf("Comparison failed, transaction
received by the DUT: %s",
seq_item_sb.convert2string()));
error_count++;
end else if (seq_item_sb.wr_ack != wr_ack_GM) begin
`uvm_error("run_phase", $sformatf("Comparison failed, transaction
received by the DUT: %s",
seq_item_sb.convert2string()));
error_count++;
end else if (seq_item_sb.overflow != overflow_GM) begin
`uvm_error("run_phase", $sformatf("Comparison failed, transaction
received by the DUT: %s",
seq_item_sb.convert2string()));
error_count++;
end else if (seq_item_sb.underflow != underflow_GM) begin
`uvm_error("run_phase", $sformatf("Comparison failed, transaction
received by the DUT: %s",
seq_item_sb.convert2string()));
error_count++;
end else if (seq_item_sb.full != full_GM) begin
`uvm_error("run_phase", $sformatf("Comparison failed, transaction
received by the DUT: %s",
seq_item_sb.convert2string()));
error_count++;
end else if (seq_item_sb.empty != empty_GM) begin
`uvm_error("run_phase", $sformatf("Comparison failed, transaction
received by the DUT: %s",
seq_item_sb.convert2string()));
error_count++;
end else if (seq_item_sb.almostfull != almostfull_GM) begin
`uvm_error("run_phase", $sformatf("Comparison failed, transaction
received by the DUT: %s",
seq_item_sb.convert2string()));
error_count++;
end else if (seq_item_sb.almostempty != almostempty_GM) begin
`uvm_error("run_phase", $sformatf("Comparison failed, transaction
received by the DUT: %s",
seq_item_sb.convert2string()));
error_count++;
end
else begin

Digital Electronics Verification Diploma Page 31 of 59 UVM FIFO Full Environment

 `uvm_info("run_phase", $sformatf("Correct output: %s",
seq_item_sb.convert2string()), UVM_LOW);
correct_count++;
end
end
endtask

/* Function Description:
Reference_model behaves as the required of the Design
to check its functionality */
task reference_model(input fifo_sequence_item fifo_seq_ref);
fork
/* First Thread: Write Operation Logic */
begin

if (!fifo_seq_ref.rst_n) begin
wr_ack_GM = 0;
overflow_GM = 0;
count_sb = 0;
GM_model.delete();
end
else if (fifo_seq_ref.wr_en && count_sb < FIFO_DEPTH) begin
GM_model.push_back(fifo_seq_ref.data_in) ;
wr_ack_GM = 1;
overflow_GM = 0;
end
else begin
wr_ack_GM = 0;
if ((count_sb == FIFO_DEPTH) && fifo_seq_ref.wr_en)
overflow_GM = 1;
else
overflow_GM = 0;
end

end

/* Second Thread: Read Operation Logic */

begin

if(!fifo_seq_ref.rst_n) begin
underflow_GM = 0;
end
else if ( fifo_seq_ref.rd_en && count_sb != 0 ) begin
data_out_GM = GM_model.pop_front();
underflow_GM = 0;
end
else begin
if((count_sb == 0)&& fifo_seq_ref.rd_en)
underflow_GM = 1 ;
else
underflow_GM = 0 ;
end

Digital Electronics Verification Diploma Page 32 of 59 UVM FIFO Full Environment

 end

/* Update the count according to the other flags */

begin
if(!fifo_seq_ref.rst_n) begin
count_sb = 0;
end
else if ( ({fifo_seq_ref.wr_en, fifo_seq_ref.rd_en} == 2'b10) &&
count_sb != FIFO_DEPTH)
count_sb = count_sb + 1;
else if ( ({fifo_seq_ref.wr_en, fifo_seq_ref.rd_en} == 2'b01) &&
count_sb != 0)
count_sb = count_sb - 1;
else if ( ({fifo_seq_ref.wr_en, fifo_seq_ref.rd_en} == 2'b11) &&
count_sb == FIFO_DEPTH)
count_sb = count_sb - 1;
else if ( ({fifo_seq_ref.wr_en, fifo_seq_ref.rd_en} == 2'b11) &&
count_sb == 0)
count_sb = count_sb + 1;

end

join /* End of Fork Join */

/* Update the flags */

full_GM = (count_sb == FIFO_DEPTH)? 1 : 0;
empty_GM = (count_sb == 0)? 1 : 0;
almostfull_GM = (count_sb == FIFO_DEPTH-1)? 1 : 0;
almostempty_GM = (count_sb == 1)? 1 : 0;

endtask

/* Report the resulted outputs */

function void report_phase(uvm_phase phase);
super.report_phase(phase);
`uvm_info("report_phase", $sformatf("Total successful counts: %0d",
correct_count), UVM_MEDIUM);
`uvm_info("report_phase", $sformatf("Total failed counts: %0d", error_count),
UVM_MEDIUM);
endfunction

endclass
endpackage

Digital Electronics Verification Diploma Page 33 of 59 UVM FIFO Full Environment

7.12 Coverage Collector Package

/* File Description: UVM COVERAGE should contain::

- Receives sequence items from the monitor
- Samples the data fields for the functional coverage */

package fifo_coverage_collector_pkg;
/* ---------------- Import UVM packages -------------- */
`include "uvm_macros.svh"
import uvm_pkg::*;

/* -------------- Import Hierarchy packages ---------- */

import fifo_sequence_item_pkg::*;
import shared_pkg::*;

class fifo_coverage extends uvm_component;

/* Add the UVM component to the UVM factory */
`uvm_component_utils(fifo_coverage)
uvm_analysis_export #(fifo_sequence_item) cov_export;
uvm_tlm_analysis_fifo #(fifo_sequence_item) cov_fifo;
fifo_sequence_item seq_item_cov;

/* -------------------- Transaction Covergroup ------------------- */

covergroup FIFO_cg;
WRITE_cp : coverpoint seq_item_cov.wr_en {
bins wr_en_0 = {0};
bins wr_en_1 = {1};
}

READ_cp : coverpoint seq_item_cov.rd_en {

bins rd_en_0 = {0};
bins rd_en_1 = {1};
}

WRITE_ACK_cp : coverpoint seq_item_cov.wr_ack {

bins wr_ack_0 = {0};
bins wr_ack_1 = {1};
}

UNDERFLOW_cp : coverpoint seq_item_cov.underflow {

bins underflow_0 = {0};
bins underflow_1 = {1};
}

FULL_cp : coverpoint seq_item_cov.full {

bins full_0 = {0};
bins full_1 = {1};
}

EMPTY_cp : coverpoint seq_item_cov.empty{

bins empty_0 = {0};
bins empty_1 = {1};

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 }

ALMOSTFULL_cp : coverpoint seq_item_cov.almostfull{

bins almostfull_0 = {0};
bins almostfull_1 = {1};
}

ALMOSTEMPTY_cp : coverpoint seq_item_cov.almostempty{

bins almostempty_0 = {0};
bins almostempty_1 = {1};
}
OVERFLOW_cp : coverpoint seq_item_cov.overflow{
bins overflow_0 = {0};
bins overflow_1 = {1};
[Link] = 0;
}

/* CROSS COVERAGE for each WR_EN, RD_EN, each output */

WRITE_ACK_cross : cross WRITE_cp,READ_cp,WRITE_ACK_cp;
UNDERFLOW_cross : cross WRITE_cp,READ_cp,UNDERFLOW_cp;
FULL_cross : cross WRITE_cp,READ_cp,FULL_cp;
EMPTY_cross : cross WRITE_cp,READ_cp,EMPTY_cp;
ALMOSTFULL_cross : cross WRITE_cp,READ_cp,ALMOSTFULL_cp;
ALMOSTEMPTY_cross: cross WRITE_cp,READ_cp,ALMOSTEMPTY_cp;
OVERFLOW_CROSS : cross WRITE_cp,READ_cp,OVERFLOW_cp;
endgroup

function new(string name = "fifo_coverage", uvm_component parent = null);

[Link](name, parent);
FIFO_cg = new();
endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);
cov_export = new("cov_export", this);
cov_fifo = new("cov_fifo", this);
endfunction

function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
cov_export.connect(cov_fifo.analysis_export);
endfunction

task run_phase(uvm_phase phase);

super.run_phase(phase);
forever begin
cov_fifo.get(seq_item_cov);
FIFO_cg.sample();
end
endtask
endclass
endpackage

Digital Electronics Verification Diploma Page 35 of 59 UVM FIFO Full Environment

7.13 Agent Package

/* File Description : UVM AGENT should contain::

- Builds and Connects the sequencer,driver and monitor
- Sets the configuration for the agent connecting the
interfaces */

package fifo_agent_pkg;
/* ---------------- Import UVM packages -------------- */
`include "uvm_macros.svh"
import uvm_pkg::*;

/* -------------- Import Hierarchy packages ---------- */

import fifo_sequencer_pkg::*;
import fifo_sequence_item_pkg::*;
import fifo_driver_pkg::*;
import fifo_monitor_pkg::*;
import fifo_config_pkg::*;

class fifo_agent extends uvm_agent;

/* Add the UVM object to the UVM factory */
`uvm_component_utils(fifo_agent)

/* Create the components and objects in agent */

fifo_sequencer agt_sqr;
fifo_driver agt_drv;
fifo_monitor agt_mon;
fifo_config_obj fifo_config_obj_agt;

uvm_analysis_port #(fifo_sequence_item) agt_ap;

/* Agent Constructor */
function new(string name = "fifo_agent",uvm_component parent= null);
[Link](name, parent);
endfunction

/* Build the components and objects */

function void build_phase(uvm_phase phase);
super.build_phase(phase);
/* Get the config object from the database */
if(! uvm_config_db
#(fifo_config_obj)::get(this,"","FIFO_VIF_CONFIG",fifo_config_obj_agt))begin
`uvm_fatal("FIFO_AGENT","FIFO_VIF_CONFIG not found in uvm")
end
/* Create the sequence,drver and monitor */
agt_sqr = fifo_sequencer::type_id::create("agt_sqr",this);
agt_drv = fifo_driver::type_id::create("agt_drv",this);
agt_mon = fifo_monitor::type_id::create("agt_mon",this);
/* Create the connection */
agt_ap = new("agt_ap",this);
endfunction

Digital Electronics Verification Diploma Page 36 of 59 UVM FIFO Full Environment

 function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
agt_drv.drv_vif = fifo_config_obj_agt.fifo_config_vif;
agt_mon.mon_vif = fifo_config_obj_agt.fifo_config_vif;
/* Connect the driver to the sequencer */
agt_drv.seq_item_port.connect(agt_sqr.seq_item_export);
/* Connect the monitor analysis port with agent */
agt_mon.mon_ap.connect(agt_ap);
endfunction
endclass
endpackage

Digital Electronics Verification Diploma Page 37 of 59 UVM FIFO Full Environment

7.14 Test Package

/* File Description : UVM Test file should contain ::

- Builds the UVM environment
- Retrieve the virtual interface from Config database
- Sets the config object to config db
- Starts the sequence to the sequencer
- Factory overrides for minimal code modifications */

package fifo_test_pkg;
/* ---------------- Import UVM packages -------------- */
`include "uvm_macros.svh"
import uvm_pkg::*;

/* -------------- Import Hierarchy packages ---------- */

import fifo_config_pkg::*;
import fifo_env_pkg::*;
import fifo_sequence_pkg::*;

class fifo_test extends uvm_test;

/* Add the UVM component to the UVM factory */
`uvm_component_utils(fifo_test)

fifo_env env;
fifo_config_obj fifo_config_obj_test;

fifo_reset_sequence fifo_reset_seq;
fifo_writeOnly_sequence fifo_writeOnly_seq;
fifo_readOnly_sequence fifo_readOnly_seq;
fifo_readWrite_sequence fifo_readWrite_seq;

/* Declare a virtual interface and handle of the environment */

virtual fifo_interface fifo_vif;

/* TEST constructor function */

function new(string name = "fifo_test",uvm_component parent = null);
[Link](name,parent);
endfunction

/* Build Phase function */

function void build_phase(uvm_phase phase);
super.build_phase(phase);

/* Build the environment component */

env = fifo_env::type_id::create("env",this);

/* Build the configuration object */

fifo_config_obj_test =
fifo_config_obj::type_id::create("fifo_config_obj_test",this);

/* Build the different test sequences */

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 fifo_reset_seq =
fifo_reset_sequence::type_id::create("fifo_reset_sequence",this);
fifo_writeOnly_seq =
fifo_writeOnly_sequence::type_id::create("fifo_writeOnly_sequence",this);
fifo_readOnly_seq =
fifo_readOnly_sequence::type_id::create("fifo_readOnly_sequence",this);
fifo_readWrite_seq =
fifo_readWrite_sequence::type_id::create("fifo_readWrite_sequence",this);

/* Retrieve the virtual interface from the configuration database

(uvm_config_db) and pass the value of the virtual interface to
fifo_test_vif */
if(!uvm_config_db #(virtual fifo_interface)::get(this,""
,"FIFO_VIF",fifo_config_obj_test.fifo_config_vif))
`uvm_fatal("build_phase","TEST- ERROR in the virtual interface in
fifo_config_vif")

/* Set the virtual interface fifo_test_vif in the configuration database to

all
the components under the test class so that any component can retrieve
it. */
uvm_config_db
#(fifo_config_obj)::set(this,"*","FIFO_VIF_CONFIG",fifo_config_obj_test);
endfunction
task run_phase(uvm_phase phase);
super.run_phase(phase);
phase.raise_objection(this);

/* RESET sequence */
`uvm_info("run_phase", "RESET asserted", UVM_LOW)
fifo_reset_seq.start([Link].agt_sqr);
`uvm_info("run_phase", "RESET deasserted", UVM_LOW)

/* Write Only sequence */

`uvm_info("run_phase", "WR Only sequence started", UVM_LOW)
fifo_writeOnly_seq.start([Link].agt_sqr);
`uvm_info("run_phase", "WR Only sequence ended ", UVM_LOW)

/* Read Only sequence */

`uvm_info("run_phase", "RD Only sequence started", UVM_LOW)
fifo_readOnly_seq.start([Link].agt_sqr);
`uvm_info("run_phase", "RD Only sequence ended ", UVM_LOW)

/* Read Write sequence */

`uvm_info("run_phase", "WR RD sequence started", UVM_LOW)
fifo_readWrite_seq.start([Link].agt_sqr);
`uvm_info("run_phase", "WR RD sequence ended ", UVM_LOW)

phase.drop_objection(this);
endtask
endclass
endpackage

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7.15 Top Module

/* File Description : Top Module should contain ::

- Root of the hierarchy
- Instantiates the DUT, interface & assertions
- Connects the interface to the DUT
- Clock Generation
- Pass the interface to configuration database
- Run test */

/* ---------------- Import UVM packages -------------- */

import uvm_pkg::*;
`include "uvm_macros.svh"

/* -------------- Import Hierarchy packages ---------- */

import fifo_test_pkg::*;

module top();
bit clk;

/* --------------- Clock Generation --------------- */

initial begin
clk = 0;
forever #1 clk = ~clk;
end

/* ------------ Hierarchy Instantiation ----------- */

/* Instantiate the interface */
fifo_interface fifo_if(clk);

/* Instantiate the DUT module */

fifo_dut DUT (
.clk(clk),
.data_in(fifo_if.data_in),
.wr_en(fifo_if.wr_en),
.rd_en(fifo_if.rd_en),
.rst_n(fifo_if.rst_n),
.full(fifo_if.full),
.empty(fifo_if.empty),
.almostempty(fifo_if.almostempty),
.almostfull(fifo_if.almostfull),
.wr_ack(fifo_if.wr_ack),
.overflow(fifo_if.overflow),
.underflow(fifo_if.underflow),
.data_out(fifo_if.data_out)
);

/* Bind the SVA assertions to DUT */

bind fifo_dut fifo_SVA FIFO_DUT_SVA(
.clk(clk),
.rst_n(DUT.rst_n),
.data_in(DUT.data_in),

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 .wr_en(DUT.wr_en),
.rd_en(DUT.rd_en),
.data_out(DUT.data_out),
.wr_ack(DUT.wr_ack),
.overflow([Link]),
.underflow([Link]),
.full([Link]),
.empty([Link]),
.almostfull([Link]),
.almostempty([Link]),
.count([Link])
);

/* --------------- Run the FIFO test -------------- */

initial begin
/* Pass the Configuration object to interface */
uvm_config_db #(virtual
fifo_interface)::set(null,"uvm_test_top","FIFO_VIF",fifo_if);

/* Run the test (Replace what is in " ") */

run_test("fifo_test");
end
endmodule

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8 Questa Sim Automation
8.1 Automation TCL Code

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8.2 Source Files List

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9 QuestaSim Waveforms
9.1 Whole Simulation Waveform

Figure 3 : Whole Simulation Waveform

9.2 Read Only Waveform

Figure 4 : Read Only Waveform

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9.3 Write Only Waveform

Figure 5 : Write-Only Waveform

9.4 Read-Write Waveform

Figure 6 : Read - Write Waveform

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10 UVM Report Summary Transcript

Figure 7 : UVM Report Summary Transcript

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11 QuestaSim Verification Snippets
11.1 Assertions Snippets

Figure 8 : Assertions Snippet

11.2 Cover Directives Snippets

Figure 9 : Cover Directives Snippets

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11.3 Covergroups Snippets

11.3.1 Coverpoints

Figure 10 : Covergroups Snippets

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11.3.2 Cross Coverpoints

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11.4 Cover Directives

11.5 Assertions

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12 Code Coverage Report
12.1 Toggle Coverage

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Digital Electronics Verification Diploma Page 52 of 59 UVM FIFO Full Environment
12.2 Assertions Coverage

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12.3 Branch Coverage

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12.4 Condition Coverage

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12.5 Directive Coverage

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13 Functional Coverage Report
13.1 Summary

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13.2 Details

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14 Assertions Coverage Report

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