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Clocked Sequential Circuit Design

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20 views34 pages

Clocked Sequential Circuit Design

Digital media

Uploaded by

f20220123
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

DESIGN OF CLOCKED

SEQUENTIAL CIRCUITS
DESIGN WITH UNUSED STATES
• Design the circuit using D Flip Flops
Answer:
Da=A’B’x
Db=C’x’+A+BCx
Dc=A’B’x’+Cx’+Ax
Y=A’x
The circuit is self correcting
STATE REDUCTION
STATE TABLE

Present Next State Output


state X=0 X=1 X=0 X=1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
e a f 0 1
f g f 0 1
g a f 0 1
STATE TABLE

Present Next State Output


state X=0 X=1 X=0 X=1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
e a f 0 1
f g e f 0 1
g a f 0 1
STATE TABLE

Present Next State Output


state X=0 X=1 X=0 X=1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
e a f 0 1
f e f 0 1
STATE TABLE

Present Next State Output


state X=0 X=1 X=0 X=1
a a b 0 0
b c d 0 0
c a d 0 0
d e f d 0 1
e a f d 0 1
f e f 0 1
STATE TABLE

Present Next State Output


state X=0 X=1 X=0 X=1
a a b 0 0
b c d 0 0
c a d 0 0
d e d 0 1
e a d 0 1

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