ANALOG & DIGITAL ELECTRONICS (3130907)

EXPERIMENT – 1
AIM:- To study and perform OP-AMP biasing and parameters

APPARATUS:-
S Range

DC Power supply 0-15V

DC Power supply 0-30V

Digital DC voltmeter 0-15v

0.25W Resistors 10Ω, 100Ω, 1.5K, 5.6K, 10K,

(Ω) (2×270K),120K, 1M

Potentiometer 10KΩ, 0.25W

General purpose op- 741 or equivalent

amp

Bread board

1. Op-amp biasing:

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2. Offset voltage:

3. Open loop voltage gain

PROCEDURE:
1. Op-amp biasing:

i. Construct the Op-amp biasing circuit as shown in the figure.

ii. switch ON the power supply and adjust it for Vcc=15V.

iii. Measure and record the dc voltage with respect to ground at

the op-amp input and output terminals.

iv. Switch off the supply and change the value of resistor.

v. Switch the supply on and again measure and record Vi and Vo.

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vi. Again switch off the supply change the value of resistor.

vii. Repeat the step (d) again.

viii. Switch off the supply and rearrange the circuit to use a single
polarity supply as shown in the figure.

ix. Switch on the supply and adjust it for the Vcc=30V.

x. Measure the dc voltage with respect to ground at the circuit

input and output terminal and record the voltage levels.

Offset voltage and currents

1. connect the op-amp inverting amplifier circuit as shown

in Figure.
2. switch on the power supply and adjust it for the
Vcc=12V

3. measure and record the dc voltage with respect to

ground at the circuit output terminals and calculate the
input offset voltage.

Open loop voltage gain:

1. Connect the circuit as shown in the figure with the dc monitor Vi and Vo.

2. Switch on the op-amp power supply and adjust it for Vcc=12V

3 .Switch on the power supply and adjust it to give Vo=5V

4. Measure and record V3, and calculate the differential input voltage.(
Vdif=V3/1000 )

5 .Calculate the op-amp open loop gain.( Av=Vo/Vdif )

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Common mode rejection ratio :

Connections are made as per the circuit diagram.

1. Give a sinusoidal input of 1 VPP 1 kHz.

2. Switch on the dual power supply.

3. Note down the output voltage from the CRO.

4. Determine the CMRR by the following procedure.

Common mode gain= Ac=Vo/Vi

Differential mode gain =Ad = R2/R1

CMRR= 20 log (Ad/Ac)

OBSERVATION TABLE :

Sr no Input voltage Output voltage

Vi ( volt ) Vo ( volt )

1.

2.

3.

4.

5.

CONCLUSION:

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EXPERIMENT – 2
AIM:- To study operational amplifiers as inverting, non-inverting amplifier and
voltage follower circuits.

APPARATUS:
Equipment Range

Dual Power supply ±15V

Resistors( Ω )

General purpose op-amp 741 or equivalent

CIRCUIT DIAGRAM:

Inverting amplifier Non inverting amplifier

Voltage follower

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PROCEDURE:
1. Connect the circuit for inverting amplifier as shown in the circuit diagram.

2. Measure the output voltage.

3. Note down the observation and repeat the same for other values of Rf and
R1.

4. Repeat steps 1-3 for noninverting amplifier and voltage follower.

OBSERVATION TABLE:
Inverting Amplifier

Sr. Rf R1 Voltage Vout Vout

No. (KΏ) (KΏ) gain (AV (Theo.) (Prac.)
)

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Non inverting Amplifier

Sr. No. Rf R1 Voltage Vout Vout

(KΏ) (KΏ) gain (AV ) (Theo.) (Prac.)

CONCLUSION:

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EXPERIMENT -3
AIM:- To study Op-amp as summing & difference amplifier

APPARATUS:
Equipment Range

Dual Power supply ±15V

DC Voltmeter 0-30 V

Signal Generator

CRO

IC 741

Resistors 1K, 2 K , 2.2 K

CIRCUITDIAGRAM
(a) Op-amp as a summing amplifier:

+
+

R3 -
IC 74 1

R2

R1 Rf

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(b) Op-amp as a differential amplifier:

R3
+
+

R2
-
IC 741

R1 Rf

PROCEDURE:
(a) Op-amp as a summing amplifier:

1. Connect the circuit as shown in the figure.

2. Apply the inputs V1, V2 and V3 and measure VO using DMM.

3. Change the values of the resistors and measure VO.

(b) Op-amp as a differential amplifier:

1. Connect the circuit as shown in the figure.

2. Apply the inputs V1 and V2 and measure VO using DMM.

3. Change the values of the resistors and measure VO.

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OBSERVATION TABLE:
(a) Op-amp as a summing amplifier:

V1 = ______ V , V2 = _____ V, V3 = ______ V

Sr. No. R1 (K) R2 (K) R3 (K) Rf (K) VO (Volts)

1.

2.

3.

4.

(b) Op-amp as a differential amplifier:

V1 = ______ V, V2 = _____ V

Sr. No. R1 (K) R2 (K) R3 (K) Rf (K) VO (Volts)

1.

2.

3.

4.

CONCLUSION:

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EXPERIMENT -4
AIM:- To study the frequency response of operational amplifier.

APPARATUS:-
Equipment Range

DC Power supply 0-15V

Signal generator 0-1MHz

Oscilloscope

0.25W Resistors ( 2×100 Ω), ( 2×1K Ω), 10K, 100K

30V capacitors 3Рf,30рf, 1500рf

General purpose op-amp IC 741

Bread board

CIRCUIT DIAGRAM:

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PROCEDURE:
Op-amp circuit frequency response.

1. Connect the inverting amplifier circuit as shown in the figure using IC 741.

2. Switch on the power supply and adjust it for the Vcc=15V

3. Set the signal generator for a 1 KHz sine wave and adjust the signal
amplitude to produce a 100mV peak to peak circuit output.

4. Record the input voltage ( Vi ) and calculate the close loop gain ( Acl ) then
maintaining the input voltage constant, increase the signal frequency until
the output falls to approximately 70.7 mV peak to peak. Record the upper
cutoff frequency ( F2 )

Slew rate effects

1. Using the inverting amplifier circuit as shown in the figure ( R1=100ohm and
R2=10KΩ ) reset the signal generator for a 1 KHz square wave, and the
signal amplitude to produce a 10V peak to peak output.

2. Measure the output rise time (tr) adjusting the signal frequency as
necessary to give an accurate measurement. Record tr and calculate the
value of SR.

3. Reset the signal to a 1 KHz sine wave and adjust the signal amplitude to
produce a 10Vpeak to peak output.

4. Maintaining the input voltage constant, increase the signal frequency until
the output falls to approximately 7.07V peak to peak. Record the slew rate
limited cutoff frequency (fp) along with the close loop gain and the output
peak amplitude.

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OBSERVATION TABLE:
Sr. Frequency Vin Vout A = Vout / Vin
No.

1.

2.

3.

4.

CONCLUSION:

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EXPERIMENT NO - 5
AIM: To study square wave generator using IC Op-amp

APPARATUS: Bread board, IC 741, resistors, capacitor, CRO, Connecting wires.

CIRCUIT DIAGRAM:

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PROCEDURE:

1) Connect the circuit as shown in the diagram.

2) Connect the power supply.
3) Verify the connections and switch on the supply
4) Observe the waveform across C and output.
5) Measure Ton and Toff time.
6) Repeat the procedure for various values of R.

CALCULATION:

T = 2RCln [(2*R1+R2)/(R2)]
If R2 = 1.16R1
F0 = 1/2RC

CONCLUSION:

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EXPERIMENT NO - 6
AIM: Study Of AND & OR Gates Using diodes
APPARATUS:-Trainer kit, Silicon diode, resistor (1 kilo ohm), wires, multimeter.

CIRCUIT DIAGRAM:-

OR LOGIC GATE

AND LOGIC GATE

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PROCEDURE:-
For OR gate:-

1. Connect Circuit for OR gate as shown in figure on bread board.

2. Apply the Inputs to the P- terminal of the diode.

3. Take +5 volt as logic 1 and ground as logic 0.

4. Connect the multimeter between register and ground as shown in circuit

diagram and observe output on multimeter.

5. Observe the output for various Input combinations.

For AND gate:-

1. Connect Circuit for AND gate as shown in figure on bread board.

2. Apply the Inputs to the n- terminal of both the diode.

3. Take +5 volt as logic 1 and ground as logic 0.

4. Connect the multimeter between junctions of diodes and ground as shown

in circuit diagram and observe output on multimeter.

5. Observe the output for various Input combinations.

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Truth Table
ANDGate:- OR Gate:-

X Y Z x y z

0 0 0 0 0 0

0 15 0 0 15 15

15 0 0 15 0 15

15 15 15 15 15 15

OBSERVATION TABLE:
AND Gate:- OR Gate:-

X y Z x y z

CONCLUSION:

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EXPERIMENT NO - 7
AIM: To study various gates using ICs.

APPARATUS:-connectingwires,IC-7408,IC-7432,IC-7404,IC-7400,IC-7402,IC-
7486

CIRCUIT DIAGRAM:-
AND gate(7408):- NOR gate(7402):-

NAND gate(7400):- OR gate(7432):-

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NOT gate(7404):- EX-OR gate(7486):-

PROCEDURE:-
1. Place the IC of series 7408 for AND gate,7432 for OR gate,7404 for
NOT,7400 for NAND,7402 for NOR and 7486 for XOR horizontally on the
breadboard.

2. We know that the IC comprises of 14 pins. Connect the 7th pin to the
ground.

3. For AND gate, two inputs are given for which one output is obtained.

4. Connect two wires with pin1 and pin2 which act as input and third wire
with pin 3 which gives the output.

5. Switch on the supply and note the readings.

6. Continue the same procedure for NAND, OR and NOR gates.

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TRUTH TABLE:
AND Gate ORGate:-

x Y Z x y z
0 0 0 0 0 0
0 1 0 0 1 1
1 0 0 1 0 1
1 1 1 1 1 1

NOR GATE : NAND GATE :

x Y Z x Y Z
0 0 0 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 1 1 1 0

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XOR GATE: NOT GATE:

x Y Z X Y

0 0 0 0 1

0 1 1 1 0

1 0 1

1 1 0

OBSERVATION TABLE:
AND Gate:- OR Gate:-

X y Z
X y Z

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NOR Gate:- NAND Gate:-

x y Z X y Z

XOR Gate:- NOT Gate:-

x y Z
X Y

CONCLUSION:-

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EXPERIMENT NO - 8
AIM: To study NAND and NOR as universal gates.
APPARATUS:- wires, bread board,IC-7400,IC-7402, multimeter

Circuit Diagram:-

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PROCEDURE:-

NAND AS UNIERSAL GATE:-

--For NOT gate

1. Connect the circuit as shown in figure.

2. Apply same input to pin 1 and 2 to NAND gate (IC 7400) i.e. logic 1 and
logic 0 as +5v and GND resp.

3. Observe output on multimeter with logic 1 as +5v and logic 0 as GND.

--For AND gate

1. Connect the circuit as shown in figure.

2. Apply the input to pin 1 and 2 to NAND gate 1 (IC 7400) i.e. logic 1
and logic 0 as +5v and GND resp.

3. Observe output on multimeter with logic 1 as +5v and logic 0 as GND

from NAND gate 2 pin

--For OR GATE

1. Connect the circuit as shown in figure.

2. Apply same input t x to pin 1 and 2 to NAND gate 1 (IC 7400) i.e. logic 1
or logic 0 as +5v and GND resp.

3. Apply same input t y to pin 4 and 5 to NAND gate 1 (IC 7400) i.e. logic 1
or logic 0 as +5v and GND resp.

4. Observe output on multimeter with logic 1 as +5v and logic 0 as GND

from NAND gate 3 pin

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--For EX-OR GATE

1. Connect the circuit for ex-or gate using NAND gate as shown in figure.

2. Apply input x to pin 1 to NAND gate 1 (IC 7400) i.e. logic 1 and logic 0 as
+5v and GND resp.

3. Apply input y to pin 2 to NAND gate 1 (IC 7400) i.e. logic 1 and logic 0 as
+5v and GND resp.

4. Observe output on multimeter with logic 1 as +5v and logic 0 as GND

from NAND gate 4 pin

NOR AS UNIERSAL GATE:-

-- For NOT gate:-

1. Connect the circuit as shown in figure.

2. Apply same input to pin 2 and 3 to NOR gate (IC 7400) i.e. logic 1 and logic
0 as +5v and GND resp.

3. Observe output on multimeter with logic 1 as +5v and logic 0 as GND on

pin 1 of gate 1.

--For AND gate

1. Connect the circuit as shown in figure.

2. Apply same input i.e x to pin 2 and 3 to NOR gate 1 (IC 7400) i.e. logic 1
and logic 0 as +5v and GND resp.

3. Apply same input i.e y to pin 2 and 3 to NOR gate 2 (IC 7400) i.e. logic 1
and logic 0 as +5v and GND resp.

4. Neither observe output on multimeter with logic 1 as + 5v and logic 0 as

GND from NOR gate 3 pin 10.

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-- For OR GATE

1. Connect the circuit as shown in figure.

2. Apply same input x to pin 2 and 3 to NOR gate 1 (IC 7400) i.e. logic 1 and
logic 0 as +5v and GND resp.

3. Apply same input y to pin 5 and 6 to NOR gate 1 (IC 7400) i.e. logic 1 and
logic 0 as +5v and GND resp.

4. Observe output on multimeter with logic 1 as +5v and logic 0 as GND from
NOR gate 2 pin 4.

--For EX-OR GATE

1. Connect the circuit for EX-OR gate using NOR gate as shown in figure.

2. Apply input x to pin 2 of NOR gate 1 (IC 7400) i.e. logic 1 and logic 0 as +5v
or GND resp.

3. Apply input y to pin 3 of NOR gate 1 (IC 7400) i.e. logic 1 and logic 0 as +5v
or GND resp.

4. Observe output on multimeter with logic 1 as +5v and logic 0 as GND from
NOR gate 4 pin 10.

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TRUTH TABLE:
NOT Gate:- AND Gate:-

A A’ A B A.B

0 1 0 0 0

1 0 0 1 0

1 0 0

1 1 1

OR Gate:- XOR Gate:- XNOR Gate

A B A+B A B F(O/P) A B F(O/P)

0 0 0 0 0 0 0 0 1

0 1 1 0 1 1 0 1 0

1 0 1 1 0 1 1 0 0

1 1 1 1 1 0 1 1 1

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OBSERVATION TABLE:
NOT Gate:- AND Gate:-

A A’ A B A.B

OR Gate:- XOR Gate:- XNOR Gate:-

A B A+B A B F A B F

CONCLUSION:-

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EXPERIMENT NO - 9
AIM: To study about half adder and half subtractor

APPARATUS:- Wires, breadboard, IC-7486, IC-7408, IC-7404

CIRCUIT DIAGRAM:-

Half ADDER: HALF SUBTRACTOR

PROCEDURE:-
FOR HALF ADDER:-

1. Connect the circuit of half adder on breadboard as shown in circuit

diagram.

2. Connect the inputs to pin 1 and pin 2 of EX-OR gate.

3. Observe pin 3 of Ex-OR gate (IC 7486) as output(sum) on multimeter.

4. Observe pin 3 of AND gate (IC 7408) as output(carry) on multimeter.

5. Check outputs sum and carry for various input combinations.

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FOR HALF SUBTRACTOR:-

1. Connect the circuit of half subtractor on breadboard as shown in circuit

diagram.

2. Connect the inputs to pin 1 and pin 2 of EX-OR gate.

3. Observe pin 3 of Ex-OR gate (IC 7486) as output(difference) on multimeter.

4. Observe pin 3 of AND gate (IC 7408) as output(borrow) on multimeter.

5. Check outputs difference and borrow for various input combinations.

NOTE: Verify observation table from truth table with x and y as inputs and s(sum)
and c(carry) as output of Half adder. D(difference) and B(borrow) as output of half
subtractor.

TRUTH TABLE:

Half Adder:- Half Subtractor:-

X Y S C X Y D B

0 0 0 0 0 0 0 0

0 1 1 0 0 1 1 1

1 0 1 0 1 0 1 0

1 1 1 1 1 1 0 0

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Observation Table:

Half Adder:- Half Subtractor:-

X Y C S X Y B D

CONCLUSION:-

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EXPERIMENT NO - 10
AIM: To study about full adder and full subtractor
APPARATUS: - Wires, breadboard, IC-7486, IC-7408, IC-7404, multimeter

CIRCUIT DIAGRAM:-

FULL ADDER:

FULL SUBTRACTOR :

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PROCEDURE:-
FOR FULL ADDER:-

1. Connect the circuit of full adder on breadboard as shown in circuit diagram.

2. Connect the inputs to pin 1 and pin 2 of EX-OR gate 1 and third input to the
pin 1 of EX-OR gate .

3. Observe output on pin 6 of Ex-OR gate 2(IC 7486) as output(sum) on

multimeter.

4. Observe output on pin 3 of OR gate (IC 7432) as output(carry) on

multimeter.

5. Check outputs sum and carry for various input combinations.

FOR FULL SUBTRACTOR:-

1. Connect the circuit of full subtractor on breadboard as shown in circuit

diagram.

2. Connect the inputs to pin 1 and pin 2 of EX-OR gate 1 and third input to the
pin 1 of EX-OR gate 2.

3. Observe output on pin 6 of Ex-OR gate 2(IC 7486) as output(difference) on

multimeter.

4. Observe output on pin 3 of OR gate (IC 7432) as output(borrow) on

multimeter.

5. Check outputs difference and borrow for various input combinations.

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NOTE: : Verify observation table from truth table with x and y as inputs and
s(sum) and c(carry) as output of full adder. D(difference) and B(borrow) as output
of full subtractor.

TRUTH TABLE:

Full Adder:- Full Subtractor:-

X Y Z C S X Y Z C S

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OBSERVATION TABLE:

Full Adder:- Full Subtractor:-

X Y Z C S X Y Z C S

CONCLUSION:

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EXPERIMENT NO - 11
AIM: To study gray to binary conversion.
APPARATUS: trainer kit, bread board,IC-7486
Circuit Diagram:-

PROCEDURE:

1. Connect the circuit for gray to binary code conversion as shown in circuit
diagram.

2. Apply Input A & B to pin no 1 & 2 of Ex-OR gate 1(IC 7486).

3. Apply Input C & Output of Ex-OR gate 1 that is pin no 3 as input to pin no 4
& 5of Ex-OR gate 2.

4. Apply Input D & Output of Ex-OR gate 2 as other input to pin 9 & 10 of Ex-
OR gate 3.

5. Also connect input to A to multimeter as output W.

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6. Also connect Pin no 3 of Ex-OR gate1 as output X to multimeter.

7. Similarly observe output Y & Z from pin no 6 & 8 respectively on

multimeter.

8. Observe output for various Input combinations.

TRUTH TABLE:
A B C D W X Y Z

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 1 0 0 1 0

0 0 1 0 0 0 1 1

0 1 1 0 0 1 0 0

0 1 1 1 0 1 0 1

0 1 0 1 0 1 1 0

0 1 0 0 0 1 1 1

1 1 0 0 1 0 0 0

1 1 0 1 1 0 0 1

1 1 1 1 1 0 1 0

1 1 1 0 1 0 1 1

1 0 1 0 1 1 0 0

1 0 1 1 1 1 0 1

1 0 0 1 1 1 1 0

1 0 0 0 1 1 1 1

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OBSERVATION TABLE:
A B C D W X Y Z

Conclusion:

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EXPERIMENT NO - 12
AIM: To study R-S FLIP-FLOP
APPARATUS: trainer kit, bread board, IC-7486, IC-7408

Circuit Diagram:-

Simple set-reset latches

Gated SR latch

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PROCEDURE:
1. Apply Input R to Pin no 1 of AND gate 1 and Input S to pin no 5 Of AND
gate 2.
2. Connect the output of AND gate 1 to Input of NOR gate 1 that is pin no
2.
3. Output of AND gate 2 is connected to pin no 6 of NOR gate 2.
4. Apply the clock pulse to pin no 2 & 4 of AND gate 1 & 2 respectively.
5. Give the feedback to NOR gate as shown in circuit diagram.
6. Observe the output for various Input combinations on multimeter at pin
no 1 & 4 of NOR gate.

CHARACTERISTIC TABLE/TRUTH TABLE:

Q S R Q(t+1)

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 Indeterminate

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 Indeterminate

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OBSERVATION TABLE:

Q S R Q(t+1)

CONCLUSION:

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EXPERIMENT NO - 13
AIM: To study D FLIP-FLOP
APPARATUS: trainer kit, bread board,IC-7400

Circuit Diagram:-
Gated D latch

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PROCEDURE:
For D-Flip-flop
1. Apply Input D to Pin no 1 of NAND gate 1 of IC 1.
2. Sort Pin no 1 and 2 of NAND gate 1 of IC 2 and apply same Input D to pin no
1.
3. Apply the clock pulse to pin no 2 & 4 of NAND gate 1 & 2 respectively of IC
1.
4. Pin no 3 of NAND gate 1 is given to Pin no 9 of NAND gate 3.
5. Pin no 6 of NAND gate 2 is given to Pin no 13 of NAND gate 4.
6. Output Q’ and Q are given to Pin 10 and 12 of gates 3 and 4 respectively.
7. Observe the output for various Input combinations on multimeter.
Note:- Observation table should be verified with Truth table

CHARACTERISTIC TABLE/TRUTH TABLE:

D FLIP-FLOP
Q D Q(t+1)

0 0 0

0 1 1

1 0 0

1 1 1

ELECTRICAL Engineering Department, Vadodara Institute of Engineering, Kotambi

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 ANALOG & DIGITAL ELECTRONICS (3130907)

OBSERVATION TABLE:
D FLIP-FLOP

Q D Q(t+1)

CONCLUSION:

ELECTRICAL Engineering Department, Vadodara Institute of Engineering, Kotambi

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