Electronic Devices and Circuits

Lecture 3
Electronic Devices and Circuits

Dr Zaki Uddin
DMTS, CEME, NUST
 Topic Covered
FET AC Analysis

FET Amplifier

Examples on FET AC analysis

 Difference between BJT and FET
 Field-effect transistor amplifiers provide an excellent voltage gain with the added feature of a high
input impedance.
 FETs are also considered low-power consumption configurations with good frequency range and
minimal size and weight.
 Both JFET and depletion MOSFET devices can be used to design amplifiers having similar voltage
gains.
 The depletion MOSFET circuit, however, has a much higher input impedance than a similar JFET
configuration.
 While a BJT device controls a large output (collector) current by means of a relatively small input
(base) current, the FET device controls an output (drain) current by means of a small input (gate-
voltage) voltage.
 In general, therefore, the BJT is a current-controlled device and the FET is a voltage-controlled
device. In both cases, however, note that the output current is the controlled variable.
 Because of the high input characteristic of FETs, the ac equivalent model is somewhat simpler than
that employed for BJTs. While the BJT had an amplification factor (b), the FET has a
transconductance factor, gm.
 JFET Small Signal Model
 The ac analysis of a JFET configuration requires that a small-signal ac model for the JFET be
developed.
 A major component of the ac model will reflect the fact that an ac voltage applied to the input
gate-to-source terminals will control the level of current from drain to source.
 The gate-to-source voltage controls the drain-to-source (channel) current of a JFET.
2
 VGS 
ID  I DSS 1    Schokley' s Equation
 VP 
The change in drain current that will result from a change in gate-to-source voltage can be
determined using the trans conductance factor gm, given by

I D  g m VGS
I D
gm 
VGS
Graphical Determination of gm
 Mathematical Definition of gm
 VGS  d  VGS 
The derivative of a function at a point is equal to  2 I DSS 
 1    1  
 VP   dVGS 
 VP 

the slope of the tangent line drawn at that point
 VGS  1 
 2 I DSS     
  
2 

1
V P  0
VP 
gm 
dI D

d  I DSS 1  VGS  
   2 I DSS  VGS 
dVGS Q  pt
dVGS
  VP   gm  
 1  

Vp  V P 

d  V  
2
 VGS 
 I DSS 1  GS   g m  g mo 
 1  

dVGS  VP    VP 
 2 I DSS
 g mo 
Vp

Determine the magnitude of gm for a JFET with IDSS = 8 mA and VP =  4 V at the following dc
bias points: a. VGS = 0.5 V. b. VGS =  1.5 V. c. VGS =  2.5 V

On specification sheets, gm is often provided as gfs or yfs

 Mathematical Definition of gm
Determine the magnitude of gm for a JFET with IDSS = 8 mA and VP =  4 V at the following dc
bias points: a. VGS = 0.5 V. b. VGS =  1.5 V. c. VGS =  2.5 V

On specification sheets, gm is often provided as gfs or yfs

Plot of gm [Link]
 Plot of gm [Link]
2
 V 
I D  I DSS 1  GS  If I D  I DSS
 VP  g m  g mo
ID  V 
 1  GS  I DSS
I DSS  VP  If I D 
2
 V  g m  0.707 g mo
 g m  g mo 1  GS 
 VP  I DSS
ID If I D 
g m  g mo 4
I DSS g m  0.5 g mo
 JFET input and output impedance
 The input impedance of all commercially available JFETs is sufficiently large to assume that
the input terminals approximate an open circuit.
 For a JFET a practical value of 109 W (1000 M W) is typical, whereas a value of 1012 W to 1015
W is typical for MOSFETs and MESFETs, respectively.
 The output impedance of JFETs is similar in magnitude to that of conventional BJTs.
 On JFET specification sheets, the output impedance will typically appear as gos or yos with the
units of mS.
1 1
Z o ( JFET )  rd  
g os yos

 The output impedance is defined on the characteristics of Figure (next slide) as the slope of
the horizontal characteristic curve at the point of operation.
 The more horizontal the curve, the greater is the output impedance.
 If it is perfectly horizontal, the ideal situation is on hand with the output impedance being
infinite (an open circuit)—an often applied approximation.
 JFET input and output impedance
VDS
rd 
ID VGS constant
 JFET AC Equivalent Circuit
The control of Id by Vgs is included as a current source gmVgs connected from drain to source as
shown in Figure. The current source has its arrow pointing from drain to source to establish a
180° phase shift between output and input voltages as will occur in actual operation

G D
+
Vgs gmVgs rd

S  S
 Steps for AC analysis of FET
1. All DC sources are set to Zero

2. Coupling and Bypass capacitors are replaced by short-circuit.

3. Inspect the circuit (replace FET with its small-signal model)

4. Redrawing the network in a more convenient and logical form

5. Solve for voltage gain , i/p and o/p impedances

 Fixed Bias Configuration
+VDD D
G
+ +
zi zo
RD C2
RG gmVgs rd RD vo
C1 vo vi
vi
 
S
RG
 vo   g mV gs rd RD  Av 
vo
  g m rd RD 
VGG vi
+ V gs  vi
If rd  10 RD
Z i  RG vo   g m vi rd RD 
Z o  rd RD Av   g m RD
 Example Fixed Bias
The fixed-bias configuration had an operating point defined by VGSQ = -2 V and IDQ = 5.625 mA,
with IDSS = 10 mA and VP = -8 V. The network is redrawn as shown in Figure with an applied +VDD
signal Vi . The value of yos is provided as 40 mS.
a. Determine gm .
b. Find rd .
c. Determine Zi .
RD 2kW
d. Calculate Zo .
vo
e. Determine the voltage gain Av . vi C1 C2
f. Determine A v ignoring the effects of rd .

D RG
G 1MW
+ +
zi zo 
2
RG gmVgs rd RD vo +
vi

 
 Fixed Bias Configuration: Example
2 I DSS 2(10mA)
a. g mo    2.5mS c. Z i  RG  1MW
Vp 8V
d. Z o  RD rd  1.85kW
 VGSQ  e. Av   g m RD rd   3.48
g m  g mo 1    1.88mS
 V  Av   g m RD  3.76
 p  f.
1 1
b. rd    25kW
yos 40mS
Self Bias Configuration with Bypass capacitor
Self Bias Configuration
Phase Relationship: The negative sign in
the gain equation reveals that a 180°
phase shift will exist between vi and vo
 Self Bias Configuration with Unbypassed Capacitor
If CS is removed, the resistor RS will be part of the ac equivalent circuit as shown in Figure. In this
case, there is no obvious way to reduce the network to lower its level of complexity. In
determining the levels of Zi , Zo , and Av , one must be very careful with notation and defined
polarities and direction. Initially, the resistance rd will be left out of the analysis to form a basis for
comparison.
Due to the open-circuit condition between the
gate and the output network, the input remains
the following:
Z i  RG
 Self Bias Configuration with Unbypassed Capacitor
V
Since Z o  o Setting Vi = 0 V in Figure results in the gate terminal being at ground
I o V 0 potential (0 V). The voltage across RG is then 0 V, and RG has been
i
effectively “shorted out” of the picture.

I o  I D  g mV gs and V gs  I o  I D R s
I o  I D   g m I o  I D R s   g m I o R s  g m I D R s
or
I o 1  g m R s    I D 1  g m R s 
V I R
and I o   I D (the controlled current source g mV gs  0 Since Z o  o  D D
I o V 0 Io
i
for the applied condition)
Since Vo   I D R D
then Vo  ( I o ) R D  I o R D
V
Z o  o  RD
Io
 Self Bias Configuration with Unbypassed Capacitor
If rd is included in the network, the equivalent will appear as shown in Figure
Self Bias Configuration with Unbypassed Capacitor
Applying KVL to the input circuit results in
 Self Bias Configuration
The self-bias configuration has an operating point defined by VGSQ = -2.6 V and IDQ = 2.6 mA, with IDSS = 8 mA and VP = 6 V.
The applied signal is Vi . The value of gos is given as 20 mS.
a. Determine gm .
b. Find rd .
c. Find Zi .
d. Calculate Zo with and without the effects of rd . Compare the results.
e. Calculate Av with and without the effects of rd . Compare the results.
 Homework
Study the following with numerical examples

[Link] Divider Configuration of JFET

[Link] Gate Configuration of JFET
[Link] Follower Configuration of JFET
 D-MOSFET Voltage-Divider Configuration
For the network shown in Figure, VGSQ = 0.35 V and IDQ = 7.6 mA .
a. Determine gm and compare to gm0 .
b. Find rd .
c. Sketch the ac equivalent network.
d. Find Zi .
e. Calculate Zo .
f. Find Av .
 E-MOSFET Drain-Feedback Configuration
Recall from dc calculations that RG could be replaced by a short-circuit equivalent since IG = 0 A and therefore VRG = 0 V.
However, for ac situations it provides an important high impedance between Vo and Vi . Otherwise, the input and output terminals
would be connected directly and Vo = Vi .
 E-MOSFET Drain-Feedback Configuration
I i  g mVgs 
Vo So that Vi 1  g m (rd R D )  I i R F  rd R D 
rd R D
V
and finally Z i  i 
RF  rd RD 
I i 1  g m (rd R D )
As V gs  Vi
Vo
So that I i  g mVi  Typically , R F  rd R D
rd R D
RF
Zi 
1  g m (rd RD )
Vo
I i  g mVi 
rd R D

Therefore Vo  rd R D I i  g mVi  For rd  10 R D

R D I i  g mVi 
RF
V  Vo Vi  rd Zi 
With I i  i  1  g m R D 
RF RF

and I i R F  Vi  rd R D I i  g mVi 
Substituting Vi = 0 V results in Vgs = 0 V and
gmVgs = 0, with a short-circuit path from gate
to ground as shown in Figure RF, rd, and RD
are then in parallel and
Z o  R F rd R D