COMPUTER ARCHITECTURE
LAB ASSIGNMENT-1
NAME- ARJUN SAGAR N V
ROLL NO.: 20BCS020
Implementation of the following in Verilog HDL:
2 INPUT AND:
Truth table:
A(input) B(input) C(output)
0 0 0
0 1 0
1 0 0
1 1 1
Circuit diagram of design:
ARJUN SAGAR N V
20BCS020
Timings:
2 INPUT OR:
Truth table:
A(INPUT) B(INPUT) C(OUTPUT)
0 0 0
0 1 1
1 0 1
1 1 1
ARJUN SAGAR N V
20BCS020
Circuit diagram of design:
Timing:
ARJUN SAGAR N V
20BCS020
2 INPUT XOR:
Truth table:
A(INPUT) B(INPUT) C(OUTPUT)
0 0 0
0 1 1
1 0 1
1 1 0
Circuit diagram of design:
ARJUN SAGAR N V
20BCS020
Timing:
HALF ADDER:
Truth table:
A(INPUT) B(INPUT) Sum(OUTPUT) Carry(output)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
ARJUN SAGAR N V
20BCS020
Circuit diagram of design:
Timing:
ARJUN SAGAR N V
20BCS020
HALF SUBTRACTOR:
Truth table:
A(INPUT) B(INPUT) Difference(OUTPUT) Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Circuit diagram of design:
ARJUN SAGAR N V
20BCS020
Timing:
FULL ADDER:
Truth table:
A(INPUT) B(INPUT) cin(INPUT) Sum(output) Carry(output)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
ARJUN SAGAR N V
20BCS020
Circuit diagram of design:
Timing:
ARJUN SAGAR N V
20BCS020
FULL SUBTRACTOR:
Truth table:
A(INPUT) B(INPUT) Bin(INPUT) Difference Borrow
(output) (output)
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Circuit diagram of design:
ARJUN SAGAR N V
20BCS020
Timing:
* * * * *
ARJUN SAGAR N V
20BCS020