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Logic Circuit Design: Combinational & Sequential

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10 views9 pages

Logic Circuit Design: Combinational & Sequential

Uploaded by

avpoojitha26
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

UNIT 1

Combinational and Sequential Logic Circuit Design


Introduction
• Logic circuits may be combinational or sequential.
• A combinational circuit consists of logic gates whose outputs at any time are determined
from only the present combination of inputs. The operation of combinational circuits
can be specified logically by a set of Boolean functions.
• Sequential circuits contain storage elements in addition to logic gates. The outputs of
sequential circuits are a function of the inputs and the state of the storage elements. The
state of the storage elements is a function of previous inputs.
• The outputs of a sequential circuit depend not only on present values of inputs, but also
on past inputs, and the circuit behaviour must be specified by a time sequence of inputs
and internal states.

Design, Analysis and Synthesis of Combinational Circuits:


Combinational Circuits
• A combinational circuit consists of an interconnection of logic gates.
• Combinational circuits react to the values at their inputs and produce the value of the
output signal, transforming binary information from the given input data to a required
output data.
• A block diagram of a combinational circuit is shown.

• The n inputs come


from an external source; the m outputs are produced by the combinational circuit and
go to an external destination.
• Each input and output variable is an analog electrical signal whose values are
interpreted to be a binary signal that represents logic 1 and logic 0.
• Several extensively used combinational circuits, such as adders, subtractors,
multipliers, comparators, decoders, encoders, and multiplexers, are available in
standard integrated circuit components and used as standard cells in complex very large
scale integrated (VLSI) circuits.

Analysis Procedure
• The analysis is to determine the function of an implemented circuit.
• The task starts with a given logic diagram and culminates with a set of Boolean
functions, a truth table, or, possibly, an explanation of the circuit operation.
• The analysis can be performed manually by finding the Boolean functions or truth table
or by using a computer simulation program.
• The first step in the analysis is to make sure that the given circuit is combinational and
not sequential.
• A combinational circuit has no feedback paths or memory elements.
• A feedback path is a connection from the output of one gate to the input of a second
gate whose output forms part of the input to the first gate.
• Feedback paths in a digital circuit define a sequential circuit.

Design Procedure

• The design is to derive a logic circuit or a set of Boolean functions from the
specification of the design objective.
• The design procedure involves the following steps:
• From the specifications of the circuit, determine the required number of inputs and
outputs and assign a symbol to each.
• Derive the truth table that defines the required relationship between inputs and outputs.
• Obtain the simplified Boolean functions for each output as a function of the input
variables.
• Draw the logic diagram and verify the correctness of the design (manually or by
simulation).
ENCODERS
The inverse function of a decoder.
• 2n (or fewer) input lines and n output lines.
• The output lines generate the binary code corresponding to the input value.

8:3 Encoder RTL Code and Testbench:


module encoder8_3(d, x, y, z);
input [7:0] d;
output reg x, y, z;
always @ (*)
begin
case(d)
8’b00000001: {x, y, z} =3’b000;
8’b00000010: {x, y, z} =3’b001;
8’b00000100: {x, y, z} =3’b010;
8’b00001000: {x, y, z} =3’b011;
8’b00010000: {x, y, z} =3’b100;
8’b00100000: {x, y, z} =3’b101;
8’b01000000: {x, y, z} =3’b110;
8’b10000000: {x, y, z} =3’b111;
endcase
end
endmodule

Testbench
module encoder_tb ();
reg [7:0] d;
wire x, y, z;
encoder8_3(d, x, y, z);
initial
begin
d=8’b00000001;
d=8’b00000010;
d=8’b00000100;
d=8’b00001000;
d=8’b00010000;
d=8’b00100000;
d=8’b01000000;
d=8’b10000000;
end
endmodule

PRIORITY ENCODER
Encoder that includes the priority function.
• Resolve the ambiguity of illegal inputs, only one of the inputs is encoded.
• The input having the highest priority will take precedence.

4:2 Priority Encoder


module encoder4_2(d, y);
input [3:0] d;
output reg [1:0] y;
always @(*)
begin
casex(d)
4’b1000: y=2’b00;
4’bx100: y=2’b01;
4’bxx10: y=2’b10;
4’bxxx1: y=2’b11;
endcase
end
endmodule
DECODERS
A decoder converts binary information from n input lines to a maximum of 2n unique output
lines.
A n-to-m decoder (m ≦2n)
– a binary code of n bits has 2n distinct information
– n input variables; up to 2n output lines
– only one output can be active (high) at any time

3:8 Decoder – RTL Code and Testbench


module decoder3_8(d, x, y, z);
input x,y,z;
output reg [7:0] d;
always @ (*)
begin
case({x,y,z})
3’b000: d=8’b00000001;
3’b001: d=8’b00000010;
3’b010: d=8’b00000100;
3’b011: d=8’b00001000;
3’b100: d=8’b00010000;
3’b101: d=8’b00100000;
3’b110: d=8’b01000000;
3’b111: d=8’b10000000;
endcase
end
endmodule

Testbench

module decoder_tb ();


reg x, y, z;
wire [7:0] d;
decoder3_8 n1(d, x, y, z)
initial
begin
#5 x=0; y=0; z=0;
#5 x=0; y=0; z=1;
#5 x=0; y=1; z=0;
#5 x=0; y=1; z=1;
#5 x=1; y=0; z=0;
#5 x=1; y=0; z=1;
#5 x=1; y=1; z=0;
#5 x=1; y=1; z=1;
end
endmodule

2:4 Decoder
module decoder2_4(y,d);
input [1:0]d;
output reg [3:0]y;
always @(*)
begin
case(d)
2’b00: y=4’b0001:
2’b01: y=4’b0010:
2’b10: y=4’b0100:
2’b11: y=4’b1000:
endcase
end
endmodule

MULTIPLEXERS
• Select from one of many inputs and directs it to a single output, controlled by a set of
selection lines.
• A multiplexer is also called a data selector.
• Normally, there are 2n inputs and n selection lines whose bit combinations determine
which input is selected.
4:1 Mux – RTL Code and Testbench
module mux4_1 (y, s1, s0, d);
input [3:0] d;
input s1, s0;
output reg y;
always @ (s1, s0, d)
begin
case ({s1, s0})
2’b00: y=d [0];
2’b01: y=d [1];
2’b10: y=d [2];
2’b11: y=d [3];
endcase
end
endmodule

Testbench
module mux4_1tb ().
reg s1, s0;
reg [3:0] d;
wire y;
mux 4_1 n1(y, s1, s0, d);
initial
begin
#5 $ monitor (“s1=%b s0=%b d=%b y=%b”, s1, s0, d, y);
d=4’b1010;
s1=1’b0; s0=1’b0;
s1=1’b0; s0=1’b1;
s1=1’b1; s0=1’b0;
s1=1’b0; s0=1’b1;
#5 $finish
end
endmodule

1:4 demux-RTL Code and Testbench


module Demux1_4(Y, S, I);
input [1:0] S;
output [3:0] Y;
assign Y0=I & (~S [1]) & (~S [0]);
assign Y1=I & (S [1]) & (~S [0]);
assign Y2=I & (~S [1]) & (~S [0]);
assign Y3=I & (S [1]) & (S [0]);
end
endmodule

Testbench

module Demuxtb;
reg [1:0] S;
reg I;
wire [3:0] Y;
Demux1_4 n1(Y, S, I);
initial
begin
S=2’b00;
I=1’b1;
#5 S=2’b01;
#5 S=2’b10;
#5 S=2’b11;
$monitor (“S=%b,I=%b,Y=%b”,S,I,Y);
end
endmodule

4-bit Comparator

module comp4bit (alb,agb,aeb,a ,b);


input [3:0] a,b;
output reg alb, agb, aeb;
always @ (*)
begin
if (a==b)
aeb=1;
else if(a>b)
agb=1;
else if(a<b)
alb=1;
end
endmodule

Testbench

module comptb;
reg [3:0] a,b;
wire alb, agb, aeb;
comp4bit n1(alb, agb, aeb, a, b);
initial
begin
a = 4'b1010;
b = 4'b0101;
#20 a=4’b0001;
#40 b=4’b0001;
$monitor (“a=%b, b=%b, alb=%b, aeb=%b, agb=%b”a,b,alb, aeb, agb);
end
endmodule

Common questions

Powered by AI

To determine the output of a combinational circuit, you need to first establish a truth table that defines the relationship between its inputs and outputs. From this truth table, you can derive the Boolean functions that simplify the logic expressions for each output, utilizing techniques such as Karnaugh maps for simplification. Once the Boolean expressions are obtained, you can use them to construct a logic diagram of the circuit .

Multiplexers, functioning as data selectors, route one of several input lines to a single output line based on the combination of selection lines. For example, a 4:1 multiplexer has four inputs and uses two selection lines to determine which input is routed to the output. The device simplifies circuit design by enabling the selection and routing of data from multiple sources to a single point of output, controlled by the logic level of the selection lines .

Using modules and testbenches in digital circuit design offers several benefits including improved modularity, reuse, and ease of testing. Modules allow designers to encapsulate and organize circuit functionality within defined boundaries, promoting code reuse and simplifying complex designs. Testbenches facilitate automated testing, validating module functionality by simulating input conditions and monitoring outputs for expected behavior. This approach reduces errors, accelerates debugging, ensures correctness, and allows for easier integration in larger systems .

The design procedure for a combinational circuit involves several steps: specify the design objective, determine the required number of inputs and outputs, assign symbols to each, derive the truth table defining the input-output relationship, obtain simplified Boolean functions for each output using the input variables, and finally, draw the logic diagram and verify its correctness manually or through simulation .

A priority encoder assigns precedence to its input lines, ensuring that when multiple inputs are simultaneously active, only the highest-priority input is encoded and represented by the output. This is achieved by using a priority logic that always selects the input with the highest priority order when more than one input is active at a time, thus preventing ambiguity in encoding .

A combinational circuit consists of logic gates whose outputs are determined solely by the current combination of inputs, without feedback paths or memory elements. In contrast, a sequential circuit contains storage elements in addition to logic gates, meaning its outputs depend not only on current inputs, but also on past inputs through feedback paths. This dependency is managed by a sequence of inputs and internal states over time .

A multiplexer and a demultiplexer serve opposite functions in digital circuits. A multiplexer selects one of several input signals and directs it to a single output line based on selection inputs, commonly used in data routing to manage multiple input sources. Conversely, a demultiplexer takes a single input and channels it to one of several outputs, dictated by control lines, facilitating data distribution from a single source to multiple destinations. Each serves as a critical component in effectively managing signal flow and control within digital systems .

Feedback paths play a crucial role in differentiating between combinational and sequential circuits. In combinational circuits, there are no feedback paths, meaning outputs are determined solely by current inputs and change instantaneously with input changes. Sequential circuits, however, have feedback paths where the output is also influenced by previous inputs via their dependence on the stored state of the circuit .

A 3:8 decoder maps three binary input lines to up to eight unique output lines, activating only one output at a time based on the binary input combination. This expansion enables a simple binary code to control multiple independent outputs, often used in address decoding in memory systems or in enabling specific hardware functions within VLSI designs. By converting binary information into a specific output line, decoders facilitate efficient data routing and control within digital circuits .

A 4-bit comparator module evaluates the relative magnitudes of two binary numbers by implementing three outputs: "a less than b" (alb), "a greater than b" (agb), and "a equal to b" (aeb). The comparator compares corresponding bits of inputs a and b from the most significant bit to the least significant bit. If at any position the bit in a is greater than in b, agb is asserted; if less, alb is asserted. If all bits are identical, aeb is asserted. This comparison allows digital systems to determine numerical relationships in logical and mathematical operations .

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