Microprocessors

and Microcontrollers
Ali Parsayan
[Link]@[Link]
1
 Chapter 5
ARM Family
STM32 Microcontrollers

2
 Outline
• 1.1 ARM Family Microprocessors and Microcontrollers
• 1.2 STM32 Family MPUs and MCUs
• 1.3 STM32 MCUs’ Structure
• 1.4 STM32 Cortex-M4 MCUs’ Structure
• 1.4 STM32 Cortex-M4 MCUs’ CPU Architecture
• 1.5 STM32 MCUs’ Assembly Language Programming

3
 General Purpose Microprocessors
vs. Microcontrollers
• General Purpose Microprocessors:

General I/O Serial

Purpose RAM ROM Timer
Port Port
Micropro
cessor
(CPU) Buses

• Microcontrollers (MCUs):

Microcontroller

I/O Serial
RAM ROM Timer
Port Port
CPU

Buses
4
 ARM Family
Microprocessors and Microcontrollers
• ARM (Advanced RISC Machine) does not produce chips but
designs & sells the license of its of architecture to others.
• More than 200 companies have bought the Arm architecture and
provide their Arm chips.

5
 ARM Family
MCUs of Different Companies
• The same CPU
o and Assembly Language.
• But different Peripherals.

6
 ARM Family
Different MPUs and MCUs Architectures

7
 ARM Family
Different MPUs and MCUs Architectures
• ARM Cortex processors:
o Cortex-A Series:
➢ Designed for high-performance applications, such as smartphones, tablets, and
other consumer electronics.
➢ Examples: Cortex-A5, Cortex-A7, Cortex-A9, Cortex-A15, Cortex-A53, Cortex-
A57, Cortex-A72, Cortex-A76, and Cortex-A78.
o Cortex-R Series:
➢ Designed for real-time applications that require high reliability and safety (e.g.,
automotive, industrial control).
➢ Examples: Cortex-R4, Cortex-R5, Cortex-R7, and Cortex-R8.
o Cortex-M Series:
➢ Designed for microcontrollers and low-power applications (e.g., IoT devices).
➢ Examples: Cortex-M0, Cortex-M3, Cortex-M4, Cortex-M7, and Cortex-M33.
8
 ARM Family
Different MPUs and MCUs Architectures
• ARM Cortex processors:

9
 ARM Family
Different MPUs and MCUs Architectures
• ARM Cortex-M processors:
o Cortex-M stands for Microcontroller cores.
o The Cortex-M is the famous microcontroller series which is ruling the
world with its flexibility in mending with the designer’s applications.
o The first Cortex-M was released in 2004 namely Cortex-M.

10
 STM32 Family MPUs and MCUs
• ST is a multinational company
o STM8: 8-bit MCUs
o STM32: 32-bit MCUs based on ARM
o Low prices
o Various chips

11
 STM32 Family MPUs and MCUs
• Naming rule of ARM processors:
o x: series
o y: memory management / protection unit
o z: cache
o T: Thumb decoder
o D: JTAG debugger
o M: fast multiplier
o I: support hardware debug
o E: enhance instructions (based on TDMI)
o J: Jazelle
➢ an extension that allows some ARM processors to execute Java bytecode in hardware
o F: vector floating point unit
o S: synthesiable, suitable for EDA tools
 STM32 Family MPUs and MCUs
• ST32 family naming conventions
STM32F407VGT
type series package
family Sub Pin Flash
series count size
Package
Family Flash Series
Type
Pin count
Sub
size series
Names L:
ofGthe new H:
0:Arm
Low BGA
Cortex-M0
Power
Chips (Ballhigher
with Grid Array)
4 6 8 F K
B T:LQFP T S
C (Low-profile
D EC R
FFlat GV HZ I
F:ST
products of 1,2:
Mainstream Cortex-M3
begin with(Foundation)
sub-series Quad Pack)
Group Number
Low density of 20 density
Medium 28 32U:QFNHigh36
density 44 Flat
(Quad 48No-leads)
64 100 144
3,4: performance
H: High
STM32. Cortex-M4
numbers have
pins W: Y:WLCSP
7: Cortex-M7
Wirelessricher512K 768K 1M 1.5M 2M
Flash 16K 32K 64K 128K 256K 384K
configurations

13

STM32F429AIH6 STM32F103C8T6 STM32F031K6U6

14
 STM32 Family MPUs and MCUs
• ARM Cortex-M Architecture:
o STMicroelectronics commonly uses ARM Cortex-M cores in their
microcontrollers.
o The Cortex-M cores are known for their energy efficiency and are widely used
in embedded systems.
• Product Series:
o STM32 is one of the popular series of microcontrollers from
STMicroelectronics.
o Within the STM32 series, there are various families (e.g., STM32F0, STM32F1,
STM32F4, etc.) catering to different application requirements.
• Peripherals and Features:
o STM microcontrollers typically come with a rich set of peripherals, including
GPIO (General Purpose Input/Output), UART (Universal Asynchronous
Receiver/Transmitter), SPI (Serial Peripheral Interface), I2C (Inter-Integrated
Circuit), timers, ADC (Analog-to-Digital Converter), and more.
o These peripherals make them versatile
15 for a wide range of applications.
 STM32 Family MPUs and MCUs
• Development Tools:
o STMicroelectronics provides a comprehensive set of development tools for STM
microcontrollers, including integrated development environments (IDEs) such
as STM32CubeIDE, as well as hardware tools like ST-LINK and Nucleo
development boards.
• Low-Power Capabilities:
o Many STM microcontrollers are designed with low-power features, making
them suitable for battery-operated and power-sensitive applications.
• Security Features:
o Some STM32 microcontrollers come with security features, such as hardware
encryption, secure boot, and tamper detection, enhancing the security of
embedded systems.
• RTOS Support:
o STM microcontrollers can be used with real-time operating systems (RTOS)
like FreeRTOS, providing a robust foundation for building complex and
multitasking applications. 16
STM32 Cortex-M1 MCUs

17
STM32 Cortex-M4 MCUs

18
 STM32 Cortex-M4 MCUs

• SPECIFICATION
o Core and Architecture:
➢ ARM Cortex-M4 processor.
➢ 32-bit RISC architecture.
o Clock and Speed:
➢ Operating Frequency: Up to 84 MHz.
➢ Built-in PLL (Phase-Locked Loop) for clock scaling.
o Memory:
➢ Flash Memory: Up to 1 MB.
➢ SRAM: Up to 64 KB.
➢ EEPROM: None (external EEPROM can be used)
19
 STM32 Cortex-M4 MCUs
• SPECIFICATION
o Peripherals:
➢ GPIO (General-Purpose I/O) pins.
➢ USART, UART, SPI, I2C communication interfaces.
➢ USB (Universal Serial Bus) interface.
➢ CAN (Controller Area Network) interface.
➢ ADC (Analog-to-Digital Converter).
➢ DAC (Digital-to-Analog Converter).
➢ PWM (Pulse Width Modulation) outputs.
➢ Timers and Counters.
o Connectivity:
➢ USB 2.0 Full Speed.
➢ Multiple serial communication interfaces (USART, UART, SPI, I2C).
20
➢ CAN (Controller Area Network) interface.
 STM32 Cortex-M4 MCUs
• SPECIFICATION
o Operating Voltage:
➢ 2.0 V to 3.6 V.
o Power Consumption:
➢ Low power modes for energy-efficient operation.
o Debugging and Development:
➢ JTAG (Joint Test Action Group) and SWD (Serial Wire Debug) debugging support.
➢ In-system programming and debugging.
o Package:
➢ Available in different package options (e.g., LQFP, QFP, BGA).
o Temperature Range:
➢ Commercial and Industrial temperature ranges available.
o Security:
➢ Hardware cryptographic acceleration.
➢ Secure boot and Flash memory protection.
o Operating Temperature:
➢ Typically, -40°C to +85°C or wider, 21
depending on the specific model.
 STM32 Cortex-M4 MCUs Structure

RAM EEPROM Timers

PROGRAM
Flash ROM

Program Data
Bus Bus
CPU

Interrupt Other
OSC Ports
Unit Peripherals

23 I/O
PINS
 Von Neumann vs. Harvard architecture
• Von Neumann architecture:
Code Data
Memory Memory

Data bus
CPU Address bus
Control bus

• Harvard architecture:

Data bus Data bus

Code Data
Memory Address bus CPU Address bus Memory
Control bus Control bus

24
 Harvard Architecture
• Separate buses for opcodes and operands:

Control bus Control bus

Code Data
Memory Data bus CPU Data bus Memory
Address bus Address bus

o Advantage:
➢ opcodes and operands can go in and out of the CPU together.
o Disadvantage:
➢ Using Harvard architecture in motherboards leads to more cost in
general purpose computers.
25
STM32 Cortex-M4 MCUs Structure
(Harvard Architecture)

26
STM32 Cortex-M4 MCUs Structure
(Memory Map)

27
 STM32 Cortex-M4 MCUs Structure
(Memory Map)
• Power up in Cortex-M:

28
29
STM32 Cortex-M4 MCUs Structure
STM32 Cortex-M4 MCUs
CPU Architecture

R0

ALU R1

R2

CPU

…
CPSR: I T H S V N Z C
R13 (SP)
PC
R14 (LR)
Instruction decoder R15 (PC)
Instruction Register
Registers
STM32 Cortex-M4 MCUs
CPU Architecture
STM32 Cortex-M4 MCUs CPU Architecture
 STM32 Cortex-M4 MCUs CPU Architecture
(Operating Modes)
• The ARM processors has seven modes of operations as:
o User mode (usr)
➢ Normal program execution mode
o Fast Interrupt mode (fiq)
➢ Supports a high-speed data transfer or channel process.
o Interrupt mode (irq)
➢ Used for general-purpose interrupt handling.
o Supervisor mode (svc)
➢ Protected mode for the operating system.
o Abort mode (abt)
➢ implements virtual memory and/or memory protection
o System mode (sys)
➢ A privileged user mode for the operating system. (runs OS tasks)
o Undefined mode (und)
➢ supports a software emulation of hardware coprocessors
• Except user mode, all are known as privileged mode.
36
STM32 Cortex-M4 MCUs CPU Architecture
(Registers)
• 37 registers:
o 31 general porpose 32 bit registers, including PC:
➢R0 to R15 are directly accessible
➢R0 to R14 are general purpose
➢R13: Stack point (sp) (in common),
✓ Individual stack for each processor mode
➢R14: Linked register (lr)
➢R15 holds the Program Counter (PC)
o 6 status registers:
➢CPSR - Current Program Status Register contains
✓ condition code flags and the current mode bits
➢5 SPSRs (Saved Program Status Registers) which
✓ are loaded with CPSR when an exceptions occurs
37
STM32 Cortex-M4 MCUs CPU Architecture
(Current Program Status Register)
D31 D30 D29 D28 ………. D7 D6 D5 D4 D3 D2 D1 D0
N Z C V Reserved I F T M4 M3 M2 M1 M0

oVerflow
Negative
carry
Thumb
Zero
Interrupt Mode bits
Fast interrupt
 STM32 Cortex-M4 MCUs
CPU Architecture
• How to speed up the CPU:
o Increase the clock frequency
➢More frequency → More power consumption &
more heat
➢Limitations
o Change the architecture
➢Pipelining
➢Harvard
➢RISC
39
STM32 Cortex-M4 MCUs CPU Architecture
(Pipeline Architecture)
• Non-pipeline
o Just fetches, decodes, or executes in a given time

• Pipeline

40
STM32 Cortex-M4 MCUs CPU Architecture
(RISC Architecture)
• Changing the architecture RISC vs. CISC:
o CISC (Complex Instruction Set Computer)
➢Put as many instruction as you can into the CPU.
o RISC (Reduced Instruction Set Computer)
➢Reduce the number of instructions, and use your
facilities in a more proper way.

41
STM32 Cortex-M4 MCUs CPU Architecture
(RISC Architecture)
• RISC architecture (Feature 1):
o RISC processors have a fixed instruction size.
o It makes the task of instruction decoder easier.
➢In ARM the instructions are 4 bytes.
➢In Thumb2 the instructions are either 2 or 4 bytes.
o In CISC processors instructions have different
lengths
o E.g. in 8051
➢CLR C ; a 1-byte instruction
➢ADD A, #20H ; a 2-byte instruction
➢LJMP HERE ; a 3-byte instruction
42
STM32 Cortex-M4 MCUs CPU Architecture
(RISC Architecture)
• RISC architecture (Feature 2):
oreduce the number of instructions:
➢Pros:
✓Reduces the number of used transistors
➢Cons:
✓Can make the assembly programming more
difficult
✓Can lead to using more memory
43
STM32 Cortex-M4 MCUs CPU Architecture
(RISC Architecture)
• RISC architecture (Feature 3):
olimit the addressing mode:
➢Advantage
✓hardwiring
➢Disadvantage
✓Can make the assembly programming more
difficult

44
STM32 Cortex-M4 MCUs CPU Architecture
(RISC Architecture)
• RISC architecture (Feature 4):
oLoad/Store
RAM USART Timers

LDR R8,= 0x20 PROGRAM

Flash ROM ALU
LDR R0,[R8] PC: Data
LDR R8,= 0x220 CPU Bus

LDR R1,[R8] Program Instruction dec.

Bus
ADD R0, R0,R1
LDR R8,= 0x230 Interrupt Other
OSC Ports
STR R0,[R8] Unit Peripherals

I/O
45 PINS
STM32 Cortex-M4 MCUs CPU Architecture
(RISC Architecture)
• RISC architecture (Feature 5):
oMore than 95% of instructions are executed
in 1 machine cycle
• RISC architecture (Feature 6):
oRISC processors have at least 32 registers.
oDecreases the need for stack and memory
usages.
➢In ARM there are 16 general purpose registers
(R0 to R15)
46
 STM32 MCUs’
Assembly Language Programming

Assembly
assembler

Machine Language
47
• The assembler listing file contains Editor Program
an abundance of information about
the assembly process and is
composed of a number of sections as
myfile.a
Page Header, Command Line,
Source Listing, Symbol Table, Cross
Reference, Register Banks, Assembler Program
Warnings and Errors.
• The map file contains all the static
symbols (functions, globals, etc.) in
your code and their relative
addresses.

[[Link]] [otherFiles.o] myfile.o [Link]

Linker

Downloaded to the
[Link] [Link]
48 Program Memory
 STM32 MCUs’
Assembly Language Programming
• MOV (MOVE) instruction:
o MOV Rd, #k
➢;Rd = k and k is an 8-bit value
o Example:
➢MOV R5, #53 ;R5 = 53
➢MOV R9, #0x27 ;R9 = 0x27
➢MOV R3, #2_11101100
o MOV Rd, Rs
➢;Rd = Rs
o Example:
➢MOV R5, R2 ;R5 = R2
➢MOV R9, R7 ;R9 = 49
R7
 STM32 MCUs’
Assembly Language Programming
• LDR instruction (loading 32-bit values):
o LDR Rd, = k
➢;Rd = k and k is an 32-bit value
o Example:
➢LDR R5, = 5543 ;R5 = 5543
➢LDR R9, = 0x123456 ;R9 = 0x123456
o LDR R4, = 2_10110110011011001

50
 STM32 MCUs’
Assembly Language Programming
• Arithmetic calculations
o Opcode destination, source1, source2
o Opcodes: ADD, SUB, AND, etc.
o Examples:
➢ADD R5, R2, R1 ;R5 = R2 + R1
➢SUB R5, R9, #23 ;R5 = R9 - 23

51
Instruction Description

ADD Rd, Rn,Op2 * ADD Rn to Op2 and place the result in Rd

ADC Rd, Rn,Op2 ADD Rn to Op2 with Carry and place the result in Rd

AND Rd, Rn,Op2 AND Rn with Op2 and place the result in Rd

BIC Rd, Rn,Op2 AND Rn with NOT of Op2 and place the result in Rd

CMP Rn,Op2 Compare Rn with Op2 and set the status bits of CPSR**

CMN Rn,Op2 Compare Rn with negative of Op2 and set the status bits

EOR Rd, Rn,Op2 Exclusive OR Rn with Op2 and place the result in Rd

MVN Rd,Op2 Store the negative of Op2 in Rd

MOV Rd,Op2 Move (Copy) Op2 to Rd

ORR Rd, Rn,Op2 OR Rn with Op2 and place the result in Rd

RSB Rd, Rn,Op2 Subtract Rn from Op2 and place the result in Rd

RSC Rd, Rn,Op2 Subtract Rn from Op2 with carry and place the result in Rd

SBC Rd, Rn,Op2 Subtract Op2 from Rn with carry and place the result in Rd

SUB Rd, Rn,Op2 Subtract Op2 from Rn and place the result in Rd

TEQ Rn,Op2 Exclusive-OR Rn with Op2 and set the status bits of CPSR

TST Rn,Op2 AND Rn with Op2 and set the status bits of CPSR

* Op2 can be an immediate 8-bit value #K which can be 0–255 in decimal, (00–FF in hex). Op2 can also be a register Rm. Rd, Rn
and Rm are any of the general purpose registers 52
** CPSR is discussed later in this chapter
 STM32 MCUs’
Assembly Language Programming
• Write a program that calculates 19 + 95:
MOV R6, #19 ;R6 = 19
MOV R2, #95 ;R2 = 95
ADD R6, R6, R2 ;R6 = R6 + R2

• Write a program that calculates 19 + 95 – 5:

MOV R1, #19 ;R6 = 19 MOV R1, #19 ;R6 = 19
MOV R2, #95 ;R2 = 95 MOV R2, #95 ;R2 = 95
MOV R3, #5 ;R21 = 5 ADD R6, R1, R2 ;R6 = R1 + R2
ADD R6, R1, R2 ;R6 = R1 + R2 MOV R2, #5 ;R21 = 5
SUB R6, R6, R3 ;R6 = R6 - R3 SUB R6, R6, R2 ;R6 = R6 - R2
53
 Assembly Language Programming
(Status Register)
D31 D30 D29 D28 ………. D7 D6 D5 D4 D3 D2 D1 D0
N Z C V Reserved I F T M4 M3 M2 M1 M0

Example:Show
Example: Showthe thestatus
statusofofthe
theZZflag
flagafter
afterthe
thesubtraction
subtractionofof0x73
0x23
Example:
Example: Show
Show the
the status of the C and
status instructions:
ofinstructions:
the Z
C flag Z flags
and after after
theafter
Z flags the addition
subtraction of
of 0x9C
the addition of
from0x52
from 0xA5ininthe
the following
following
0x0000009C
from
0x38 0x9C in and
and 0x2F the 0xFFFFFF64
in following in the following instructions:
instructions:
the following instructions:
LDR
LDR R0,=0xA5
R0,=0x52
LDR
MOV LDR
R6, #0x38 R0,=0x9C
R0,=0x9C;R6 = 0x38
LDR
LDR R1,=0x23
R1,=0x73
LDR
MOV LDR
R7, #0x2F R1,=0xFFFFFF64
R1,=0x9C;R17 = 0x2F
SUBS
SUBS R0,R0,R1
R0,R0,R1 ;subtract R1 R1 from
from R0
ADDSR6,R7
ADDS SUBS
R6, R0,R0,R1;add R7 ;subtract
R0,R0,R1 ;add
to R6R1 toR21
;subtract R0 fromR0 R20
Solution:
Solution:
Solution: 52
Solution: 0xA5 0101 101000100101
-- 9C
7338 00000000
1001 1100 00000000 00000000 0011 1000
0x23 0111
0000009C 0011
00000000
0010 0011 00000000 00000000 10011100
+ - +DF
2F
9C
0x82 1101
FFFFFF64 00000000
1001
1000 1100
1111
11111111 00000000
0010 11111111 R0 00000000
11111111
R0= =0xDF0x82
0010 1111
01100100
Z = 10 because 67the R20
00
00000000 00000000
10000
00000000
has a value 00000000
0000other thanR0
00000000 00000000
zero=00000000 01100111
$00 the subtraction.
after 00000000
CZ====01
R6
R0
Z because
becauseR1
=000000000
0x67
because theis
the bigger
R20
R20 ishasthan
zero R0 the
after
a value and there
thanis0 aafter
subtraction.
other borrow from D32 bit.
the subtraction.
CC==11because
becausethere
R21 isisnot
R1 is a carry
not beyond
bigger theand
than R0
R20 D7there
andbit.
thereisisno
noborrow
borrowfrom
fromD32
D32bit.
bit.
C = 0 because there is nobigger than
carry beyond the D31 bit.
Z = 1 because R0 (the result) has a value 0 in it after the addition.
Z = 0 because the R6 (the result) has a value other than 0 after the addition.
54
Assembly Language Programming
(Memory Map in STM32F103)

Example: Add contents of location 0x90 to contents of location 0x94

Afterand
running the following
store instruction:
the result STR (Store register)
in location 0x20000300.

SRAM
STR R5, [R2]
Solution:
locations 0x20000000 through 0x20000003 will be loaded
with 0x78, 0x56, 0x34, and 0x12, respectively.
STR Rx,[Rd] ;[Rd]=Rx
LDR (Load register)
Example: Write a program that copies the contents of location 0x80
LDR R6,=0x90 ;R6 = 0x90
intoLDR
location 0x88. 0x12 0x2000 0003
R1,[R6] Example:
LDR Rd,
;R1 = [0x90] [Rx] ;Rd = [Rx]
0x34 0x2000 0002
Solution:
LDR R6,=0x94 ;R6 = 0x94 0x56
;[0x20000000]=0x12345678
0x2000 0001
LDRR2,[R6]
LDR R2,=0x80 Example:
;R2 == [0x94]
;R1 0x80 0x78 0x2000 0000
LDR R5,=0x12345678
LDR R2,R2,R1
ADD R1,[R2] ;R1 == R2
;R2 [0x80]
+ R1
LDRR4,=0x20000000
LDR R6,=0x20000300
R2,=0x88 ;R2 LDR
;R6= =0x88
R2, =0x20000000
R5: 0x12
LDR 0x34 0x56 0x78
0x20000300
LDR R1, [R4]
STR R2,[R6]
STR R1,[R2] ;[0x88] =STR
R1 = R5,[R2]
;[0x20000300] R2 ; [R2] = R5
 Assembly Language Programming
(LDRB, LDRH, STRB, STRH)
Data Size Bits Load instruction used Store instruction used
Byte 8 LDRB STRB
Half-word 16 LDRH STRH
Word 32 LDR STR

LDR Rd,[Rs] STR Rs,[Rd]

LDRB Rd,[Rs] STRB Rs,[Rd]
LDRH Rd,[Rs] STRH Rs,[Rd]

Assumethat
Assume thatR5=0x40000200,
R5=0x40000200,and andR1locations 0x40000200
= 0x41526374.

SRAM
through
After 0x40000203
running contain
the following 0x78, 0x56, 0x34 ,and 0x12,
instruction:
respectively.
STRB R1, [R5]
After running
locations the following
0x40000200 instruction:
will be loaded with 0x74.
LDRH R7, [R5]
R7 will be loaded with 0x00005678 -
0x12 0x4000 0203
-
0x34 0x4000 0202
-
0x56 0x4000 0201
0x00 0x00 0x78
0x74 0x4000 0200

R7
R1 0x00
x 0x00
x 0x56
x 0x78
0x74
Memory Map in STM32F103
I/O Register Address
GPIOA_LCKR 0x40010818
GPIOA_BRR 0x40010814
GPIOA_BSRR 0x40010810
GPIOA_ODR 0x4001080C
GPIOA_IDR 0x40010808
GPIOA_CRH 0x40010804
GPIOA_CRL 0x40010800
Example: Read the contents of GPIOA_IDR.
Example: Write 0x53F6 into GPIOA_ODR.
Solution:
Solution: LDR R1,=0x40010808 ;R1= 0x40010808
LDR R2,=0x53F6 LDR ;R6
R2,[R1]
= 0x53F6 ;R2 = [0x4001080C]
LDR R1,=0x4001080C ;R1= 0x4001080C
STR R2,[R1] ;[0x4001080C] = 0x53F6

57
 Assembly Language Programming
(Some ARM addressing modes)
• Immediate
o MOV R1, #0x25 F04F0125

o ADD R6, R6, #0x40

• Register addressing mode
o MOV R2, R4 EB020301
o ADD R3, R2, R1
• Register indirect (indexed)
o STR R5, [R6]
o LDR R10, [R3]
 Assembly Language Programming
(Assembler Directives)
• Assembler directives vs. Instructions:
o Instructions (e.g. ADD, MOV) tell the CPU what to
do
o Assembler directives tell the assembler what to do
➢AREA
➢IMPORT and EXPORT
➢END
➢DCD, DCW, DCB
➢EQU
➢INCLUDE
 Assembly Language Programming
(Area)
• AREA sectionName, attribute1, attribute2, …
• Code:
AREA MY_PROG, CODE, READONLY 8 bits
4G
__main
– AREA myCode, CODE, READONLY Cortex-M3 internal
peripherals
0xFFFF FFFF
0xE000 0000

MOV R4, #6
• Data:
ADD R1, R1, R2 3G 0xC000 0000

– AREA
…. myData1, DATA, READWRITE FSMC
– AREA myConst, DATA, READONLY 2G
myFunc 0x8000 0000

ADD R2, R3, R4 0x6000 0000

0x5FFF FFFF
… READWRITE 1G
Peripherals
0x4000 0000

…
0x3FFF FFFF
SRAM 0x2000 0000
READONLY
… 0
Flash
0x1FFF FFFF
0x0000 0000
Assembly Language Programming
(IMPORT and EXPORT)
File1.s
; from the main program:
IMPORT MY_FUNC
...
BL MY_FUNC ;call MY_FUNC function
...

File2.s
AREA OUR_EXAMPLE,CODE,READONLY
EXPORT MY_FUNC
IMPORT DATA1
MY_FUNC
LDR R1,=DATA1
...

61
 Assembly Language Programming
(An Example)
EXPORT __main
AREA PROG_2_1, CODE, READONLY
__main
MOV R1, #0x25 ; R1 = 0x25
MOV R2, #0x34 ; R2 = 0x34
ADD R3, R2, R1 ; R3 = R2 + R1
HERE B HERE ; stay here forever
END ;end of source file

62
 Assembly Language Programming
(Defining Const. Values using DCD, DCW, and DCB)
• DCB allocates bytes of memory & initializes them.
o Examples:
➢MYVALUE DCB 5
➢FIBO DCB 1,1,2,3,5,8
➢MY_MSG DCB “Hello World!”
• DCW allocates a half-word
o Example:
➢MYVALUE DCW 25425

• DCD allocates a word of memory

o Example:
➢MYDATA DCD 0x200000, 0x30F5, 5000000
63
 Assembly Language Programming
(Storing Fixed Data in Program Memory)
EXPORT __main
AREA PROG2_2, CODE, READONLY
__main LDR R2, =OUR_FIXED_DATA ; point to OUR_FIXED_DATA
LDRB R0, [R2] ; load R0 with the contents of memory pointed to by R2
ADD R1, R1, R0 ; add R0 to R1
HERE B HERE ; stay here forever
AREA LOOKUP_EXAMPLE, DATA, READONLY
OUR_FIXED_DATA
DCB 0x55, 0x33, 1, 2, 3, 4, 5, 6
DCD 0x23222120, 0x30
DCW 0x4540, 0x50
END

64
 Assembly Language Programming
(Allocating memory using SPACE)
• SPACE allocates memory without initializing.
o Example 1: Allocating 4 bytes of memory:
➢MY_LONG SPACE 4
o Example 2: Allocating 2 bytes:
➢ALFA SPACE 2
o Example 3: Allocating an array of 20 bytes:
➢MY_ARRAY SPACE 20

65
 Assembly Language Programming
(Defining 3 variables A, B, and C)
EXPORT __main
AREA OUR_DATA, DATA, READWRITE
AREA OUR_PROG, CODE, READONLY
; Allocates the followings in SRAM
__main ;A=5
A SPACE 4
LDR R0, =A ; R0 = Addr. of A
B SPACE 4
MOV R1, #5 ; R1 = 5
C SPACE 4
STR R1, [R0] ; init. A with 5
END
;B=4
LDR R0, =B ; R0 = Addr. of B
MOV R1, #4 ; R1 = 4
STR R1, [R0] ; init. B with 4 int main()
; R1 = A {
LDR R0, =A ; R0 = Addr. of A int a = 5;
LDR R1, [R0] ; R1 = value of A int b = 4;
; R2 = B int c = a + b;
LDR R0, =B ; R0 = Addr. of A
LDR R2, [R0] ; R2 = value of A while(1)
; C = R1 + R2 (C = A + B) {
ADD R3, R1, R2 ; R3 = A + B }
LDR R0, =C ; R0 = Addr. of C }
STR R3, [R0] ; C = R3
loop B loop
 Assembly Language Programming
(ALIGN)
• ALIGN is used to align data on 32-bit or 16-bit
boundary.
a)
DTA DCB 0x55
DCB 0x22
END
b)
DTA DCB 0x55
ALIGN 2
DCB 0x22
END
c)
DTA DCB 0x55
ALIGN 4
DCB 0x22
 Assembly Language Programming
(Assembler Directives)
• name EQU value
o Example 1:
COUNT EQU 0x25
MOV R1, #COUNT ;R1 = 0x25
MOV R2, #COUNT + 3 ;R2 = 0x28
o Example 2:
GPIOA_ODR EQU 0x4001080C

• name RN register
o Example 1:
RESULT RN R2
MOV RESULT,#23

o Example 2:
ProgCounter RN R15 68
 Assembly Language Programming
(Assembler Directives: INCLUDE)
• INCLUDE “[Link]”
[Link]
GPIOA_CRL EQU 0x40010800
GPIOA_CRH EQU 0x40010804
GPIOA_IDR EQU 0x40010808
GPIOA_ODR EQU 0x4001080C
....

Program.s
include “[Link]”

69
 Assembly Language Programming
(Startup and main files)
Startup_stm32f10x.s

AREA RESET, DATA, READONLY

EXPORT __Vectors
__Vectors DCD __initial_sp ; loc. 0 to 3 (Stack init)
DCD Reset_Handler ; loc. 4 to 7
...
main.s
Reset_Handler PROC
IMPORT __main AREA OUR_EXAMPLE,CODE,READONLY
... EXPORT __main
__main
LDR R0, =__main ...
BX R0

;reserving 0x400 bytes for stack

AREA STACK, NOINIT, READWRITE, ALIGN=3

Stack_Mem SPACE 0x400

__initial_sp
70
 Assembly Language Programming
(Flash memory and PC register)
[Link]
Line Offset Machine Instruction _
1 00000000 ; The program adds some data
2 00000000 EXPORT __main
3 00000000 AREA PROG_2_4, CODE, READONLY
4 00000000 __main
5 00000000 F04F 0125 MOV R1, #0x25 ; R1 = 0x25
6 00000004 F04F 0234 MOV R2, #0x34 ; R2 = 0x34
7 00000008 EB02 0301 ADD R3, R2, R1 ; R3 = R2 + R1
8 0000000C E7FE HERE B HERE ; stay here forever
9 0000000E END
Assembly Language Programming
(Flash memory and PC register)
0x08000200 F04F0125
0x08000204 F04F0234
F04F0234
0F02
0x08000208 EB020301
EB020301
0x0800020C E7FE
0x0800020E

RAM Timers

PROGRAM
Flash ROM ALU

PC: 0x08000200
0x0800020C
0x08000208
0x08000204
0x0800020E Data
32bit

32bit
CPU Bus
Code Instruction dec.
Bus

Other
Ports
Peripherals

I/O
PINS
Assembly Language Programming
(Pipeline (Cont.))
SUB R3,R3,R4
LDR R2, [R4] ; R2 = [R4] ADD R0, R0,R1
ADD R0,R0,R1 ; R20 = R20 + R21 LDR R2, [R4]
SUB R3,R3,R4

Fetch

Decode

Execute

73
 Assembly Language Programming
(Addressing Modes)
• Topics:
o Alignment
o Little endian vs. Big endian
o Advanced Indexed Addressing Modes
o LDR pseudo-instruction & PC relative
addressing
o Bit-addressable memory

74
 Assembly Language Programming
(Addressing Modes)
• Memory Map:
 Assembly Language Programming
(Addressing Modes)
• Alignment and misalignment :

76
 Assembly Language Programming
(Addressing Modes)
• 16-bit data and memory alignment:

77
 Assembly Language Programming
(Addressing Modes)
• Little endian vs. Big endian:
o LDR R2, =0x7698E39F ; R2=0x7698E39F
o LDR R1, =0x80000000
o STR R2, [R1]
• Little endian

• Big endian
 Assembly Language Programming
(Addressing Modes)
• Advanced Indexed Addressing Modes:
o Pre-indexed addressing
➢with fixed offset
➢with offset register
➢With scaled offset register
o Pre-indexed with write-back
➢With fixed offset
o Post-indexed addressing
➢With fixed offset
79
 Assembly Language Programming
(Addressing Modes)
• Pre-indexed Addressing :
o STR Rd, [Rm, #k]
o LDR Rd, [Rm, #k]

o LDR R5, [R2, #4] ; R5 = contents of location R2+4

80
 Assembly Language Programming
(Addressing Modes)
• Pre-indexed Address mode with Offset register:
o LDR Rd, [Rm, Rn] LDR Rd, [Rm, Rn, shift]
o STR Rs, [Rm, Rn] STR Rs, [Rm, Rn, shift]

o LDR R5, [R2, R1] ; R5 = contents of loc. R2+R1

o LDR R6, [R2, R1, LSL #2] ; R6= [R2+(R1<<2)]
81
 Assembly Language Programming
(Addressing Modes)
• Look-up table:
o Assuming R2 has the x value range of 0–6, the
program calculates 10 to the power of R2 and stores
the result in R3.
➢ EXPORT __main
➢ AREA LOOKUP_EXAMP_6_16, READONLY, CODE
➢__main
➢ LDR R1, =LOOKUP ; point to LOOKUP
➢ LDR R3, [R1, R2, LSL #2] ; R3 = entry of lookup table
index by R2
➢ HERE B HERE ; stay here forever
➢ LOOKUP DCD 1, 10, 100, 1000, 10000, 100000, 1000000
➢ END 82
 Assembly Language Programming
(Addressing Modes)
• Pre-indexed Addressing mode with write-back
and fixed offset:
o LDR Rd, [Rm, k]!
o STR Rd, [Rm, k]!

83
 Assembly Language Programming
(Addressing Modes)
• Post-indexed Addressing mode
o LDR Rd, [Rm], #k
o STR Rd, [Rm], #k

84
 Assembly Language Programming
(Addressing Modes)
• PC Relative addressing:
o LDR Rd, [PC, #k]

85
 Assembly Language Programming
(Addressing Modes)
• LDR Pseudo-instruction:
o EXPORT __main
o AREA EXAMPLE, READONLY, CODE
o __main
o LDR R0, =0x12345678
o LDR R1, =0x86427531
o ADD R2, R0, R1
o H1 B H1
o END

86
 Assembly Language Programming
(Addressing Modes)
• ADR Pseudo-instruction:
o ADR Rn, Label
➢ADD Rn, PC, #offset

87
 Assembly Language Programming
(Addressing Modes)
• ADR Pseudo-instruction Example:
o EXPORT __main
o AREA LOOKUP_EXAMPLE, READONLY, CODE
o __main
o ADR R2, OUR_FIXED_DATA ; R2 points to OUR_FIXED_DATA
o LDRB R0, [R2] ; load R0 with the contents
o ; of memory pointed to by R2
o ADD R1, R1, R0 ; add R0 to R1
o HERE B HERE ; stay here forever
o OUR_FIXED_DATA
o DCB 0x55, 0x33, 1, 2, 3, 4, 5, 6
o END

88
 Assembly Language Programming
(Addressing Modes)
• SRAM bit-addressable Memory:
o Bit alias address = Bit alias base address + Byte offset × 32 + Bit number × 4

89
 Assembly Language Programming
(Addressing Modes)
• Peripheral bit-addressable region:

90
 Assembly Language Programming
(Arithmetic and Logic Instructions)
• Instructions:
oAdd, subtract, multiply, and divide
instructions
oWith carry
oLogic instructions
oShift and Rotate instructions
oBCD, Packed BCD and ASCII
conversion.
91
 Assembly Language Programming
(Arithmetic and Logic Instructions)
• S suffix in ARM instructions:
Instructions: OpCode S Operands

Instruction (Flags unchanged) Instruction (Flags updated)

ADD Add ADDS Add and set flags
ADC Add with carry ADCS Add with carry and set flags
SUB SUBS SUBS Subtract and set flags
SBC Subtract with carry SBCS Subtract with carry and set flags
MUL Multiply MULS Multiply and set flags
UMULL Multiply long UMULLS Multiply Long and set flags
RSB Reverse subtract RSBS Reverse subtract and set flags
RSC Reverse subtract with carry RSCS Reverse subtract with carry and set flags
Note: The above instruction affect all the N, Z, C, and V flag bits of CPSR
92(current program status register)
 Assembly Language Programming
(Arithmetic and Logic Instructions)
• ADD instruction:
o LDR R2, =0xFFFFFFF5 ; R2 = 0xfffffff5
o MOV R3, #0x0B ; R3 = 0x0B
o ADDS R1, R2, R3 ; R1 = R2 + R3 and update the flags

0xFFFFFFF5 1111 1111 1111 1111 1111 1111 1111 0101

+ 0x0000000B + 0000 0000 0000 0000 0000 0000 0000 1011
0x100000000 1 0000 0000 0000 0000 0000 0000 0000 0000
All zeros

C=1 Z=1

93
 Assembly Language Programming
(Arithmetic and Logic Instructions)
• Adding 64-bit using ADC (Add with carry):
o LDR R0, =0xf62562fa ; r0 = 0xf62562fa
o LDR R1, =0xf412963b ; r1 = 0xf412963b
o MOV R2, #0x35 ; r2 = 0x35
o MOV R3, #0x21 ; r3 = 0x21
o ADDS R5, R1, R0 ; r5 = 0xf62562fa + 0xf412963b
o ; now c = 1
o ADC R6, R2, R3 ; r6 = r2 + r3 + c
o ; = 0x35 + 21 + 1 = 0x57
00 00 00 35 F6 25 62 FA
+ 00 00 00 21 F4 12 96 3B
00 00 00 57 1 EA 37 F9 35

C=1
 Assembly Language Programming
(Arithmetic and Logic Instructions)
• Some ideas about subtraction:
o 100 – 34 = ?
o 99 – 34 = ?
o 100 – 34 = (99 - 34) + 1
o 34 – 19 = ?
o 34 +100 - 19 – 100 = 34 + (99 - 19) + 1 - 100

95
 Assembly Language Programming
(Arithmetic and Logic Instructions)
Some ideas about subtraction (Cont.):
o 100000000 – 00101101 = ?
o = 011111111 – 00101101 + 1 = A
o ➔ – 00101101 = A - 100000000
o 010110110 – 00101101 =
o 010110110 + A – 100000000 =

96
 Assembly Language Programming
(Arithmetic and Logic Instructions)
• Sub instruction:
o MOV R2, #0x4F ; r2 = 0x4f
o SUBS R4, R2, #0x05 ; r4 = r2 – 0x05

0x4F 0000004F
2’s complement
– 0x05 + FFFFFFFB
1 0000004A
0x4A

C=1
(no barrow)

97
 Assembly Language Programming
(Arithmetic and Logic Instructions)
• Using SUBC (SUB with carry):
o LDR r0, =0xf62562fa ; r0 = 0xf62562fa
o LDR r1, =0xf412963b ; r1 = 0xf412963b
o MOV r2, #0x21 ; r2 = 0x21
o MOV r3, #0x35 ; r3 = 0x35
o SUBS r5, r1, r0 ; r5 = r1 – r0
o ; = 0xf412963b – 0xf62562fa
o ; = 0xFDED3341, and c = 0
o SBC r6, r3, r2 ; r6 = r3 – r2 – 1 + c
o ; = 0x35 – 0x21 – 1 + 1 = 0x13

00 00 00 35 F4 12 96 3B F4 12 96 3B
2’s complement
– 00 00 00 21 F6 25 62 FA + 09 DA 9D 06
00 00 00 13 FD ED 33 41 0 FD ED 33 41

C=0
 Assembly Language Programming
(Arithmetic and Logic Instructions)
• Multiplication instruction:
o MUL Rd, Rn, Op2 ; Rd = Rn × Op2
o Example:
➢ MOV R1, #0x25 ; R1=0x25
➢ MOV R2, #0x65 ; R2=0x65
➢ MUL R3, R1, R2 ; R3 = R1 × R2 = 0x65 × 0x25

o UMULL RdLo, RdHi, Rn, Op2 ; RdHi:RdLo = Rn × Op2

o Example:
➢ LDR R1, =0x54000000 ; R1 = 0x54000000
➢ LDR R2, =0x10000002 ; R2 = 0x10000002
➢ UMULL R3, R4, R2, R1 ; 0x54000000 × 0x10000002 = 0x054000000A8000000
➢ ; R3 = 0xA8000000, the lower 32 bits
➢ ; R4 = 0x05400000, the higher 32 bits

o MLA Rd, Rm, Rs, Rn ; Rd = Rm × Rs + Rn

o Example:
➢ MOV R1, #100 ; R1 = 100
➢ MOV R2, #5 ; R2 = 5
➢ MOV R3, #40 ; R3 = 40
➢ MLA R4, R1, R2, R3 99; R4 = R1 × R2 + R3 = 100 × 5 + 40 = 540
 Assembly Language Programming
(Arithmetic and Logic Instructions)
• Division instruction:
o UDIV Rd, Rn, Op2 ; Rd = Rn / Op2
o Example:
➢ mov r1, #8 ; r1 = 8
➢ mov r2, #3 ; r2 = 3
➢ udiv r5, r1, r2 ; r5 = 8 / 3 = 2

100
 Assembly Language Programming
(Arithmetic and Logic Instructions)
• Logic instructions:
o AND Rd,Rn,Op2 ; Rd = Rn AND Op2
o ORR Rd,Rn,Op2 ; Rd = Rn OR Op2
o EOR Rd,Rn,Op2 ; Rd = Rn XOR Op2
o MVN Rd,Op2 ; Rd = 1’s Complement of Op2 (11111111 – Rd)
• AND can be used to clear a specific bit(s) of a byte
• OR can be used to set a specific bit(s) of a byte
Show the results of the following.

MOV R2,#0x35 ;R2 = 0x35

ANDS R3,R2,#0x0F ;R3 = R2 AND 0x0F (now R2 = 0x05)

Solution:

35 0011 0101
AND 0F 0000 1111
05 0000 0101 ;35 AND 0F = 05, Z = 0
 Assembly Language Programming
(Arithmetic and Logic Instructions)
• Setting and Clearing bits:
o OR can be used to set a specific bit(s) of a byte
o AND can be used to clear a specific bit(s) of a byte
o EOR can be used to toggle a specific bit(s) of a byte
04 00000100 44 01000100
OR 30 00110000 EOR 06 00000110
34 00110100 34 01000010

35 00110101
AND 0F 00001111
05 00000101
 Assembly Language Programming
(Rotate and Shift Instructions)
• LSL instruction:
o MOVS Rd, Rn, LSL #numOfShift
o LSL(S) Rd, Rn, #numOfShift ;Logical Shift Left
• In LSL, as bits are shifted from right to left, 0 enters the LSB and the MSB exits
to the carry flag.
• In other words, in LSL 0 is moved to the LSB, and the MSB is moved to the C.

• this instruction multiplies content of the register by 2 if after LSL the carry flag
is not set.
• In the next code you can see what happens to 00100110 aftr running 3 LSL
instructions.
o ;Assume C = 0
o MOV R2 , #0x26 ;R2 = 0000 0000 0000 0000 0000 0000 0010 0110 (38) C = 0
o LSLS R2,R2,#1 ;R2 = 0000 0000 0000 0000 0000 0000 0100 1100 (74) C = 0
o LSLS R2,R2,#1 ;R2 = 0000 0000 0000 0000 0000 0000 1001 1000 (148) C = 0
o LSLS R2,R2,#1 ;R2 = 0000 0000 0000 0000 0000 0001 0011 0000 (296) C = 0
 Assembly Language Programming
(Rotate and Shift Instructions)
• LSR instruction:
o LSR(S) Rd, Rn, #numOfShift ;Logical Shift Right
o MOVS Rd, Rn, LSR #numOfShift
• In LSR, as bits are shifted from left to right, 0 enters the MSB and the
LSB exits to the carry flag.
• In other words, in LSR 0 is moved to the MSB, and the LSB is moved to
the C.

• this instruction divides content of the register by 2 and carry flag

contains the remainder of division.
• In the next code you can see what happens to 0010 0110 after running 3
LSR instructions.
o MOV R2, #0x26 ;R2 = 0000 0000 0000 0000 0000 0000 0010 0110 (38)
o LSRS R2, R2, #1 ;R2 = 0000 0000 0000 0000 0000 0000 0001 0011 (19) C = 0
o LSRS R2, R2, #1 ;R2 = 0000 0000 0000 0000 0000 0000 0000 1001 (9) C = 1
o LSRS R2, R2, #1 ;R2 = 0000 0000 0000 0000 0000 0000 0000 0100 (4) C = 1
 Assembly Language Programming
(Rotate and Shift Instructions)
• ROR instruction (Rotate Right):
o ROR Rd, Rm, #numOfShifts ;Rotate Rm right Rn bit positions
o MOVS Rd, Rm, ROR #numOfShifts
• In ROR, as bits are rotated from left to right, the LSB goes to the
MSB and to the carry flag.

• See what happens to 0010 0110 after running 3 ROR instructions:

o ;assume C = 0 (carry is 0 )
o MOV R2, #0x26 ;R2 = 0000 0000 0000 0000 0000 0000 0010 0110
o RORS R2, R2, #1 ;R2 = 0000 0000 0000 0000 0000 0000 0001 0011 C = 0
o RORS R2, R2, #1 ;R2 = 1000 0000 0000 0000 0000 0000 0000 1001 C = 1
o RORS R2, R2, #1 ;R2 = 1100
105 0000 0000 0000 0000 0000 0000 0100 C = 1
 Assembly Language Programming
(Rotate and Shift Instructions)
• RRX instruction (Rotate Right with extend):
o RRX(S) Rd, Rm ;Rotate Rm right 1 bit through C flag
o MOVS Rd, Rm, RRX
• In RRXS, as bits are rotated from left to right, the carry flag
enters the MSB and the LSB exits to the carry flag.
• In other words, in RRXS the C is moved to the MSB, and the LSB
is moved to the C.

• See what happens to 0010 0110 after running 3 ROR instructions:

o ;assume C = 0 (carry is 0 )
o MOV R2, #0x26 ;R2 = 0010 0000 0000 0000 0000 0000 0000 0110
o RRXS R2, R2 ;R2 = 0001 0000 0000 0000 0000 0000 0000 0011 C = 0
o RRXS R2, R2 ;R2 = 0000 0000 0000 0000 0000 0000 0000 1001 C = 1
o RRXS R2, R2 ;R2 = 1000 0000 0000 0000 0000 0000 0000 0100 C = 1
 Assembly Language Programming
(Rotate and Shift Instructions)
• BCD, Packed BCD and ASCII conversion:
•BCD Codes
•ASCII
BCD Codes
Packed BCD

BCD1 BCD0

ASCII and BCD Codes

107 for Digits 0–9
 Assembly Language Programming
(Rotate and Shift Instructions)
• Packed BCD to ASCII conversion:
o To convert packed BCD to ASCII:
o you must first convert it to unpacked BCD.
o Then the unpacked BCD is tagged with 011 0000
(30H).
➢ Packed BCD = 1001 0010

➢ Unpacked BCD = 0000 1001 , 0000 0010

➢ ACSII = 0011 1001 , 0011 0010

 Assembly Language Programming
(Signed Numbers)
• 8-bit Signed numbers:

Decimal Binary Hex

-128 1000 0000 80
-127 1000 0001 81
-126 1000 0010 82
... .... ... ..
-2 1111 1110 FE
-1 1111 1111 FF
0 0000 0000 00
+1 0000 0001 01
+2 0000 0010 02
… .... .... ..
+127 0111 1111 7F
109
 Assembly Language Programming
(Signed Numbers)
• 16-bit Signed numbers:

Decimal Binary Hex

-32,768 1000 0000 0000 0000 8000
-32,767 1000 0000 0000 0001 8001
-32,766 1000 0000 0000 0010 8002
... .... ... ..
-2 1111 1111 1111 1110 FFFE
-1 1111 1111 1111 1111 FFFF
0 0000 0000 0000 0000 0000
+1 0000 0000 0000 0001 0001
+2 0000 0000 0000 0010 0002
… .... .... …
+32,766 0111 1111 1111 1110 7FFE
+32,767 110
0111 1111 1111 1111 7FFF
 Assembly Language Programming
(Signed Numbers)
• 32-bit Signed numbers:

Decimal Binary Hex

-2,147,483,648 10000000000000000000000000000000 80000000
-2,147,483,647 10000000000000000000000000000001 80000001
-2,147,483,646 10000000000000000000000000000010 80000002
... ... ...
-2 11111111111111111111111111111110 FFFFFFFE
-1 11111111111111111111111111111111 FFFFFFFF
0 00000000000000000000000000000000 00000000
+1 00000000000000000000000000000001 00000001
+2 00000000000000000000000000000010 00000002
... ... ...
+2,147,483,646 01111111111111111111111111111110 7FFFFFFE
+2,147,483,647 111
01111111111111111111111111111111 7FFFFFFF
 Assembly Language Programming
(Signed Numbers)
• Adding signed numbers:
o MOV R1, 0xFC ; r1 = 1111 0101
o MOV R2, #0x07 ; r2 = 0000 0111
o ADDS R3, R1, R2 ; r3 = r1 + r2

Considering 8-bit Considering 8-bit

signed numbers unsigned numbers
-11 1111 0101 245
+ +7 + 0000 0111 + 7
-4 1111 1100 252

112
 Assembly Language Programming
(Signed Numbers)
• Overflow:
0110 0000 +96
+ 0100 0110 + +70
1010 0110 -90

o There is a carry from D6 to D7 but no carry out of D7

(C = 0).
o Carry:
➢There is a carry from D7 out (C = 1) but no carry from D6
to D7 113
 Assembly Language Programming
(Signed Numbers)
• Overflow:
o Solving the Overflow problem:
➢ Choose proper types for variables

0000 0000 0110 0000 +96

+0000 0000 0100 0110 + +70
0000 0000 1010 0110 +166

114
 Assembly Language Programming
(Signed Numbers)
• Overflow (V) and Negative (N) flags in ARM:
o In a 32-bit operation, V is set to 1 in either of two
cases:
➢ There is a carry from D30 to D31 but no carry out of D31 (C = 0).
➢ There is a carry from D31 out (C = 1) but no carry from D30 to D31.

+6E2F356F 0110 1110 0010 1111 0011 0101 0110 1111

+ +13D49530 +0001 0011 1101 0100 1001 0101 0011 0000
V =1
+8203CA9F 01000 0010 0000 0011 1100 1010 1001 1111 = –0x7DFC3561
C =0 N =1
 Assembly Language Programming
(Signed Numbers)
• Multiplication of Signed numbers:
o Unsigned Multiplication 1111 1101 253
➢MUL Rd,Rn,Op2 × 0000 0010 × 2
➢UMULL RdLo,RdHi,Rn,Rm 11111 1010 506
o Signed Multiplication
➢SMULL Rdlo,Rdhi,Rm,Rn 1111 1101 -3
× 0000 0010 × 2
1111 1010 -6
 Assembly Language Programming
(Signed Numbers)
• Division of Signed numbers:
o Unsigned Division
➢UDIV Rd, Rm, Rn
✓; Rd = Rm / Rn
o Signed Division
➢SDIV Rd,Rm,Rn
✓; Rd = Rm / Rn
 Assembly Language Programming
(Signed Numbers)
• ASR (Arithmetic Shift Right) Instruction:
o ASR(S) Rd, Rm, #count @Arithmetic Shift Right
o MOVS Rd, Rm, ASR #count
o ASR means arithmetic shift right. ASR instruction can divide signed number by 2.
o In ASR, as bits are shifted from left to right, MSB is held constant and the LSB exits to
the carry flag.
o In other words MSB is not changed but is copied to D6, D6 is moved to D5, D5 is moved
to D4 and so on.

o In the next code you can see what happens to 0010 0110 after running 5 ASR
instructions.
o MOV R2, #0xD0 @R2 = 0000 0000 0000 0000 0000 0000 1101 0000(-48) C = 0
o ASRS R2, R2, #1 @R2 = 0000 0000 0000 0000 0000 0000 1110 1000(-24) C = 0
o ASRS R2, R2, #1 @R2 = 0000 0000 0000 0000 0000 0000 1111 0100(-12) C = 0
o ASRS R2, R2, #1 @R2 = 0000 0000 0000 0000 0000 0000 1111 1010(-6) C = 0
o ASRS R2, R2, #1 @R2 = 0000 0000 0000 0000 0000 0000 1111 1101(-3) C = 0
o ASRS R2, R2, #1 @R2 = 0000 0000 0000 0000 0000 0000 1111 1110(-1) C = 1
 Assembly Language Programming
(Signed Numbers)
• Signed number comparison:
o CMP Rn, Op2
➢ Op2 > Rn V=N
➢ Op2 = Rn Z=1
➢ Op2 < Rn N≠V

Instruction Action
BEQ Branch equal Branch if Z = 1
BNE Branch not equal Branch if Z = 0
BMI Branch minus (branch negative) Branch if N = 1
BPL Branch plus (branch positive) Branch if N = 0
BVS Branch if V set (branch overflow) Branch if V = 1
BVC Branch if V clear (branch if no overflow) Branch if V = 0
BGE Branch greater than or equal Branch if N = V
BLT Branch less than Branch if N ≠ V
BGT Branch greater than Branch if Z = 0 and N = V
BLE Branch less than or equal Branch if Z = 1 or N ≠ V
 Assembly Language Programming
(Signed Numbers)
• In this program, the result is incorrect!:
o ; storing data in program memory.
o EXPORT __main
o AREA NotExtendingExample, CODE, READONLY
o __main
o LDR R0,=AA
o LDRB R1,[R0] ;read AA
o LDR R0,=BB
o LDRB R2,[R0] ;read BB
o SDIV R3,R1,R2 ;R3 = R1 / R2
o HERE B HERE
R1 = 0x000000E7 = 231
o AA DCB -25 R2 = 0x000000FE = 254
o BB DCB -2 R0 = R1 / R2 = 231 / 254 = 0

120
 Assembly Language Programming
(Signed Numbers)
• Sign extending a byte:
o LDRSB Rn, [Rs]
D31 D8 D7 D6 ... D0
sign magnitude
upper 24-bit 8-bit

o Example 1:
➢ ; assume memory location 0x80000 has +96 = 0110 0000 and R1=0x80000
➢ LDRSB R0, [R1] ; now R0 = 00000000000000000000000001100000
o Example 2:
➢ ; assume memory location 0x80000 contains -2 = 1111 1110 and R2=0x80000
➢ LDRSB R4, [R2] ; now R4 = 11111111111111111111111111111110
 Assembly Language Programming
(Signed Numbers)
• Sign extending a half word:
o LDRSH Rn, [Rs]
D31 D16 D15 D14 ... D0
sign magnitude
upper 16-bit 16-bit

o Example 1:
➢ ; assume 0x80000 contains +260 = 0000 0001 0000 0100 and r1=0x80000
➢ LDRSH R0, [r1] ; R0=0000 0000 0000 0000 0000 0001 0000 0100
o Example 2:
➢ ; assume location 0x20000 has -327660=0x8002 and R2=0x20000
➢ LDRSH R1, [r2] ; R1=FFFF8002
 Assembly Language Programming
(Signed Numbers)
• Now, the result is correct!:
o ; storing data in program memory.
o EXPORT __main
o AREA ExtendingExample, CODE, READONLY
o __main
o LDR R0,=AA
o LDRSB R1,[R0] ;read AA
o LDR R0,=BB
o LDRSB R2,[R0] ;read BB
o SDIV R3,R1,R2 ; R3 = R1 / R2
o HERE B HERE
R1 = 0xFFFFFFE7 = -25
o AA DCB -25
R2 = 0xFFFFFFFE = -2
o BB DCB -2 R0 = R1 / R2 = -25 / -2 = 12

123
 Assembly Language Programming
(Signed Numbers)
• Avoiding overflow by using proper variables:
o EXPORT __main
o AREA EXAMPLE5_14, CODE, READONLY
o __main
o LDR R1, =DATA1
o LDR R2, =DATA2
o LDR R3, =RESULT
o LDRSB R4, [R1] ; R4 = +96
o LDRSB R5, [R2] ; R5 = +70
o ADD R4, R4, R5 ; R4 = R4 + R5 = 96 + 70 = +166
o STR R4, [R3] ; Store +166 in location RESULT
o HL B HL
o DATA1 DCB +96
o DATA2 DCB +70
o ALIGN
o AREA VARIABLES, DATA, READWRITE ; The following is stored in RAM
o RESULT DCW 0
o END 124
 Assembly Language Programming
(Branch & Call Instructions)
• Topics:
o Introduction to branch and call
o Branch
o Call
➢LR
➢Calling a function
o Time Delay

125
 Assembly Language Programming
(Branch & Call Instructions)
• CPU executes instructions
one after another. 1 void main ()
2 {
o For example in the following 3 a = b + c;

C program, CPU first 4

5
c -= 2;
d = a + c;

executes the instruction of line 6 }

3 (adds b and c), then executes

the instruction of line 4.
 Assembly Language Programming
(Branch & Call Instructions)
• But sometimes we need the CPU to execute,
an instruction other than the next
instruction. For example:
o When we use a conditional instruction (if)
o When we make a loop
o When we call a function

127
 Assembly Language Programming
(Branch & Call Instructions)
• Example 1: Not executing
the next instruction, 1
2
void main ()
{

because of condition. 3
4
int a = 2;
int c = 3;

o In the following example, 5

6
if (a == 8)
c = 6;

the instruction of line 6 is 7 else

8 c = 7;
not executed. 9 c = a + 3;
}
 Assembly Language Programming
(Branch & Call Instructions)
• Example 2: In this example
the next instruction will not 1 void main ()
2 {
be executed because of loop. 3 int a, c = 0;
4 for(a = 2; a < 4; a++)
o In the following example, the 5 c += a;

order of execution is as follows: 6

7 }
a = c + 2;

➢Line 4 8
9
➢Line 5
➢Again, line 4
➢Again line 5
➢Line 6
 Assembly Language Programming
(Branch & Call Instructions)
• Example 3: Not Code

executing the next 1

2
void func1 ();
void main ()

instruction, because of 3
4
{
int a = 2, c = 3;

calling a function. 5
6
func1 ();
c = a + 3;

o In the following example,

7 }
8 void func1 (){

the instruction of line 6 is 9

10 }
int d = 5 / 2;

not executed after line 5. 11

 Assembly Language Programming
(Branch & Call Instructions)
• In the assembly language, there are 2 groups of
instructions that make the CPU execute an
instruction other than the next instruction. The
instructions are:
o Branch: used for making loop and condition
o Call: used for making function calls

131
 Assembly Language Programming
(Branch & Call Instructions)
• Branch:
o Branch changes the Program Counter (PC) and
causes the CPU to execute an instruction other than
the next instruction.

132
 Assembly Language Programming
(Branch & Call Instructions)
• Branch in ARM:
Code
o There are 2 branch instructions in 1 MOV R1, #0

ARM: B and BX. 2 MOV R2, #2

3 L1
L1 ADD R1, R1, R2
o We label the location where we want 4 B L1 L1

to jump, using a unique name 5 SUB R10,R1,R5

o Then, in front of the branch

instruction we mention the name of
the label.
o This causes the CPU to jump to the
location we have labeled, instead of
executing the next instruction.
 Assembly Language Programming
(Branch & Call Instructions)
• Ways of specifying the branch target:
o B and BX provide the branch address using 2
different ways:
o B operand
➢PC = PC + (operand*2)
o BX Rn
➢PC = Rn register

134
 Assembly Language Programming
(Branch & Call Instructions)
• B (Branch):
oB PC = PC + (operand×2)
➢To execute B: The operand shifts left and then it is
added to the current value of PC.
1110 0xxx XXXX XXXX

➢Example:
✓Operand = 000000000111
✓ PC = PC + 000000001110

1110 0000 0000 0000 0000 0000 0000 0111

 Assembly Language Programming
(Branch & Call Instructions)
• B instruction:
o To execute B the operand shifts left and then it is added to the current value
of PC.
o Cortex-M has a 3-stage pipeline. So, when an instruction is executed, PC
points to 4 bytes below.
PC: 0800001C
0800000C
0800001E
08000010
08000014 Address Code
+ 8000008 EXPORT __main
00000018 8000008 __main MOV R1,#0x15
Machine code:
opCode operand
800000C MOV R7, #5

E002 8000010 B LBL_NAME

Shift left 8000012 MOV R8, #4
00000004
8000016 ADD R8, R8, R7
8000018
8000018 LBL_NAME
Machine code:
opCode operand 8000018 ADD R6, R6, R7
E7FD 800001A B LBL_NAME
FFFFFFFA 800001C
 Assembly Language Programming
(Branch & Call Instructions)
• BX Instruction:
o BX Rn PC = Rn 0100 0111 0nnn n000

BX R3 0100 0111 0001 1000

o The Program counter is loaded with the

contents of Rn register.
➢For example, if R5 points to location 100, by
executing BX R5, the CPU jumps to location
100.
 Assembly Language Programming
(Branch & Call Instructions)
• BX Instruction:
o To execute BX:
➢The value of a register is loaded to the PC.
Address Code
PC: 0800000C
08000010
08000012 8000008 AREA PROG,CODE,READONLY
8000008 __main MOV R1,#0x15
R7: 00000000
80000016 800000C LDR R7, =LBL1
800000E BX R7
8000010 MOV R8, #4
8000014 ADD R8, R8, R7
8000016
8000016 LBL1
8000016 ADD R6, R6, R7
8000018 B LBL1
800001A
 Assembly Language Programming
(Branch & Call Instructions)
• Conditional
D31
Jump
D30
in D28
D29
ARM:………. D7 D6 D5 D4 D3 D2 D1 D0
N Z C V Reserved I F T M4 M3 M2 M1 M0

Negative
oVerflow
Zero carry
o The conditional jump instructions in ARM are as follows:
Instruction Abbreviation of Action
BCS lbl branch if carry set Branch to location lbl if C = 1
BHS lbl branch if higher or same
BCC lbl branch if carry clear Branch if C = 0
BLO lbl branch if lower
BEQ lbl branch if equal Branch if Z = 1
BNE lbl branch if not equal Branch if Z = 0
BLS lbl branch if lower or same Branch if Z = 1 or C = 0
BHI lbl branch if higher Branch if Z = 0 and C = 1
o The N and V flags are related to signed numbers and their branch instructions
are discussed in Chapter 5.
 Assembly Language Programming
(Branch & Call Instructions)
• Conditional vs. Unconditional:
oThere are 2 kinds of Branch
➢Unconditional Branch: When CPU
executes an unconditional branch, it jumps
unconditionally (without checking any condition)
to the target location.
✓Example: BX and B instructions
➢Conditional Branch: When CPU executes a
conditional branch, it checks a condition, if the
condition is true then it jumps to the target
location; otherwise, it executes the next instruction.
 Assembly Language Programming
(Branch & Call Instructions)
• Usages of Conditional jump:
o Conditions
a
➢When b is subtracted from a:
➢The result is zero, when a is equal to b -b
➢Carry will be set when a >= b
o Loop
 Assembly Language Programming
(Branch & Call Instructions)
• Example 1:
oWrite a program that if R0 is equal to R1
then R2 increases. R0 == R1
No

oSolution: Yes
➢ SUBS R0, R0, R1 ;Z will be set if R0 == R1
➢ BNE NEXT ;if Not Equal jump to next
ADD R2, R2, #1 increment R2
➢ NEXT
 Assembly Language Programming
(Branch & Call Instructions)
• Example 2:
oWrite a program that if R6 < R4 then R2
increases. R6 < R4
No

oSolution: Yes
➢ SUBS R6,R6,R4 ;C will be set when R6 >= R4
➢ BCS L1 ;if Carry set jump to L1
➢ ADD R2,R2,#1 increment R2
➢ L1
 Assembly Language Programming
(Branch & Call Instructions)
• Example 3:
oWrite a program that if R6 >= R4 then
R2 increases. R6 >= R4
No

oSolution: Yes
➢ SUBS R6,R6,R4 ;C will be set when R6 >= R4
➢ BCC L1 ;jump to L1 if Carry cleared
➢ ADD R2,R2,#1 increment R2
➢ L1
 Assembly Language Programming
(Branch & Call Instructions)
• Example 4 (IF and ELSE): R7 = 5
o int main ( )
o {
o R7 = 5;
No
o if (R0 > R1) R0 > R1
o R2++;
o else Yes
o R2--;
o R7++;
o } increment R2

MOV R7,#5 decrement R2

SUBS R1,R1,R0 ;C is set when R1 >= R0
BCS ELSE_LABEL ;jump to else if set
ADD R2,R2,#1
JMP NEXT
ELSE_LABEL
increment R7
SUB R2,R2,#1
NEXT
ADD R7,R7,#1
 Assembly Language Programming
(Branch & Call Instructions)
• Loop:
o Write a program that executes the instruction “ADD
R3,R3,R1” 9 times. R6 = 9

o Solution:
➢ MOV R6,#9 ;R6 = 9 R3 = R3 + R1

➢ L1 ADD R3,R3,R1
➢ SUBS R6,R6,#1 ;R6 = R6 - 1 R6 = R6 - 1

➢ BNE L1 ;if Z = 0
➢ L2 B L2 ;Wait here forever
Yes
R6 > 0

No

END
 Assembly Language Programming
(Branch & Call Instructions)
• Loop:
o Write a program that calculates the result of
9+8+7+…+1
R6 = 9

o Solution: R7 = 0

➢ MOV R6, #9 @R6 = 9 R7 = R7 + R6

➢ MOV R7, #0 @R7 = 0
➢ L1 ADD R7,R7,R6 @R7 = R7 + R6
R6 = R6 - 1
➢ SUBS R6,R6,#1 @R6 = R6 - 1
➢ BNE L1 @if Z = 0
➢ L2 B L2 @Wait here forever
Yes
R6 > 0

No

END
 Assembly Language Programming
(Branch & Call Instructions)
• Loop:
o Write a program that calculates the result of
20+19+18+17+…+1 R6 = 20
R7 = 0

o Solution:
➢ MOV R6, #20 @R6 = 20 R7 = R7 + R6

➢ MOV R7, #0 @R7 = 0

➢ L1 ADD R7,R6,R6 @R7 = R7 + R6 R6 = R6 - 1

➢ SUBS R6,R6,#1 @R6 = R6 - 1

➢ BNE L1 @if Z = 0
➢ L2 B L2 @Wait here forever Yes
R6 > 0

No

END
 Assembly Language Programming
(Branch & Call Instructions)
• Loop:
o for (init; condition; calculation) init

o{
Do something

o do something
o} calculation

Yes
Condition

No

END
 Assembly Language Programming
(Branch & Call Instructions)
• Loop:
o Write a program that calculates 1+3+5+…+27
R0 = 0
o Solution: R6 = 1

➢ MOV R0,#0
R0 = R0 + R6
➢ MOV R6,#1
➢ L1 ADD R0,R0,R6
R6 = R6 + 2
➢ ADD R6,R6,#2 ;R16 = R16 + 2
➢ SUBS R7,R6,#27
➢ BCC L1 ;if R6 <= 27 jump L1
Yes
R6 <= 27

No

END
 Assembly Language Programming
(Branch & Call Instructions)
• CMP instruction:
o CMP sets the flags the same way as SUBS. But does
not store the result of subtraction. So, it suits for
comparing.

MOV R0,#0 MOV R0,#0

MOV R6,#1 MOV R6,#1
L1 ADD R0,R0,R6 L1 ADD R0,R0,R6
ADD R6,R6,#2 ADD R6,R6,#2
SUBS R7,R6,#27 CMP R6,#27
BCC L1 BCC L1
 Assembly Language Programming
(Branch & Call Instructions)
• Conditional Execution in ARM (Case Study)
31 28 27 26 0

Cond Instruction
Bits Mnemonic Extension Meaning Flag
0000 EQ Equal Z=1
0001 NE Not equal Z=0
0010 CS/HS Carry Set/Higher or Same C=1
0011 CC/LO Carry Clear/Lower C=0
0100 MI Minus/Negative N=1
0101 PL Plus N=0
0110 VS V Set (Overflow) V=1
0111 VC V Clear (No Overflow) V=0
1000 HI Higher C = 1 and Z = 0
mov 1001 r1, #10 HS ; r1 = 10Lower or Same C = 1 and Z = 1
cmp 1010 r1, #0GE ; compare r1 than
Greater withor 0
Equal N=V
addne 1011 r1, r1,LT#10 ; this line is executed if z = 0
Less than N≠V
1100 GT ; (if in the lastthan
Greater cmp operands were not equal)
Z = 0 and N = V
1101 LE Less than or Equal Z = 0 or N ≠ V
1110 AL Always (unconditional)
1111 --- Not Valid
 Assembly Language Programming
(Branch & Call Instructions)
• Calling a Function:
o To execute a call:
➢ Address of the next instruction is saved in LR (R14).
➢ PC is loaded with the subroutine address
Address Code
08000010 AREA PROG,CODE,READONLY
08000010 __main MOV R1, #5
Machine code: 08000014 MOV R2, #6
F000F803 08000018 BL FUNC_NAME
Shiftoperand
opCode left 0800001C
0800001C MOV R2, #6
0006 08000020 L1 B L1
08000022 FUNC_NAME
LR: 0800001C
00000000
08000022 ADD R2,R2,R1
08000024 SUB R2,R2,#3
PC: 0800001C
08000014
08000028
08000024
0800002C
08000018 08000028 BX LR
+ 0800002A
08000022
 Assembly Language Programming
(Branch & Call Instructions)
• PROC and ENDP:
o The directives are used to mark the beginning and
end of a subroutine:
➢FUNC_NAME PROC
➢ ...
➢ BX LR
➢ ENDP
Assembly Language Programming
(Time delay)

Microcontroller
XTAL1
TMachine cycle = 1
XTAL2
FXTAL

For F = 1GHz: TMachine = 1 = 1 ns

cycle 1GHz
Assembly Language Programming
(Time delay)
machine cycle
MOV R6, #19 1
MOV R0, #95 1
MOV R1, #5 1
ADD R6, R6, R0 1
ADD R6, R6, R1 1
5

Delay = 5 x T machine cycle = 5 x 1 ns = 5 ns

Assembly Language Programming
(Time delay)

machine cycle
MOV R6, #100 1
AGAIN: ADD R7,R7,R6 1 *100
SUBS R6,R6,#1 1 *100
BNE AGAIN 1/3 *100

Branch penalty
Assembly Language Programming
(Time delay)

machine cycle
MOV R6, #50
1
AGAIN: NOP
1 *50
NOP
1 *50
SUBS R6,R6,#1
1 *50
BNE AGAIN 1/3 *50

158
Assembly Language Programming
(Time delay)

machine cycle
MOV R7, #20
1
L1: MOV R6, #50
1 *20
L2: NOP
1 *20 * 50
NOP
1 *20 * 50
SUBS R6,R6,#1 1 *20 * 50
BNE L2 1/3 *20 * 50
SUBS R7,R7,#1 1 *20
BNE L1 1/3 *20

159
Assembly Language Programming
(Stack - Push and Pop)
Push Pop
 Assembly Language Programming
(Stack - Push and Pop)
• R13 is the stack pointer
• PUSH {Rn}
o SP = SP – 4 0x2000050
0x2000054
o [SP] = Rn 0x2000058
0x200005C
• POP {Rn} 0x2000060
SP 0x2000064
o Rn = [SP]
o SP = SP + 4
 Assembly Language Programming
(Stack - Push and Pop)
• PUSH {register list}
o PUSH {R10}
o PUSH {R2,R3,R5}
o PUSH {R5-R9}
• POP {register list}
o POP {R9}
o POP {R4-R11}
o POP {R1-R4,R7}
Assembly Language Programming
(Stack)
Address Code

...
R0: 00000000
00000010 LDR R0,=0x10
LDR R1,=0x20
R1: 00000000
00000020
LDR R2,=0x30
R2: 00000030
00000000 0x00000010
PUSH {R0}
0x00000020
PUSH {R1}
0x00000030
PUSH {R2}
MOV R0,#0
MOV R1,#0
MOV R2,#0
POP {R2}

20005F0 POP {R1}

20005F4 POP {R0}
20005F8 L1 B L1
20005FC
2000600
SP Memory
Assembly Language Programming
(Stack - Initialization)
CPU Memory
20002000 00000000
00001001 00000004
SP (R13): 00000008

PC (R15): 00001000
Flash Boot
memory program

20000000
Stack
SRAM 20001FFF
20002000
3FFFFFFF
 Assembly Language Programming
(Stack - Startup File)
; memory allocation for stack
Stack_Size EQU 0x00000400 Stack
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; Heap Configuration
Heap_Size EQU 0x00000200 Heap
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit

PRESERVE8
THUMB Vector Table
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
Assembly Language Programming
(Stack - Memory Allocation)
Memory
__Vectors 20000600 00000000
080000ED 00000004
00000008

Flash
Reset_Handler Reset 080000ED memory
program
SystemInit System init

__main main

Heap_Mem 20000000
Heap
200001FF
Stack_Mem 20000200
Stack SRAM
200005FF
__initial_sp 20000600
 Assembly Language Programming
(Stack)
• Some Stack Usages Nested Calls:
EXPORT __main
AREA MY_CODE, CODE, READONLY
__main
BL FUNC1
HERE B HERE
; subroutine FUNC1
FUNC1 PROC
PUSH {LR} ;store the LR on the stack
BL FUNC2 ;the func. call changes the LR
POP {LR} ;restore the LR value from the stack
BX LR
ENDP
; subroutine FUNC2
FUNC2 PROC
;do something
BX LR ; return
ENDP
END
 Assembly Language Programming
(Stack)
• Some stack usages Preserving registers values:
EXPORT __main
AREA MY_CODE, CODE, READONLY
__main PROC
BL DELAY
HERE B HERE
ENDP

DELAY PROC
PUSH {R7} ;store R7 onto the stack
LDR R7,=120000
D_1 SUBS R7,R7,#1
BNE D_1
POP {R7} ;restore R7
BX LR
ENDP
END
Question?

169