Interpolator
Overview
The first component of any process flow is the Framework. After that the user may determine that
interpolation and/or decimation filters are required in their design.
The following table lists (under “Matching Components”) the associated stereo Interpolators and
Decimators for each Framework. Additionally, there are single channel versions of each Interpolator and
Decimator (prefaced with “Mono”) available.
Sample
Matching Matching
Framework Rates
Components Description Components Description
Name Supported
(miniDSP_A) (miniDSP_D)
(Fs) Kbps
48, 44.1, 4x Decimation 8x Interpolation
Dec4xIn Int8xOut
AIC3254 8x4x/ 32, 24, (Stereo) (Stereo)
AIC3262 8x4x 22.05, 16, 4x Decimation 8x Interpolation
11.025, 8 MonoDec4xIn MonoInt8xOut
(Mono) (Mono)
2x Decimation 4x Interpolation
Dec2xIn Int4xOut
AIC3254 4x2x/ (Stereo) (Stereo)
96, 88.2
AIC3262 4x2x 2x Decimation 4x Interpolation
MonoDec2xIn MonoInt4xOut
(Mono) (Mono)
1x Decimation 2x Interpolation
Dec1xIn Int2xOut,
AIC3254 2x1x / (Stereo) (Stereo)
192, 176.4
AIC3262 2x1x 1x Decimation 2x Interpolation
MonoDec1xIn MonoInt2xOut
(Mono) (Mono)
8x Interpolation
48, 44.1, Int8xOut
TSC2117/AIC36 (Stereo)
32, 24, 16, MonoDec4xIn 4x Decimation
8x4x Synch 8x Interpolation
11.025, 8 MonoInt8xOut
(Mono)
4x Interpolation
Int4xOut
TSC2117/AIC36 (Stereo)
96, 88.2 MonoDec2xIn 2x Decimation
4x2x Synch 4x Interpolation
MonoInt4xOut
(Mono)
2x Interpolation
Int2xOut
TSC2117/AIC36 (Stereo)
192, 176.4 MonoDec1xIn 1x Decimation
2x1x Synch 2x Interpolation
MonoInt2xOut
(Mono)
8x Interpolation
48, 44.1, Int8xOut
TSC2117/AIC36 (Stereo)
32, 24, 16, MonoDec4xIn 4x Decimation
8x4x Asynch 8x Interpolation
11.025, 8 MonoInt8xOut
(Mono)
4x Interpolation
Int4xOut
TSC2117/AIC36 (Stereo)
96, 88.2 MonoDec2xIn 2x Decimation
4x2x Asynch 4x Interpolation
MonoInt4xOut
(Mono)
8x Interpolation
48, 44.1, Int8xOut
TSC2117/AIC36 (Stereo)
32, 24, 16, MonoDec4xIn 4x Decimation
8x4x Asynch 8x Interpolation
11.025, 8 MonoInt8xOut
(Mono)
48, 44.1, Dec4xIn
ADC3x01 4x 32, 24, 16, 4x Decimation Not Applicable Not Applicable
11.025, 8 MonoDec4xIn
Dec2xIn
ADC3x01 2x 96, 88.2 2x Decimation Not Applicable Not Applicable
MonoDec2xIn
Dynamic Range Compression (DRC) Feature
All Interpolators may include a DRC feature in the DAC channel. This is hardware DRC and its
parameters can be set on Runtime Properties window. Include_DRC Design time property has to be
set to YES for hardware DRC to become active.
The DRC algorithm works independently for Left and Right DAC channels. The DRC serves to limit the
digital gain provided to the DAC data so as to limit the output data when it is expected to exceed
beyond a specified threshold. The rate at which the DRC decreases or increases the gain according to
variations in the input amplitude or programmed gain is limited by the attack and decay parameters
specified by the user through control registers.
Figure: Combined transfer function of the DRC and PGA
Configurable Properties (Design Time)
Property Scaling Description
Include_DRC YES or NO Enables and Disables DRC
Configurable Properties (Run Time)
Property Permitted Values Description
DRC_Enable YES / NO DRC Enable or Disable. Make
sure to set Include_DRC in
Design Time Configurable
Properties to YES to activate the
DRC block.
Volume_Control_dB -63.5dB to 24dB Digital Volume Control.
Programmable gain of a digital
volume control block that can
control the volume of the
playback signal from +24dB to –
63.5dB in steps of 0.5dB. Default
value is 0dB. Performance of
DRC can become more
noticeable if this value is set very
high.
Energy_Time_Constant_ms 1 to 350 ms Used in the signal energy
calculations by DRC. Only
effective when Include_DRC is
YES
DRC_Hyteresis 0dB, 1dB, 2dB, 3 dB It can be programmed to values
between 0dB and 3dB in steps of
1dB. It is a programmable
window around the programmed
DRC Threshold that must be
exceeded for a disabled DRC to
become enabled, or an enabled
DRC to become disabled. For
example, if the DRC Threshold is
set to -12dBFS and DRC
Hysteresis is set to 3dB, then if
the gain compression in the DRC
is inactive, the output of the DAC
Digital Volume Control must
exceed –9dBFS before gain
compression due to the DRC is
activated. Similarly, when the
gain compression in the DRC is
active, the output of the DAC
Digital Volume Control needs to
fall below -15dBFS for gain
compression in the DRC to be
deactivated. The DRC Hysteresis
feature prevents the rapid
activation and de-activation of
gain compression in the DRC in
cases when the output of DAC
Digital Volume Control rapidly
fluctuates in a narrow region
around the programmed DRC
Threshold. By programming the
DRC Hysteresis as 0dB, the
hysteresis action is disabled.
Recommended Value of DRC
Hysteresis is 3 dB.
DRC_Threshold_dBFS -24dB to -3dB DRC threshold. Level of signal at
which gain compression
becomes active.
DRC_HOLD_Time_WordCLK 0, 32, 64, 128,…..,128x4096 DRC hold time in word clocks.
DRC Hold is intended to slow the
start of decay for a specified
period of time in response to a
decrease in energy level.
DRC_Attack_Rate_perWCLK 4dB, 2dB, 1dB, 1/2dB,……, DRC attack rate per DAC word
1/4096dB clock. When the output of the
DAC Digital Volume Control
exceeds the programmed DRC
Threshold, the gain applied in the
DAC Digital Volume Control is
progressively reduced to avoid
the signal from saturating the
channel. This process of reducing
the applied gain is called Attack.
DRC_Decay_Rate_perWCLK 1/64dB, 1/128dB, DRC decay rate per DAC word
1/256dB,….., 1/2097152dB clock. When the DRC detects a
reduction in output signal swing
beyond the programmed DRC
Threshold, the DRC enters a
Decay state, where the applied
gain in Digital Volume Control is
gradually increased to
programmed values.
HPF_n0 -1 to High pass filter coefficient n0
0.99999988079071044921875
HPF_n1 -1 to High pass filter coefficient n1
0.99999988079071044921875
HPF_d1 -1 to High pass filter coefficient d0
0.99999988079071044921875
I2C Interface
I2C DSP Memory Size
Description
Address Address
DSPCoefBlockStart1 4
I2CAddress1 Alpha
bytes
DSPCoefBlockStart2 4
I2CAddress2 1minus2alpha
bytes
DSPCoefBlockStart3 4 HPF_n0
I2CAddress3
bytes
DSPCoefBlockStart4 4 HPF_n1
I2CAddress4
bytes
DSPCoefBlockStart5 4 HPF_d1
I2CAddress5
bytes
Alpha and 1-2alpha are DRC energy filter coefficients; they are calculated by Energy Time Constant.