CPU_Arthmatic Logic Unit
(ALU)
Lecture 8
L8_CPU_ALU 1
ALU control
• ALU performs all mathematical and logical
operations inside CPU. ALU has:
o Two input data A and B (operands which are the data
being processed),
o One output data R which is the result of the operation,
o Function select ALU Control input which is used to
select the operation that should be performed by the
ALU.
o Flags which are status bits set/reset by ALU to
describe the result of the last operation performed by
ALU.
L8_CPU_ALU 2
ALU control design
• The main control unit issues 2-bit control signal called “ALUOp” to select one ALU Functio
of the following operations: control n
• ALUOp = 00 : Load/Store instruction (Load/Store data from/to data 0000 AND
memory) 0001 OR
• ALUOp = 01 : Branch instruction (Branch is taken if result is zero) 0010 add
• ALUOp = 10 : The register format (R-type instruction) given in the table 0110 subtract
below:
0111 set-on-
• There is a dedicated control unit (ALU Control) issues “ALU control” signal to less-
select the operation that need to be performed by ALU. than
• ALU Control unit receives ALUOp select signal from the main control unit and 1100 NOR
based on it, the ALU Control unit issues 4-bit ALU Control signal that is sent
directly to the ALU to select the operation that should be performed by ALU.
• The 4-bit ALU Control signal are given in the table.
L8_CPU_ALU 3
ALU control design
MUX 1 Main Control
Unit
L8_CPU_ALU
MUX 2
MUX 4
MUX 3
4
ALU control unit design
• In Load/Store instruction, the function F is “add”, because ALU will add
the offset value to the base address to compute the effective address.
• In Branch instruction, the function F is “subtract”, because ALU will
subtract the content of two source registers to check if they are equal
or not by checking the zero flag in order to decide if the branch will be
taken or not.
• In R-type instruction, the function F depends on function field in the
instruction “ISA of R-format”.
L8_CPU_ALU 5
ALU control
opcode ALUOp Operation funct ALU function ALU control
lw 00 load word XXXXXX add 0010
sw 00 store word XXXXXX add 0010
beq 01 branch equal XXXXXX subtract 0110
R-type 10 add 100000 add 0010
subtract 100010 subtract 0110
AND 100100 AND 0000
OR 100101 OR 0001
set-on-less-than 101010 set-on-less-than 0111
L8_CPU_ALU 6
Different ISA formats
There are different ISA formats used for each one of the three operations controlled by
the ALUOp control signal which is generated by the main control unit.
• ALUOp = 00 : Load/Store instruction uses I-format for ISA
Load/
35 or 43 rs rt address
Store
31:26 25:21 20:16 15:0
• ALUOp = 01 : Branch instruction uses I-format for ISA
Branch 4 rs rt address
31:26 25:21 20:16 15:0
• ALUOp = 10 : The register format uses R-format for ISA
R-type 0 rs rt rd shamt funct
31:26 25:21 20:16 15:11
L8_CPU_ALU 10:6 5:0 7
Different ISA formats
• Different control signals derived from instructions
are required.
• For example: In R-format (R-type) and in branch
instruction , the field rt is readable and it is used to
define one source register BUT same field in Load
instruction is used to define the register that will be
used to store the data that comes from memory. This
means, register rt is used to define read register in
some instructions and write register in other
instructions. In other words, there are two paths
(ways) should be connected to Read Register 2 input
in the register file that are used to define rt register
number. To avoid the conflict between the two path,
a 2:1 Mux should be used so always one input is
selected based on the instruction type.
L8_CPU_ALU 8
Different ISA formats
R-type 0 rs rt rd shamt funct
31:26 25:21 20:16 15:11 10:6 5:0
Load/
35 or 43 rs rt address
Store
31:26 25:21 20:16 15:0
Branch 4 rs rt address
31:26 25:21 20:16 15:0
opcode always read, write for sign-extend
read except R-type and add
for load and load
L8_CPU_ALU 9
Datapath With Control
Main Control
Unit
L8_CPU_ALU 10
R-Type Instruction
MUX 1
Main Control
Unit
L8_CPU_ALU
MUX 2
MUX 4
MUX 3
11
Load Instruction
MUX 1
Main Control
Unit
L8_CPU_ALU
MUX 2
MUX 4
MUX 3
12
Branch-on-Equal Instruction
MUX 4
Main Control
Unit
MUX 1
MUX 3
MUX 2
L8_CPU_ALU 13
Implementing Jumps
• Jump uses word (32-bit) address
• Jump instruction update PC with concatenation of
• Top 4 bits of old PC
• 26-bit jump address
• 00
Therefore; the effective address created by “Jump” instruction is:
31 30 29 28 27 …………………… 7 6 5 4 3 2 1 0
4 MSB bits of old PC 26 bits from “jump” ISA 00
31:26 25:0 bit
These two zeros
2 address are inserted by
• Need an extra control signal decoded from opcode shift left 2
operation
L8_CPU_ALU 14
MUX 1 Main Control
Datapath with “Jump”
Unit
L8_CPU_ALU
MUX 2
MUX 4
MUX 5
MUX 3
15
Performance Issues
• Longest delay determines clock period
• Critical path: load instruction
• Instruction memory → register file → ALU → data memory → register file
• Not feasible to vary period for different instructions
• Violates design principle
• Making the common case fast
• We will improve performance by pipelining
L8_CPU_ALU 16