Chapter 4: Memory Management Memory Management Program must be brought (from disk) into memory and placed within a process for it to be run. Main ‘memory and registers are only storage CPU can access directly. Register access in one CPU clock (or less). Main memory can take many cycles. Address binding of instructions and data to memory addresses can happen at three different stages > Compile time: If memory location known a priori, absolute code can be generated; must recompile code if starting location changes Load time: Must generate relocatable code if memory location is not known at compile time v > Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another. Need hardware support for address maps (e.g., base and limit registers) Logical vs. Physical Address Space > An address generated by the CPU is commonly referred to as a logical address, whereas an address seen by the memory unit-that is, the one loaded into the memory address register of the memory-is commonly referred to as a physical addres. > Logical and physical addresses are the same in compile-time and load-time address-binding schemes; logical (virtual) and physical addresses differ in execution-time address-binding scheme. > The run-time mapping from virtual to physical addresses is done by a hardware device called the memory ‘management unit (MMU). The base register is now called a relocation register. ‘The value in the relocation register is added to every address generated by a user process at the time the address is sent to memory. > For example, if the base is at 14000, then an attempt by the user to address location 0 is dynamically relocated to location 14000; an access to location 346 is mapped to location 14346. relocation rege 1000 logical sical addess adtiess cry memo M6 1045 wa Fig: Dynamic relocation using a relocation register Seema, Department of BCA, S R N MN College of Applied Sciences, Shimoga 1Chapter 4: Memory Management Swapping > A process must be in memory to be executed. A process, however, can be swapped temporarily out of memory to a backing store and then brought into memory for continued execution. y A process can be swapped temporarily out of memory to a backing store, and then brought back into ‘memory for continued execution is called swapping. > Backing store — fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images v Roll out, roll in — swapping variant used for priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executed > Major part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swapped y ‘Modified versions of swapping are found on many systems (i.e., UNIX, Linux, and Windows) v System maintains a ready queue of ready-to-run processes which have memory images on disk backing toe swapping of two processes using a disk as a backing store. Contiguous Allocation > Main memory usually into two partitions: ‘© Resident operating system, usually held in low memory with interrupt vector ‘* User processes then held in high memory Memory Mapping and Protection > Relocation registers used to protect user processes from each other, and from changing operating-system code and data ‘+ Base register contains value of smallest physical address ‘+ Limit register contains range of logical addresses ~ each logical address must be less than the limit register ‘| MMU maps logical address dynamically Seema, Department of BCA, S R N MN College of Applied Sciences, Shimoga 2Chapter 4: Memory Management v ‘When the CPU scheduler selects a process for execution, the dispatcher loads the relocation and limit registers with the correct values as part of the context switch, > Because every address generated by a CPU is checked against these registers, we can protect both the ‘operating system and the other users’ programs and data from being modified by this running process. > The relocation-register scheme provides an effective way to allow the operating system's size to change dynamically. __ . _ [retoes ion ] register { i | | logical physical address address { cpu memory = | | trap: addressing error Fig: Hardware support for relocation and limit registers. Memory Allocation > One of the simplest methods for allocating memory is to divide memory into several fixed-sized partitions. Each partition may contain exactly one process. Thus, the degree of multiprogramming is bound by the number of partitions. > In this multi-partition scheme when a partition is free, a process is selected from the input queue and is loaded into the free partition, When the process terminates, the partition becomes available for another process. y In the variable-partition scheme, the operating system keeps a table indicating which parts of memory are available and which are occupied. Initially, all memory is available for user processes and is considered one large block of available memory a hole. A memory contains a set of holes of vatious sizes, v As processes enter the system, they are put into an input queue. The operating system takes into account the memory requirements of each process and the amount of available memory space in determining which processes are allocated memory. v ‘When a process is allocated space, it is loaded into memory, and it can then compete for CPU time. When a Process terminates, it releases its memory which the operating system may then fill with another process from the input queue. Seema, Department of BCA, S R N MN College of Applied Sciences, Shimoga 3Chapter 4: Memory Management > The memory blocks available comprise a set of holes of various sizes scattered throughout memory. When a process arrives and needs memory, the system searches the set for a hole that is large enough for this process. > If the hole is too large, itis split into two parts. One partis allocated to the arriving process; the other is returned to the set of holes. When a process terminates, it releases its block of memory, which is then placed back in the set of holes. > If the new hole is adjacent to other holes, these adjacent holes are merged to form one larger hole. At this point, the system may need to check whether there are processes waiting for memory and whether this newly freed and recombined memory could satisfy the demands of any of these waiting processes. > This procedure is a particular instance of the general Dynamic Storage-Allocat in Problem, which concerns how to satisfy a request of size n from a list of free holes. ‘* First-fit: Allocate the first hole that is big enough. ‘+ Best-fit: Allocate the smallest hole that is big enough; must search entire list, unless ordered by size. Produces the smallest leftover hole. + Worst-fit: Allocate the largest hole; must also search entire list. Produces the largest leftover hole. > First-fit and best-fit better than worst-fit in terms of speed and storage utilization Fragmentation > External Fragmentation — total memory space exists to satisfy a request, but itis not contiguous > Internal Fragmentation — allocated memory may be slightly larger than requested memory; this size difference is memory internal to a partition, but not being used. > One solution to the problem of external fragmentation is Compaction. The goal is to shuffle the memory contents s0 as to place all free memory together in one large block. > Compaction is not always possible, however. If relocation is static and is done at assembly or load time, compaction cannot be done; compaction is possible only if relocation is dynamic and is done at execution time. > If addresses are relocated dynamically, relocation requires only moving the program and data and then changing the base register to reflect the new base address. When compaction is possible, we must determine its cost. > The simplest compaction algorithm is to move all processes toward one end of memory; all holes move in the other direction, producing one large hole of available memory. This scheme can be expensive. > Another possible solution to the external-fragmentation problem is to permit the logical address space of the processes to be non-contiguous, thus allowing a process to be allocated physical memory wherever such memory is available. Paging > Logical address space of a process can be noncontiguous; process is allocated physical memory whenever the latter is available Seema, Department of BCA, S R N MN College of Applied Sciences, Shimoga 4Chapter 4: Memory Management > Keep track of all free frames. > Toruna program of size n pages, need to find n free frames and load program > Set up a page table to translate logical to physical addresses. > Suffers from internal fragmenta Basic Method n. » Divide physical memory into fixed-sized blocks called frames. > Divide logical memory into blocks of same size called pages. physical ) aess 10000 ,., 000 ant. tm Ps physical memory page table Fig: Paging hardware. > Address generated by CPU is divided int: © Page number (p) — used as an index into a page table which contains base address of each page in physical memory Page offset (d) — combined with base address to define the physical memory address that is sent to the ‘memory unit v The page number is used as an index into a page table. > The page table contains the base address of each page in physical memory. This base address is combined ‘with the page offset to define the physical memory address that is sent to the memory unit. (bytes or words) then the v If the size of the logical address space is 2", and a page size is 2” addressing u high-order m- n bits of a logical address designate the page number, and the n low-order bits designate the age offset. Seema, Department of BCA, S R N MN College of Applied Sciences, Shimoga 5Chapter 4: Memory Management Tare page o page | page page 2 a) page 2 ory ‘eee 5 7| page hs Paging Model of Logical and Physical Memory Paging Example > Consider the memory in figure below. Here, in the logical address, bytes and a physical memory of 32 bytes (8 pages). = 2 and m= 4, Using a page size of 4 v Logical address 0 is page 0, offset 0. Indexing into the page table, we find that page 0 is in frame 5. Thus, logical address 0 maps to physical address 20 [= (5 x 4) + 0]. Logical address 3 (page 0, offset 3) maps to physical address 23 [ = (5 x 4) + 3]. Logical address 4 is page 1, offset 0; according. to the page table, page 1 is mapped to frame 6. Thus, logical address 4 maps to physical address 24 [ = (6 x 4) + O]. Logical address 13 maps to physical address 9. > Every logical address is bound by the paging hardware to some physical address, v ‘When we use a paging scheme, we may have some internal fragmenta Fig: 32-byte memory and 4-byte pages > Since the operating system is managing physical memory, it must be aware of the allocation details of physical memory-which frames are allocated, which frames are available, how many total frames there are, and so on. This information is generally kept in a data structure called a frame, Seema, Department of BCA, S R N MN College of Applied Sciences, Shimoga 6Chapter 4: Memory Management > The frame table has one entry for each physical page frame, indicating whether the latter is free or allocated and, if itis allocated, to which page of which process or processes. > When a process arrives in the system to be executed, ts size, expressed in pages, is examined. Each page of the process needs one frame, Thus, if the process requires n pages, at least n frames must be available in ‘memory. > [fn frames are available, they are allocated to this arriving process. The first page of the process is loaded into one of the allocated frames, and the frame number is put in the page table for this process. The next age is loaded into another frame; its frame number is put into the page table, and so on, ioral Teo are ‘4 ‘3 i +3 pace “4 + fpage 8 8 6 6 1” ” 18 1a paged 9 10 20 20 pao a new-prosess page abe 21 a o a) Before Allocation. b) After Allocation: Hardware Support > The hardware implementation of the page table can be done in several ways. In the simplest case, the page table is implemented as a set of dedicated registers, v These registers should be built with very high-speed logic to make the paging-address translation efficient. > The use of registers for the page table is satisfactory if the page table is reasonably small. v For large number of pages, page table is kept in main memory v Page-table base register (PTBR) points to the page table y Page-table length register (PRLR) indicates size of the page table v In this scheme every data/instruction access requires two memory accesses. One for the page table and one for the data/instruction. v ‘The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs) v Some TLBs store adkress-space identifiers (ASIDs) in each TLB entry — uniquely identifies each process to provide address-space protection for that process. Seema, Department of BCA, S R N MN College of Applied Sciences, Shimoga 7Chapter 4: Memory Management v ‘The TLB is used with page tables in the following way. The TLB contains only a few of the page-table entries. When a logical address is generated by the CPU, its page number is presented to the TLB. If the page number is found, its frame number is immediately available and is used to access memory. y The whole task may take less than 10 percent longer than it would used. an unmapped memory reference were > If the page number is not in the TLB (known as a TLB miss) a memory reference to the page table must be made. When the frame number is obtained, we can use it to access memory. v ‘The percentage of times that a particular page number is found in the TLB is called the hit ratio. ager stress pla page tae, phys or Te rf ‘memory — prysial Fig: Paging hardware with TLB For example, let Hit ratio = 80% Access Time = 100 nanosecond TLB Access = 20 nanosecond Then, Bffective Access Time = 0.80 x 120 + 0.20 x 220 = 140 nanoseconds Memory Protection > Memory protection implemented by associating protection bit with each frame > Valid-invalid bit attached to each entry in the page table: © “valid” indicates that the associated page is in the process” logical address space, and is thus a legal page ‘© “invalid” indicates that the page is not in the process” logical address space Seema, Department of BCA, S R N MN College of Applied Sciences, Shimoga 8Chapter 4: Memory Management () or Invalid (i) Bit in a Page Table Shared Pages > Shared code * One copy of read-only (reentrant) code shared among processes (i.e, text editors, compilers, ‘window systems). # Shared code must appear in same location in the logical address space of all processes > Private code and data * Each process keeps a separate copy of the code and data The pages for the private code and data can appear anywhere in the logical address space a we a +f ates ots g af cams i 6] we woz | pio tae ote zi ota 3 ° 2 19 soa | pageuow Fig: Shared Pages Example Segmentation > Memory-management scheme that supports user view of memory > A program is. collection of segments. A segment isa logical unit such as: main program, procedure, function, ‘method, object, local variables, global variables, common block, stack, symbol table, arrays. Seema, Department of BCA, S R N MN College of Applied Sciences, Shimoga 9Chapter 4: Memory Management Fig: User’s View of a Program Basic Method V A logical address space is a collection of segments. Each segment has a name and a length > The addresses specify both the segment name and the offset within the segment, v For simplicity of implementation, segments are numbered and are referred to by a segment number, rather than by a segment name. v Logical address consists of a two tuple, Segment table ~ maps two-dimensional physical addresses; each table entry has: © base — contains the starting physical address where the segments reside in memory. + limit ~ specifies the length of the segment > Segment-table base register (STBR) points to the segment table’s location in memory > Segment-table length register (STLR) indicates number of segments used by a program; segment numbers is legal if s < STLR 1] cru sp: adessing ero: shysial rereny Fig: Segmentation Hardware Seema, Department of BCA, S R N MN College of Applied Sciences, Shimoga 10Chapter 4: Memory Management Example > We have five segments numbered from 0 through 4. The segments are stored in physical memory as shown. The segment table has a separate entry for each segment, giving the beginning address of the segment in physical memory (or base) and the length of that segment (or limit). > For example, segment 2 is 400 bytes long and begins at location 4300. Thus, a reference to byte 53 of segment 2 is mapped onto location 4300 +53= 4353. A reference to segment 3, byte 852, is mapped to 3200 (the base of segment 3) + 852 = 4052. A reference to byte 1222 of segment 0 would result in a trap to the ‘operating system, as this segment is only 1000 bytes long, ae on saree — ‘symbol any wore “toe ae ii=ac—] [ar wom | aris) | main J 2) 40 400 | ref | fen fis ie eo n/m ole = Inia tess space sami op pinsical memo Fig: Example of Segmentation Seema, Department of BCA, S R N MN College of Applied Sciences, Shimoga a