UNIT 3

**1. What is the highest privilege level in a processor’s protection mechanism?**

a) Level 0
b) Level 1
c) Level 2
d) Level 3
**Answer**: a) Level 05†source

**2. Which privilege level is typically assigned to application programs?**

a) Level 0
b) Level 1
c) Level 2
d) Level 3
**Answer**: d) Level 35†source

**3. What does the CPL (Current Privilege Level) represent?**

a) The privilege level requested by the program
b) The privilege level of the segment being accessed
c) The privilege level of the currently executing task
d) The privilege level of the data segment
**Answer**: c) The privilege level of the currently executing task5†source

**4. Which privilege level allows access to data segments from all other privilege levels?**
a) CPL 0
b) CPL 1
c) CPL 2
d) CPL 3
**Answer**: a) CPL 05†source

**5. What is the role of the Requested Privilege Level (RPL)?**

a) It sets the privilege level of the data segment
b) It represents the privilege level of the program requesting access
c) It checks if a task is allowed to access a specific code segment
d) It ensures that only privileged code can access a segment
**Answer**: b) It represents the privilege level of the program requesting access5†source

**6. What happens if the RPL of a selector is greater than the CPL?**
a) The processor generates a General Protection fault
b) The RPL overrides the CPL
c) The task is granted access to the segment
d) The DPL is ignored
**Answer**: b) The RPL overrides the CPL5†source

**7. Which instruction is used to transfer control between privilege levels through a call gate?**
a) MOV
b) JMP
c) CALL
d) RET
**Answer**: c) CALL5†source

**8. What type of exception is generated when a privilege-level violation occurs?**

a) Divide-by-zero exception
b) Stack fault
c) General Protection fault
d) Page fault
**Answer**: c) General Protection fault5†source

**9. What is the main purpose of a call gate?**

a) To transfer data between segments
b) To allow control transfer between different privilege levels
c) To switch between stacks
d) To bypass privilege-level checks
**Answer**: b) To allow control transfer between different privilege levels5†source

**10. What privilege level check must be passed to access a data segment?**
a) DPL = CPL
b) DPL ≥ Max(CPL, RPL)
c) CPL ≥ DPL
d) RPL = CPL
**Answer**: b) DPL ≥ Max(CPL, RPL)5†source

**11. Which privilege level is typically assigned to lower-priority device drivers?**

a) Level 0
b) Level 1
c) Level 2
d) Level 3
**Answer**: c) Level 25†source

**12. What does DPL stand for?**

a) Descriptor Privilege Level
b) Data Privilege Level
c) Device Privilege Level
d) Direct Privilege Level
**Answer**: a) Descriptor Privilege Level5†source

**13. What does the processor do when it detects a privilege-level violation?**

a) It ignores the violation
b) It generates a General Protection fault
c) It resets the program
d) It grants temporary access
**Answer**: b) It generates a General Protection fault5†source

**14. The privilege level of a code segment is checked when control is transferred using which
instruction?**
a) RET
b) JMP
c) CALL
d) Both b and c
**Answer**: d) Both b and c5†source

**15. What are the two least significant bits of a segment selector used for?**
a) To indicate the segment size
b) To indicate the Requested Privilege Level (RPL)
c) To indicate the segment’s offset
d) To indicate the segment’s base address
**Answer**: b) To indicate the Requested Privilege Level (RPL)5†source

**16. What determines whether a processor can access a segment?**

a) CPL only
b) RPL only
c) DPL only
d) CPL, RPL, and DPL
**Answer**: d) CPL, RPL, and DPL5†source

**17. Which of the following instructions can only be executed at privilege level 0 (PL0)?**
a) MOV
b) RDTSC
c) JMP
d) CALL
**Answer**: b) RDTSC5†source

**18. How many privilege levels does the processor segment protection mechanism recognize?**
a) 2
b) 3
c) 4
d) 5
**Answer**: c) 45†source

**19. At which privilege level does the operating system kernel usually run?**
a) Level 0
b) Level 1
c) Level 2
d) Level 3
**Answer**: a) Level 05†source

**20. Which privilege level is assigned to high-priority device drivers and OS services?**
a) Level 0
b) Level 1
c) Level 2
d) Level 3
**Answer**: b) Level 15†source

**21. What happens when an application running at privilege level 3 calls an operating system routine at
level 1?**
a) The CPL changes to 1 temporarily
b) The CPL remains the same
c) A General Protection fault is generated
d) The program is terminated
**Answer**: a) The CPL changes to 1 temporarily5†source

**22. Which of the following segments can a task at CPL 3 access?**

a) A data segment with DPL = 0
b) A data segment with DPL = 1
c) A data segment with DPL = 3
d) Any data segment
**Answer**: c) A data segment with DPL = 35†source

**23. What must be true for a task to load a data segment selector into a segment register?**
a) DPL must be less than CPL
b) DPL must be equal to CPL
c) DPL must be greater than or equal to Max(CPL, RPL)
d) CPL must be greater than DPL
**Answer**: c) DPL must be greater than or equal to Max(CPL, RPL)5†source
**24. Which register stores the Current Privilege Level (CPL)?**
a) CS and SS
b) DS and SS
c) CS and DS
d) ES and FS
**Answer**: a) CS and SS5†source

**25. What is the purpose of the Requested Privilege Level (RPL)?**

a) To lower the privilege level of a task
b) To prevent tasks from accessing segments above their privilege level
c) To ensure that only privileged instructions are executed
d) To verify data access permissions
**Answer**: b) To prevent tasks from accessing segments above their privilege level5†source

**26. When does a processor switch to a more privileged stack?**

a) When calling a non-conforming code segment
b) When calling a conforming code segment
c) When accessing data from a code segment
d) When an application crashes
**Answer**: a) When calling a non-conforming code segment5†source

**27. What is a call gate used for?**

a) To execute privileged instructions
b) To transfer control between different privilege levels
c) To switch between stacks
d) To access hardware devices
**Answer**: b) To transfer control between different privilege levels5†source

**28. Which privilege level allows access to data segments at all privilege levels?**
a) CPL 1
b) CPL 2
c) CPL 3
d) CPL 0
**Answer**: d) CPL 05†source

**29. What happens if an application at CPL 3 tries to access a data segment with DPL 0?**
a) Access is granted
b) Access is denied
c) The program is terminated
d) A warning is issued
**Answer**: b) Access is denied5†source

**30. Which of the following is a privileged instruction?**

a) CALL
b) MOV
c) JMP
d) INVLPG
**Answer**: d) INVLPG5†source

**31. Which level is described as the lowest priority in privilege levels?**

a) Level 0
b) Level 1
c) Level 2
d) Level 3
**Answer**: d) Level 35†source
**32. Which of the following causes a general protection exception (#GP)?**
a) A task violating privilege level while accessing a segment
b) A task executing a HALT instruction
c) A task switching stacks
d) A program using a CALL instruction
**Answer**: a) A task violating privilege level while accessing a segment5†source

**33. What is the primary method of controlling access to code and data segments?**
a) Stack switching
b) Privilege level checking
c) Program termination
d) Code compilation
**Answer**: b) Privilege level checking5†source

**34. What type of code segment allows execution to continue at the current privilege level when
transferred into?**
a) Conforming code segment
b) Non-conforming code segment
c) Data segment
d) Segment register
**Answer**: a) Conforming code segment5†source

**35. In which privilege level are math libraries typically placed?**

a) Level 0
b) Level 1
c) Level 2
d) Level 3
**Answer**: d) Level 35†source

**36. What is the privilege check when accessing a conforming code segment?**
a) CPL = DPL
b) CPL ≥ DPL
c) CPL ≤ DPL
d) RPL ≥ DPL
**Answer**: b) CPL ≥ DPL5†source

**37. What is the main purpose of a General Protection Fault (#GP)?**

a) To detect hardware malfunctions
b) To signal an invalid privilege level access
c) To reset the processor
d) To initiate stack switching
**Answer**: b) To signal an invalid privilege level access5†source

**38. How does the processor switch stacks when transferring to a more privileged level?**
a) Automatically
b) Manually by the user
c) Using the INVLPG instruction
d) Using the JMP instruction
**Answer**: a) Automatically5†source

**39. Which of the following can override the CPL during access checks?**
a) DPL
b) RPL
c) Segment selector
d) Task descriptor
**Answer**: b) RPL5†source

**40. In which instruction is the current privilege level (CPL) stored?**

a) JMP
b) MOV
c) RET
d) CALL
**Answer**: b) MOV5†source
-------------------------------------------------------------------------------------------------------
UNIT 5

**1. How many segments are used in a 7-segment display to show digits?**
a) 5
b) 6
c) 7
d) 8
Answer**: c) 713†source

**2. Which segment of a 7-segment display is responsible for displaying the decimal point?**
a) Segment A
b) Segment G
c) Segment D
d) Segment DP
Answer**: d) Segment DP13†source

**3. In a common anode 7-segment display, the LEDs that are lit are connected to which voltage level?**

a) Ground (0V)
b) +5V
c) +3.3V
d) No voltage
Answer**: a) Ground (0V)13†source

**4. What is the bit pattern for displaying the digit ’0’ in a common anode 7-segment display?**
a) F9H
b) C0H
c) 92H
d) A4H
Answer**: b) C0H13†source

**5. What is the purpose of a look-up table in a 7-segment display?**

a) To store different voltage levels
b) To store bit patterns for different digits
c) To manage brightness levels
d) To handle color selection
Answer**: b) To store bit patterns for different digits13†source

**6. In a 7-segment display, which segment is turned off when displaying the number ’1’?**
a) Segment A
b) Segment B
c) Segment C
d) Segment G
Answer**: d) Segment G13†source
**7. What does the instruction ‘MOV P1, A‘ do in the context of controlling a 7-segment display?**
a) It moves data to the display segments.
b) It turns off all segments.
c) It controls brightness.
d) It clears the display.
Answer**: a) It moves data to the display segments13†source

**8. In a common anode display, how do you turn off an LED segment?**
a) Set it to 1
b) Set it to 0
c) Ground the segment
d) Connect it to a power source
Answer**: a) Set it to 113†source

**9. To display the digit ’8’ on a common anode 7-segment display, what is the bit pattern?**
a) 80H
b) 82H
c) 90H
d) 0F9H
Answer**: a) 80H13†source

**10. What happens when the data ‘MOVC A, @A+DPTR‘ is executed in a 7-segment display program?**

a) It lights up specific segments.

b) It clears the display.
c) It reads data from the look-up table.
d) It turns off all segments.
Answer**: c) It reads data from the look-up table13†source

**11. What is the primary difference between common anode and common cathode 7-segment
displays?**
a) The number of segments used
b) The polarity of the LED connections
c) The type of digits they can display
d) The brightness levels
Answer**: b) The polarity of the LED connections13†source

**12. In a common anode display, to display the digit ’1’, which bit pattern should be used?**
a) F9H
b) C0H
c) 80H
d) A4H
Answer**: a) F9H13†source

**13. Which of the following operations would be used to increase the value of a digit on a 7-segment
display?**
a) INC A
b) MOV P1, A
c) RET
d) CLR A
Answer**: a) INC A13†source

**14. What kind of microcontroller register is often used to output data to a 7-segment display?**
a) Data pointer (DPTR)
b) Program counter (PC)
c) Accumulator (A)
d) Stack pointer (SP)
Answer**: c) Accumulator (A)13†source

**15. In a 7-segment display, which segments are turned on to display the number ’4’?**
a) A, B, C, F
b) B, C, F, G
c) A, F, G, E
d) A, B, G, D
Answer**: b) B, C, F, G13†source

### **4x4 Matrix Keyboard:**

**16. How many rows and columns are in a 4x4 matrix keyboard?**
a) 3 rows and 4 columns
b) 4 rows and 4 columns
c) 5 rows and 4 columns
d) 4 rows and 5 columns
Answer**: b) 4 rows and 4 columns13†source

**17. How many keys are there in a 4x4 matrix keyboard?**

a) 8
b) 12
c) 16
d) 24
Answer**: c) 1613†source

**18. In a 4x4 matrix keyboard, which microcontroller ports are typically connected to the rows and
columns?**
a) P0 and P1
b) P2 and P3
c) P1 and P2
d) P0 and P2
Answer**: c) P1 and P213†source

**19. What technique is used to detect a key press in a 4x4 matrix keyboard?**
a) Scanning rows and columns
b) Interrupt handling
c) Polling
d) Both a and c
Answer**: d) Both a and c13†source

**20. In a matrix keyboard, what does the microcontroller do when a key is pressed?**
a) It sends a reset signal.
b) It reads the key code directly.
c) It checks the voltage level of the corresponding row and column.
d) It turns off the display.
Answer**: c) It checks the voltage level of the corresponding row and column13†source

**21. What is the benefit of using a matrix configuration for keyboards?**

a) Fewer microcontroller pins are required
b) Faster response time
c) Lower power consumption
d) Easier to program
Answer**: a) Fewer microcontroller pins are required13†source
**22. How does the microcontroller identify the pressed key in a matrix keyboard?**
a) By measuring current
b) By detecting the row and column intersection
c) By scanning the columns only
d) By sending a signal to all rows
Answer**: b) By detecting the row and column intersection13†source

**23. What is the main purpose of pull-up resistors in a 4x4 matrix keyboard?**
a) To limit the current
b) To hold the lines at a known state when no key is pressed
c) To increase voltage
d) To generate key codes
Answer**: b) To hold the lines at a known state when no key is pressed13†source

**24. How does a microcontroller begin scanning a 4x4 matrix keyboard?**

a) It scans rows one by one
b) It sends data to the columns
c) It starts with scanning columns and detecting rows
d) It resets the display
Answer**: a) It scans rows one by one13†source

**25. What happens when two keys are pressed simultaneously on a 4x4 matrix keyboard?**
a) Both keys are detected
b) Neither key is detected
c) The microcontroller detects a ghosting effect
d) The display turns off
Answer**: c) The microcontroller detects a ghosting effect13†source

**26. What is the purpose of debouncing in a matrix keyboard?**

a) To reduce power consumption
b) To prevent multiple false key detections
c) To speed up key detection
d) To scan more keys
Answer**: b) To prevent multiple false key detections13†source

**27. How does the microcontroller handle multiple key presses in a 4x4 matrix keyboard?**
a) It disables all keys
b) It uses an interrupt handler
c) It scans for the first key press
d) It generates key codes for all pressed keys
Answer**: c) It scans for the first key press13†source

**28. Which microcontroller port is commonly used for interfacing a 4x4 matrix keyboard?**
a) P0
b) P1
c) P2
d) P3
Answer**: b) P113†source

**29. How does the

microcontroller differentiate between key presses in different rows of the matrix keyboard?**
a) By checking the current level
b) By checking the voltage across rows
c) By scanning rows and detecting active columns
d) By measuring temperature
Answer**: c) By scanning rows and detecting active columns13†source

**30. What is the typical method to interface a 4x4 matrix keyboard to a microcontroller?**
a) Using ADC
b) Scanning the rows and columns via GPIO pins
c) Using UART communication
d) Direct memory access
Answer**: b) Scanning the rows and columns via GPIO pins13†source