Topic 5

An Interleaved PFC Preregulator for

High-Power Converters
 An Interleaving PFC Pre-Regulator
for High-Power Converters
Michael O’Loughlin, Texas Instruments

ABSTRACT
In higher power applications, to fully utilize the line, power factor correction (PFC) is a necessity.
Passive solutions were developed first, which required bulky inductors and capacitors. To reduce the
volume of these bulky solutions active PFC using a boost topology was developed. The active solutions
had higher power densities than the passive solutions. Interleaving PFC pre-regulators is the next step
in increasing PFC pre-regulator power densities, reducing the overall volume of the design.
Interleaving will reduce magnetic volume and has the added benefit of reducing RMS current in the
boost capacitor. This topic will evaluate the benefits of interleaving PFC pre-regulators.

I. SINGLE STAGE BOOST CONVERTER REVIEW the converter’s input and will require filtering to
meet EMI specifications. The diode output
In PFC pre-regulators, the most popular
current (I1) is discontinues and needs to be
topology used is a boost converter. This is
filtered out by the output capacitor (COUT). In this
because boost converters can have continuous
input current that can be manipulated with topology, the output capacitor ripple current
average current mode control techniques to force (ICOUT) is very high and is the difference between
input current to track changes in line voltage. I1 and the dc output current ( IOUT).
Fig. 1 shows a traditional single stage boost. The
inductor ripple current (∆IL1) is directly seen at
IIN L1 IOUT
I1

VIN

ICOUT COUT RLOAD

S1

ON
S1

OFF IIN

∆IL1

I
1

ICOUT = I1 - IOUT
0A

Fig. 1. Traditional boost stage.

5-1
 II. BENEFITS OF TWO PHASE INTERLEAVING IIN L1
I1
IOUT

BOOST CONVERTERS VIN

Fig. 2 shows the functional diagram of a two S1

ICOUT COUT RLOAD

phase interleaved boost converter. The

interleaved boost converter is simply two boost L2
converters in parallel operating 180° out of I2

phase. The input current is the sum of the two

inductor currents IL1 and IL2. Because the S2
inductor’s ripple currents are out of phase, they
tend to cancel each other and reduce the input
ripple current caused by the boost inductors. ON

The best input inductor ripple current S1

cancellation occurs at 50 percent duty cycle. OFF
The output capacitor current is the sum of the ON

two diode currents (I1 + I2) less the dc output S2

current. Interleaving reduces the output OFF

capacitor ripple current ( IOUT) as a function of

∆IL1
duty cycle. As the duty cycle approaches 0
percent, 50 percent and 100 percent duty cycle, IIN/2

the sum of the two diode currents approaches ∆IL1

dc. At these points, the output capacitor only has IIN = IL1 + IL2
to filter the inductor ripple current.
I1

I2

0A

ICOUT = (I1 + I2) - IOUT

Fig. 2. Interleaved boost stage.

5-2
III. INPUT RIPPLE CURRENT REDUCTION AS A In PFC pre-regulators the duty cycle (D(θ))
FUNCTION OF DUTY CYCLE is not constant and will varies with changes in
line phase angle (θ) and input voltage (VIN(θ) ).
The following equations show how the ratio
The amount of duty cycle variation for universal
of input ripple current to the inductor ripple
applications can be quite large. This variation in
current (K(D)) vary with changes in duty cycle.
duty cycle can be observed by evaluating a
Fig. 3 shows how K(D) varies with changes in
converter that was designed for a universal input
duty cycle.
of 85 V to 265 V RMS with a regulated 385 V
ΔI IN dc output. At low line the duty cycle (D1(θ))
K(D) =
ΔI L 1 will vary from 100% to 69% and at high line the
duty cycle (D2(θ)) will vary from 100% down
1 − 2D to 2%. The inductor ripple current cancellation
K(D) = if D ≤ 0.5 will not be 100% throughout the line cycle.
1− D
However, it is good enough to drastically reduce
2D - 1 the input ripple current for a given inductance.
K(D) = if D > 0.5 The highest ripple current in this example would
D occur at the peak of low line with a duty cycle
1.0 of 69%. The input ripple current at this duty
cycle will be 55% of the individual inductor
0.9
ripple current. When the converter is operating
0.8 at 2% and 100% duty cycle there is very little
0.7 inductor ripple current cancellation. However, at
these duty cycles the interleaved PFC pre-
K(D) = ∆IIN/∆IL1

0.6
regulator has very little inductor ripple current.
0.5 Overall, the input ripple current of the PFC
0.4 boost will be 55% of what it would have been in
a single phase PFC designed for the same power
0.3
level and inductance. This can be found by
0.2 evaluating Fig. 3.
0.1
V IN (θ ) = VIN(rms) × 2 sin (θ )
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
VOUT − V IN (θ )
D - Duty Cycle D(θ ) =
VOUT
Fig. 3. Input ripple current reduction.

5-3
 1.0 The reduction in energy storage does not
0.9
directly translate into magnetic volume
reduction. A designer could expect to see up to a
0.8
D1(θ) 25% reduction in magnetic volume going from a
0.7 single phase PFC pre-regulator to a dual phase
interleaved PFC. This will be discussed later in
D - Duty Cycle

0.6
the paper with actual design examples.
0.5 Interleaving PFC pre-regulators if done in
0.4 this fashion will not increase the size of the EMI
filter. A common design practice is to select the
0.3
switching frequency of the power converter
0.2
below the EMI lower limit of 150 kHz. The
0.1 D2(θ) second harmonic of switching frequency would
0.0
be twice the fundamental and will most likely be
0 30 60 90 120 150 180
in the EMI band and would need to be filtered to
Phase Angle - O meet specifications. Interleaving two pre-
regulators will cause the input to see a switching
Fig. 4. Duty cycle variation in universal PFC frequency that is twice the switching frequency
pre-regulator. of a single phase. This means the fundamental
switching frequency of the converter will most
IV. INPUT RIPPLE CURRENT CANCELLATION likely be pushed into the EMI band and will be
CAN REDUCE BOOST MAGNETIC VOLUME at the second harmonic of an individual stage’s
The inductor ripple current cancellation switching frequency. However, the input ripple
allows the designer to reduce boost inductor current at this frequency will be reduced by a
magnetic volume. This is due to the energy factor of two. This should not put any additional
storage requirement of the two interleaved constraints on the EMI filter.
inductors being half that of single stage pre-
regulator designed for the same power level,
switching frequency and inductance.
Single stage inductor energy (ESingle):

1 2
E SINGLE = LI
2

Two phase total inductor energy (EInterleaved):

2 2
1 ⎛I⎞ 1 ⎛I⎞ 1
E INTERLEAVED = L⎜ ⎟ + L⎜ ⎟ = LI 2
2 ⎝2⎠ 2 ⎝2⎠ 4

5-4
 V. THE EMI FILTER CAN ALSO BE REDUCED VI. OUTPUT CAPACITOR RIPPLE CURRENT
Depending on the design parameters just REDUCTIONS AS A FUNCTION OF DUTY CYCLE
interleaving PFC pre-regulators could reduce Interleaving PFC pre-regulator stages has
the size of the EMI filter. For example in the added benefit of reducing the output
European designs and boost follower capacitor RMS current. Fig. 5 shows the
applications where the boost voltage is just normalized output capacitor RMS current in a
above the peak of the input line voltage the single stage boost (ICOUT1(D)) and in a two stage
highest inductor ripple current occurs at 50% interleaved boost converter (ICOUT2(D)) as a
duty cycle. From the graph in Fig. 3 it can be function of duty cycle. Knowing that the duty
observed when the converter is operating at cycle in universal PFC pre-regulator
50% duty cycle the inductor ripple currents applications varies from 100% to 2% and
would cancel each other out. In this case the studying Fig. 5 it can be observed that
EMI filter would be drastically reduced just by interleaving will drastically reduce output
interleaving. capacitor RMS current. In this example the
The designer also has the option of running RMS current would be cut in half. This
the interleaved pre-regulator at a lower reduction in RMS current will reduce electrical
switching frequency and increase the boost stress in the output capacitor and improve the
inductance slightly to reduce input ripple converter’s reliability.
current. If this is done correctly the designer
I C OUT1 (D) = (1 − D) × (1 − D )
2
could decrease the size of the EMI filter without
increasing the size of the boost inductor volume
compared to a single stage pre-regulator 1
(1 − 2D) × (1 − 2D ) if D ≤ 0.5
2
I C OUT2 (D) =
approach. The designer may be able to reduce 2
both the EMI filter; as well as, the boost
inductor if the converter’s switching frequency 1
(2 − 2D) × (2 − 2D ) if D > 0.5
2
is not reduced too much. I C OUT12 (D) =
2
0.60
Single Stage ICOUT1(D)
0.54 RMS Current
ICOUT - Output Capacitor Current - A

0.48

0.42

0.36
Interleaved ICOUT2(D)
0.30 RMS Current

0.24

0.18

0.12

0.06

0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
D - Duty Cycle - C

Fig. 5. Normalized output capacitor RMS

currents as a function of D.

5-5
 VII. 350-W, TWO PHASE INTERLEAVE PFC VIII. LAB RESULTS
PROTOTYPE The largest inductor ripple current occurs
To evaluate some of the benefits of when the converter operates at low line input at
interleaving a 350-W two phase interleaved PFC the peak of line. The oscilloscope plot in Fig. 7
pre-regulator was constructed. This prototype shows the inductor ripple current cancellation at
was designed for a universal input of 85 V to the peak of line when the input is 85 VRMS. CH1
265 V RMS. The boost output voltage (VOUT) is L1 inductor current, CH2 is L2 inductor
for the design was 385 VDC. The circuit was current. M1 is the input current which is the sum
designed for a switching frequency (fS) of of inductor currents L1 and L2. The current
100 kHz to limit switching losses. The prototype probes were set with 2 A/Div. ratio. From this
used 600-μH inductors for L1 and L2. The plot it can observed that the input ripple current
output capacitor (COUT) needed for the design is 55% of the individual inductor current. The
was a 220-μF electrolytic capacitor. A reduction in input ripple current agrees with the
functional schematic of the circuit is presented graph of Fig. 3 for 69% duty cycle.
in Fig. 6.
Input Current IIN

IL2

M1

IL1
CH2

CH1

Fig. 7. Inductor ripple current, POUT = 350 W.

VLINE
L1
D1

VOUT
Q1
COUT

L2
D2

UCC28220
UCC28528 PFC Interleaved
Controller PWM Q2
Controller

Fig. 6. Dual interleaved PFC.

5-6
 Figs. 8 and 9 show the input and inductor
ripple currents at maximum load at minimum
and maximum line voltage. CH1 and CH2 are Input Current IIN

inductor current L1 and L2. M1 is the input

current to the converter and is the sum of L1 and M1
L2. The current probe was set with 2 A/Div.
IL2
ratio. From these waveforms, it can be observed
that high frequency input ripple current is much CH2
less than the individual phase’s boost inductor IL1
current. If this was a single stage topology the
full inductor ripple current would be seen at the CH1
input of the converter.

Input Current IIN

Fig. 9. Input current at VIN = 265 V, 2 A/Div.
The following equations was used to
IL2 calculate the highest RMS current in the output
capacitor. The highest ripple current occurs at
M1
the minimum input (VIN(min)) of 85 V RMS. The
calculation is based on half a line cycle of the
CH2
IL1
50 Hz line (fLINE). The duty cycle of each boost
stage (D1(t)) at low line varies from 100% to
69%. The estimated output capacitor RMS
current (ICOUT(rms)) was 1 A.
CH1
fS
Iterations =
Fig. 8. Input current at VIN = 85 V, 2 A/Div. 2 × f LINE

1
2 × f LINE
Step =
Iterations

POUT × 2
I IN (t) = × sin(ω × t )
VIN(min)

The RMS current in the boost capacitor was

measured at 1 A, which is less than half of what
it would be in a single stage PFC pre-regulator
with the same power requirements.

Iterations
1
∑ I IN (n × Step ) × (2 − 2D1(ω × n × Step)) × (2 − 2D1(ω × n × Step))
2 2

2
I Cout_rms = n =1
≈1A
Iterations

5-7
 IX. EVALUATE INDUCTOR RIPPLE CURRENT Four phase input current to inductor current
CANCELLATION IN THREE AND FOUR PHASE ratio as a function of D (K4(D)):
INTERLEAVED PFC PRE-REGULATORS
1− 4× D 1
The following equations and the graph in if D ≤
1− D 4
Fig. 10 show how the ratio of input ripple 1 − 6 × D + 8× D2 +1 1 2
current to inductor ripple current vary with × if <D<
k 4( D ) =
2 (− 1 + D ) × D 4 4
changes in duty cycle for two, three and four
1 − 10 × D + 8 × D + 3
2
2 3
phase interleaved PFC pre-regulators. Note × if <D<
these equations are based on the boost 2 (− 1 + D ) × D 4 4
converters operating in continues conduction 4× D − 3 3
if D ≥
mode (CCM). D 4
Two phase input current to inductor current
ratio as a function of D (K2(D)):
1.0
1 − 2D 1
if D ≤ 0.9
k 2( D ) = 1 − 21×−(1D− D ) 2 K2(D)

1 0.8
if D >
1 − (1 − D ) 2 0.7 K3(D)

Three phase input current to inductor current 0.6

∆IIN/∆IL1
ratio as a function of D (K3(D)): 0.5

1 − 3D 1 0.4
if D ≤
1− D 3 0.3
1 − 9× D + 9× D2 + 2 1 2
k 3( D ) = × if < D < 0.2
3 (− 1 + D ) × D 3 3
3× D − 2
0.1 K4(D)
2
if D ≥
D 3 0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
D - Duty Cycle

Fig. 10. Ratio of input ripple current/inductor

ripple vs. duty cycle (D).

5-8
 X. THE TOTAL INDUCTOR ENERGY IS In the following equations that calculate
REDUCED FOR EACH ADDITIONAL PHASE energy and energy reduction n represents the
For each additional interleaved phase added total number of interleaved phases in the pre-
will reduce the total inductor energy required by regulator.
the design, when compared to a single stage Total multiple phase inductor energy
PFC pre-regulator and a n phase interleaved pre- (EInterleaved(n)).
regulator. The graph in Fig. 11 shows the n
1 ⎛I⎞
2

percent reduction in total inductor energy E Interleaved ( n ) = ∑ L⎜ ⎟

k =1 2 ⎝ n ⎠
(%_Energy_Reduction) required in the design
going from a single phase boost to 4 phase
⎛ 2
⎞
⎜ 1 - ∑ ⎛⎜ 1 ⎞⎟
n
interleaved pre-regulator. From this graph it can ⎟
be observed that the total energy going from a ⎜ ⎟
%_Energy_Reduction(n) = ⎜ k =1 ⎝ ⎠
n
single phase to a two phase interleaved power 1 ⎟ × 100
converter will be reduced by 50%. A three ⎜ ⎟
⎜ ⎟
phase interleaved pre-regulator will take ⎝ ⎠
roughly 67% less total inductor energy
compared to a single phase approach. A four 100

phase interleaved PFC pre-regulator will reduce 90

the total inductor energy required by the design
80
by 75%. Interleaving reduces the total energy
required by the design which will allow the total Energy Reduction - % 70
boost inductor volume to be reduced. However, 60
there is not an easy mathematical calculation to
50
show the reduction in boost magnetic volume by
interleaving. The reduction in magnetic volume 40
will vary depending on the magnetic cores that 30
are selected. The best way to evaluate the
reduction in boost magnetic volume is by going 20

through a theoretical design using similar 10

magnetic cores. 0
1 2 3 4
Interleaved Phase - n

Fig. 11. Percent of total inductor energy

reduction.

5-9
 XI. MAGNETIC VOLUME REDUCTION To do a true comparison of inductor volume
To show how interleaving PFC pre- reduction required using the same magnetic core
regulators can reduce magnetic volume a type. One of the more efficient core sets to wind
theoretical design of boost inductors was is an EE core set. For this example EE cores
conducted for a universal 500-W PFC pre- from Mag-Inc were selected for the individual
regulator for a single phase to a four phase PFC designs. Fig. 12 shows the mechanical drawing
pre-regulator. The output of the converters was of the EE cores used for this example.
set at 385 V. The inductance (L) was chosen B C
based on the inductance for a four phase design.
This would ensure the inductance would work L
for 1- through 4-phase interleaved PFC
applications. Also the amount of boost inductor
ripple chosen was small enough that the ac A F E
portion of the inductor ripple current would be
negligible. The following equations were used M
to select the area products required for the
inductors for the four different designs. In the
following equations n represents the number of
interleaved phases in the pre-regulators. D

Fig. 12. Mechanical drawing of Mag-Inc EE

POUT(max) × 2
I PEAK = , peak input current core.
VIN(min)
The estimated volume of the boost inductor
(VINDUCTOR) will be based on magnetic core
VOUT (VCORE) volume and exposed copper winding
× 0.5
L= 2 volume (VCOPPER.) This evaluation will not take
I PEAK into account bobbin size and was also based on
× 0.3 × 100 kHz
4 dimension B of the E core being trimmed to get
the area product as close to calculated as
∆B = 0.2 T, change in flux density possible.
VCORE = A × (2 × B ) × C
3.95 × 10 6 A
Cd = , current density
m2
VCOPPER = 2 × (2 × D × M ) × ( A − 2 × L )
Ku = 0.4, winding factor
VINDUCTOR = VCORE + VCOPPER
I PEAK
L×
WaAc( n ) = n × I RMS
ΔB Ku × Cd

I PEAK I PEAK
L×
WaAc( n ) = n × n× 2
ΔB Ku × Cd

5-10
 To show the reduction in boost inductor XII. EMI FILTER REDUCTION FOR 3RD AND 4TH
volume Table I. was constructed for a single PHASE
phase through a four phase interleaved PFC pre- Form Fig. 10 it can be observed that the
regulator. The following equation was used to three phase inductor ripple current is completely
calculate the reduction in total inductor cancelled at 33% and 66% duty cycle. In
magnetic volume (% Reduction in Inductor universal designs a three phase system would
Volume) as compared to a single phase PFC reduce the size of the EMI filter. This is because
inductor. VINDUCTOR (1) is the volume of a the inductor ripple current in a universal design
tradition single phase pre-regulators boost is at its maximum at the peak of low line which
inductor. Variable VINDUCTOR(n) is the volume has a duty cycle around 69%. At this point the
of a single inductor in a multiphase boost pre- input ripple current would be 10% of the
regulator where n is the total number of phases inductor ripple current. The reduction in input
in the pre-regulator used in the reduction ripple current should result in a reduction of the
comparison. This exercise showed that the size of the EMI filter.
reduction in total magnetic volume was much The four phase system has almost no ripple
less than the total energy reduction that was current when the converter is operating at 25%,
calculated previously. However, interleaving 50%, 75% duty cycle. In European and boost
reduced the magnetic volume by 32% to 51% follower pre-regulators interleaving with four
depending on the number of phases that were phases will also reduce the size of the EMI filter
used in the design. just by interleaving. This is due to the maximum
inductor ripple that occurs at 50% duty cycle
being 100% cancelled at the input of the
converter. Also the 4-phase inductor ripple
current cancellation curves show that overall
input ripple current should be much less than a
two phase interleaved converter for these
applications.

⎛V (1) − n × VINDUCTOR ( n ) ⎞
% reduction in inductor volume = ⎜⎜ INDUCTOR ⎟⎟ × 100
⎝ VINDUCTOR (1) ⎠
TABLE I. BOOST INDUCTOR MAGNETIC VOLUME REDUCTION
Mag-Inc. % Reduction
VINDUCTOR
WaAc EE Core A B C D E F L M AC In Inductor
(h)
Set Volume
Units cm4 mm mm mm mm mm mm mm mm cm2 cm3 %
# of
Phases
1 23.228 48020-EC 80.00 24.862 19.80 14.962 59.30 19.80 9.90 19.80 3.920 150.099 0
2 5.807 45528-EC 54.90 16.941 20.60 7.841 37.50 16.80 8.38 10.70 3.461 51.118 32
3 2.581 44020-EC 42.80 13.481 15.40 7.381 30.40 11.90 5.94 9.54 1.833 26.480 47
4 1.452 44016-EC 42.80 13.204 9.00 7.104 30.40 11.90 5.94 9.54 1.071 18.554 51

5-11
 XIII. OUTPUT CAPACITOR RIPPLE CURRENT ICOUT4(D) is the normalized output capacitor
CANCELLATION IN THREE AND FOUR PHASE RMS current as a function of D.
INTERLEAVED PFC PRE-REGULATORS
Each individual added phase will continue to 1 1
(1 − 4 D ) − (1 − 4 D )2 if D ≤
reduce the RMS current in the boost capacitor. 4 4
1 1 2
However, the amount of reduction decreases (2 − 4 D ) − (2 − 4 D )2 <D<
if
with each additional phase. Please refer to I COUT4 (D) = 4 4 4
1
Fig. 13 for a normalized output capacitor RMS (3 − 4 D ) − (3 − 4 D )2 if 2 < D < 3
current for a single phase boost through 4 phase 4 4 4
1
interleaved boost converter. (4 − 4 D ) − (4 − 4 D ) if D ≥ 3
2

4 4
The equations below gives the normalized
output capacitor RMS current (ICOUT1(D))
0.50
converter in a single stage PFC pre-regulator as
a function of duty cycle (D). 0.45

ICOUT1(D) is the normalized output capacitor 0.40 ICOUT1(D)

RMS current as a function of D.

ICOUT - Output Current - A

0.35 ICOUT2(D)

0.30
I COUT 1 ( D ) = 1 (1 − D ) − (1 − D )
2

0.25 ICOUT4(D)

ICOUT2(D) is the normalized output capacitor 0.20 ICOUT3(D)

RMS current as a function of D. 0.15

0.10
1
(1 − 2 D ) − (1 − 2 D ) if D < 1
2

I COUT2 (D) = 2 2 0.05

1
(2 − 2 D ) − (2 − 2 D ) if D ≥ 1
2 0.00
2 2 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
D - Duty Cycle - %
ICOUT3(D) is the normalized output capacitor
RMS current as a function of D. Fig. 13. Output capacitor RMS current.

1 1
(1 − 2 D ) − (1 − 3D )2 if D ≤
3 3
1 1 2
I COUT3 (D) = (2 − 2 D ) − (2 − 3D )2 if <D<
3 3 3
1 2
(3 − 2 D ) − (3 − 3D )2 if D ≥
3 3

5-12
 XIV. EFFICIENCY The 350-W prototype had greater than 91%
Interleaving and paralleling power efficiency over line and load.
converters can increase the efficiency of the 97

power converter; as long as, the inductor ripple 96

currents are kept within reason. The
semiconductor switching losses will remain 95 VIN = 265 V

roughly the same. The I2R losses should be

reduced with each additional phase. However, if 94

Efficiency - %
the inductor currents have excessive inductor 93
ripple the higher RMS currents will cause
greater conduction losses driving down 92 VIN = 85 V
efficiency. Also at lower power levels where the
switching losses dominate interleaving will not 91

show a drastic improvement in efficiency.

90

Single phase conduction losses: 89

20 30 40 50 60 70 80 90 100

PSINGLE = I R
2 VOUT - Output Power - %

Fig. 14. Prototype efficiency.

Two phase conduction losses:
2 2
⎛I⎞ ⎛I⎞ I2
P2_PHASE = ⎜ ⎟ R + ⎜ ⎟ R = R
⎝2⎠ ⎝2⎠ 2

Three phase conduction losses:

2 2 2
⎛I⎞ ⎛I⎞ ⎛I⎞ I2
P3_PHASE =⎜ ⎟ R+⎜ ⎟ R+⎜ ⎟ R= R
⎝3⎠ ⎝3⎠ ⎝3⎠ 3

Four phase conduction losses:

2 2 2 2
⎛I⎞ ⎛I⎞ ⎛I⎞ ⎛I⎞ I2
P4_PHASE = ⎜ ⎟ R + ⎜ ⎟ R + ⎜ ⎟ R + ⎜ ⎟ R = R
⎝4⎠ ⎝4⎠ ⎝4⎠ ⎝4⎠ 4

5-13
 XV. CONCLUSION REFERENCES
Interleaving PFC pre-regulators has many [1] Lazlo Balogh and Richard Redi, “Power
benefits. It can reduce EMI and boost inductor
Factor Correction with Interleaved
magnetic volume. The amount of reduction Boost,” APEC 1993, pp. 168-174
varies and depends on the design requirements
and design tradeoffs. The designer may choose [2] Lloyd Dixon, “High Power Factor
to reduce either the boost inductor magnetic Switching Pre-regulator Design
volume or cut back the switching frequency to Optimization,” Unitrode Power Supply
reduce the size of the EMI filter. In some cases Design Seminar SEM-700, 1990, Topic 7
just adding an additional phase will reduce the [3] Brett Miwa, David Otten, Martin F.
size of the EMI filter. Interleaving also reduces Schlecht, “High Efficiency Power Factor
the RMS current in the boost capacitor greatly Correction Using Interleaved Techniques”
reducing electrical over stress on the capacitor. IEEE 1992, pp. 557 to 568
However, the complexity and cost of the design
will increase with each additional phase. [4] Michael O’Loughlin, “350W, Two Phase
Interleaved PFC Pre-regulator Design
XVI. ACKNOWLEDGEMENTS Review,” Texas Instrument Literature
Number SLUA369, 2006
I would like to thank Isaac Cohen for his
contributions to this article. His consolation and [5] Michael O’Loughlin,“HPA117 350W
advice greatly contributed to the quality of this Interleaved PFC Pre-Regulator User’s
seminar paper. Guide,” TI Literature Number SLUU228,
2005
[6] Brian Shafer, “Interleaving Contributes
Unique Benefits to Forward Converters
and Flyback Converters,” Texas
Instrument Power Supply Design Seminar,
Topic 4, SEM 1600, 2004
[7] P. Zumel, O. Garcia, J. A. Cobos, J.
Uceda, “EMI Reduction by Interleaving of
Power Converters Presentation,” APEC
2004
[8] “UCC28220/1 Dual Interleave PWM
Controller,” Data Sheet, Instruments
Literature Number SLUS544, September
2003
[9] “UCC28521/8 Advanced PFC/PWM
Controller Data Sheet,” Texas Instruments
Literature Number SLUS608

5-14