dsPIC33CK256MP508 FAMILY
21.0 TIMER1 If Timer1 is used for SCCP, the timer should be running
in Synchronous mode.
Note 1: This data sheet summarizes the features The Timer1 module can operate in one of the following
of the dsPIC33CK256MP508 family of modes:
devices. It is not intended to be a compre-
hensive reference source. To complement • Timer mode
the information in this data sheet, refer to • Gated Timer mode
“Timer1 Module” ([Link]/ • Synchronous Counter mode
DS70005279) in the “dsPIC33/PIC24 • Asynchronous Counter mode
Family Reference Manual”. A block diagram of Timer1 is shown in Figure 21-1.
The Timer1 module is a 16-bit timer that can operate as
a free-running interval timer/counter.
The Timer1 module has the following unique features
over other timers:
• Can be Operated in Asynchronous Counter mode
• Asynchronous Timer
• Operational during CPU Sleep mode
• Software Selectable Prescalers 1:1, 1:8, 1:64
and 1:256
• External Clock Selection Control
• The Timer1 External Clock Input (T1CK) can
Optionally be Synchronized to the Internal Device
Clock and the Clock Synchronization is Performed
after the Prescaler
FIGURE 21-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM
TECS[1:0]
TGATE
TCS
T1CK
(External
Clock)
0 TCY 00
TCY T1CK
1 01
TGATE
Sync 0 tmr_clk
Prescaler TMRx
FOSC
2 10
1 2
FRC
3 11 Comparator 0
TCKPS[1:0]
Timer
1 Interrupt
PRx
T1CK
2017-2022 Microchip Technology Inc. and its subsidiaries DS70005349K-page 437
dsPIC33CK256MP508 FAMILY
21.1 Timer1 Control Register
REGISTER 21-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0
TON(1) — SIDL TMWDIS TMWIP PRWIP TECS1 TECS0
bit 15 bit 8
R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0
TGATE — TCKPS1 TCKPS0 — TSYNC(1) TCS(1) —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 TON: Timer1 On bit(1)
1 = Starts 16-bit Timer1
0 = Stops 16-bit Timer1
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Timer1 Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12 TMWDIS: Asynchronous Timer1 Write Disable bit
1 = Timer writes are ignored while a posted write to TMR1 or PR1 is synchronized to the asynchronous
clock domain
0 = Back-to-back writes are enabled in Asynchronous mode
bit 11 TMWIP: Asynchronous Timer1 Write in Progress bit
1 = Write to the timer in Asynchronous mode is pending
0 = Write to the timer in Asynchronous mode is complete
bit 10 PRWIP: Asynchronous Period Write in Progress bit
1 = Write to the Period register in Asynchronous mode is pending
0 = Write to the Period register in Asynchronous mode is complete
bit 9-8 TECS[1:0]: Timer1 Extended Clock Select bits
11 = FRC clock
10 = FOSC
01 = TCY
00 = External Clock comes from the T1CK pin
bit 7 TGATE: Timer1 Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 6 Unimplemented: Read as ‘0’
Note 1: When Timer1 is enabled in External Synchronous Counter mode (TCS = 1, TSYNC = 1, TON = 1), any
attempts by user software to write to the TMR1 register are ignored.
DS70005349K-page 438 2017-2022 Microchip Technology Inc. and its subsidiaries
dsPIC33CK256MP508 FAMILY
REGISTER 21-1: T1CON: TIMER1 CONTROL REGISTER (CONTINUED)
bit 5-4 TCKPS[1:0]: Timer1 Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3 Unimplemented: Read as ‘0’
bit 2 TSYNC: Timer1 External Clock Input Synchronization Select bit(1)
When TCS = 1:
1 = Synchronizes the External Clock input
0 = Does not synchronize the External Clock input
When TCS = 0:
This bit is ignored.
bit 1 TCS: Timer1 Clock Source Select bit(1)
1 = External Clock source selected by TECS[1:0]
0 = Internal peripheral clock (FP)
bit 0 Unimplemented: Read as ‘0’
Note 1: When Timer1 is enabled in External Synchronous Counter mode (TCS = 1, TSYNC = 1, TON = 1), any
attempts by user software to write to the TMR1 register are ignored.
2017-2022 Microchip Technology Inc. and its subsidiaries DS70005349K-page 439