Memory Addressing
2.2.1 Byte Ordering
Instructions and data are stored in memory in little-endian byte order. Little-endian ordering
places the
least-significant byte of the instruction or data item at the lowest memory address and the
most-
significant byte at the highest memory address.
Figure 2-5 shows a generalization of little-endian memory and register images of a quadword
data
type. The least-significant byte is at the lowest address in memory and at the right-most byte
location
of the register image.
Figure 2-5. Byte Ordering
Figure 2-6 on page 15 shows the memory image of a 10-byte instruction. Instructions are byte
data
types. They are read from memory one byte at a time, starting with the least-significant byte
(lowest
address). For example, the following instruction specifies the 64-bit instruction MOV RAX,
1122334455667788 instruction that consists of the following ten bytes:
48 B8 8877665544332211
48 is a REX instruction prefix that specifies a 64-bit operand size, B8 is the opcode that—
together
with the REX prefix—specifies the 64-bit RAX destination register, and 8877665544332211
is the 8-
byte immediate value to be moved, where 88 represents the eighth (least-significant) byte and
11
represents the first (most-significant) byte. In memory, the REX prefix byte (48) would be
stored at the
lowest address, and the first immediate byte (11) would be stored at the highest instruction
address.
Quadword in Memory
Quadword in General-Purpose Register
00hbyte 0
01hbyte 1
02hbyte 2
03hbyte 3
04hbyte 4
05hbyte 5
06hbyte 6
07hbyte 7
063
byte 0byte 1byte 2byte 3byte 4byte 5byte 6byte 7
High (most-significant) Low (least-significant)
High (most-significant)
Low (least-significant)[AMD Public Use]
Memory Model 15
24592—Rev. 3.23—October 2020 AMD64 Technology
Figure 2-6. Example of 10-Byte Instruction in Memory
2.2.2 64-Bit Canonical Addresses
Long mode defines 64 bits of virtual address, but implementations of the AMD64 architecture
may
support fewer bits of virtual address. Although implementations might not use all 64 bits of
the virtual
address, they check bits 63 through the most-significant implemented bit to see if those bits
are all
zeros or all ones. An address that complies with this property is said to be in canonical
address form. If
a virtual-memory reference is not in canonical form, the implementation causes a general-
protection
exception or stack fault.
2.2.3 Effective Addresses
Programs provide effective addresses to the hardware prior to segmentation and paging
translations.
Long-mode effective addresses are a maximum of 64 bits wide, as shown in Figure 2-3 on
page 12.
Programs running in compatibility mode generate (by default) 32-bit effective addresses,
which the
hardware zero-extends to 64 bits. Legacy-mode effective addresses, with no address-size
override, are
32 or 16 bits wide, as shown in Figure 2-4 on page 13. These sizes can be overridden with an
address-
size instruction prefix, as described in “Instruction Prefixes” on page 76.
There are five methods for generating effective addresses, depending on the specific
instruction
encoding:
• Absolute Addresses—These addresses are given as displacements (or offsets) from the base
address of a data segment. They point directly to a memory location in the data segment.
• Instruction-Relative Addresses—These addresses are given as displacements (or offsets)
from the
current instruction pointer (IP), also called the program counter (PC). They are generated by
control-transfer instructions. A displacement in the instruction encoding, or one read from
00h
01h
02h
03h
04h
05h
06h
07h
08h22
09h11 High (most-significant)
Low (least-significant)48
B8
88
77
66
55
44
33[AMD Public Use]
16 Memory Model
AMD64 Technology 24592—Rev. 3.23—October 2020
memory, serves as an offset from the address that follows the transfer. See “RIP-Relative
Addressing” on page 18 for details about RIP-relative addressing in 64-bit mode.
• Indexed Register-Indirect Addresses—These addresses are calculated off a base address
contained
in a general-purpose register specified by the instruction (base). Different encodings allow
offsets
from this base using a signed displacement or using the sum of the displacement and a scaled
index
value. Instruction encodings may utilize up to ten bytes—the ModRM byte, the optional SIB
(scale, index, base) byte and a variable length displacement—to specify the values to be used
in the
effective address calculation. The base and index values are contained in general-purpose
registers
specified by the SIB byte. The scale and displacement values are specified directly in the
instruction encoding. Figure 2-7 shows the components of the address calculation. The
resultant
effective address is added to the data-segment base address to form a linear address, as
described in
“Segmented Virtual Memory” in Volume 2. “Instruction Formats” in Volume 3 gives further
details on specifying this form of address.
Figure 2-7. Complex Address Calculation (Protected Mode)
• Stack Addresses—PUSH, POP, CALL, RET, IRET, and INT instructions implicitly use the
stack
pointer, which contains the address of the procedure stack. See “Stack Operation” on page 19
for
details about the size of the stack pointer.
• String Addresses—String instructions generate sequential addresses using the rDI and rSI
registers,
as described in “Implicit Uses of GPRs” on page 30.
In 64-bit mode, with no address-size override, the size of effective-address calculations is 64
bits. An
effective-address calculation uses 64-bit base and index registers and sign-extends
displacements to 64
bits. Due to the flat address space in 64-bit mode, virtual addresses are equal to effective
addresses.
(For an exception to this general rule, see “FS and GS as Base of Address Calculation” on
page 17.)
[Link] Long-Mode Zero-Extension of 16-Bit and 32-Bit Addresses
In long mode, all 16-bit and 32-bit address calculations are zero-extended to form 64-bit
addresses.
Address calculations are first truncated to the effective-address size of the current mode (64-
bit mode
or compatibility mode), as overridden by any address-size prefix. The result is then zero-
extended to
the full 64-bit address width.
+
*
Effective Address
DisplacementIndex
Scale by 1, 2, 4, or 8
Base[AMD Public Use]
Memory Model 17
24592—Rev. 3.23—October 2020 AMD64 Technology
Because of this, 16-bit and 32-bit applications running in compatibility mode can access only
the low
4GB of the long-mode virtual-address space. Likewise, a 32-bit address generated in 64-bit
mode can
access only the low 4GB of the long-mode virtual-address space.
[Link] Displacements and Immediates
In general, the maximum size of address displacements and immediate operands is 32 bits.
They can
be 8, 16, or 32 bits in size, depending on the instruction or, for displacements, the effective
address
size. In 64-bit mode, displacements are sign-extended to 64 bits during use, but their actual
size (for
value representation) remains a maximum of 32 bits. The same is true for immediates in 64-
bit mode,
when the operand size is 64 bits. However, support is provided in 64-bit mode for some 64-
bit
displacement and immediate forms of the MOV instruction.
[Link] FS and GS as Base of Address Calculation
In 64-bit mode, the FS and GS segment-base registers (unlike the DS, ES, and SS segment-
base
registers) can be used as non-zero data-segment base registers for address calculations, as
described in
“Segmented Virtual Memory” in Volume 2. 64-bit mode assumes all other data-segment
registers (DS,
ES, and SS) have a base address of 0.
2.2.4 Address-Size Prefix
The default address size of an instruction is determined by the default-size (D) bit and long-
mode (L)
bit in the current code-segment descriptor (for details, see “Segmented Virtual Memory” in
Volume 2).
Application software can override the default address size in any operating mode by using the
67h
address-size instruction prefix byte. The address-size prefix allows mixing 32-bit and 64-bit
addresses
on an instruction-by-instruction basis.
Table 2-1 on page 18 shows the effects of using the address-size prefix in all operating
modes. In 64-
bit mode, the default address size is 64 bits. The address size can be overridden to 32 bits. 16-
bit
addresses are not supported in 64-bit mode. In compatibility and legacy modes, the address-
size prefix
works the same as in the legacy x86 architecture.[AMD Public Use]
18 Memory Model
AMD64 Technology 24592—Rev. 3.23—October 2020
2.2.5 RIP-Relative Addressing
RIP-relative addressing—that is, addressing relative to the 64-bit instruction pointer (also
called
program counter)—is available in 64-bit mode. The effective address is formed by adding the
displacement to the 64-bit RIP of the next instruction.
In the legacy x86 architecture, addressing relative to the instruction pointer (IP or EIP) is
available
only in control-transfer instructions. In the 64-bit mode, any instruction that uses ModRM
addressing
(see “ModRM and SIB Bytes” in Volume 3) can use RIP-relative addressing. The feature is
particularly useful for addressing data in position-independent code and for code that
addresses global
data.
Programs usually have many references to data, especially global data, that are not register-
based. To
load such a program, the loader typically selects a location for the program in memory and
then adjusts
the program’s references to global data based on the load location. RIP-relative addressing of
data
makes this adjustment unnecessary.
[Link] Range of RIP-Relative Addressing
Without RIP-relative addressing, instructions encoded with a ModRM byte address memory
relative
to zero. With RIP-relative addressing, instructions with a ModRM byte can address memory
relative to
the 64-bit RIP using a signed 32-bit displacement. This provides an offset range of 2
GBytes from the
RIP.
Table 2-1. Address-Size Prefixes
Operating Mode
Default
Address
Size (Bits)
Effective
Address Size
(Bits)
Address-
Size Prefix
(67h) 1
Required?
Long Mode
64-Bit Mode 64 64 no
32 yes
Compatibility Mode
32 32 no
16 yes
16 32 yes
16 no
Legacy Mode
(Protected, Virtual-8086, or Real
Mode)
32 32 no
16 yes
16 32 yes
16 no
Note:
1. “No” indicates that the default address size is used.[AMD Public Use]
Memory Model 19
24592—Rev. 3.23—October 2020 AMD64 Technology
[Link] Effect of Address-Size Prefix on RIP-Relative Addressing
RIP-relative addressing is enabled by 64-bit mode, not by a 64-bit address-size. Conversely,
use of the
address-size prefix does not disable RIP-relative addressing. The effect of the address-size
prefix is to
truncate and zero-extend the computed effective address to 32 bits, like any other addressing
mode.
[Link] Encoding
For details on instruction encoding of RIP-relative addressing, see in “Encoding for RIP-
Relative
Addressing” in Volume 3