Chapter 9

Memory Devices, Circuits,

and Subsystem Design

The 8088 and 8086 Microprocessors,Triebel and Singh 1

 Introduction
9.1 Program and Data Storage Memory—
9.2 Read-Only Memory—
9.3 Random Access Read/Write Memories—
9.4 Parity, Parity Bit, and Parity-Checker/Generator
Circuit
9.5 FLASH Memory
9.6 Wait-State Circuitry—
9.7 8088/8086 Microcomputer System Memory
Interface Circuitry—

The 8088 and 8086 Microprocessors,Triebel and Singh 2

9.1 Program and Data Storage Memory- The
Memory Unit
Memory—provides the ability to store and retrieve digital information
• Instructions of a program
• Data to be processed
• Results produced by processing
• Organization of the Microcomputer memory unit
• Secondary storage—stores information that is not
currently in use
• Slow-speed
• Very large storage capacity
• Implemented with magnetic/optical storage devices—in PC
• Hard disk drive
• Floppy disk drive
• Zip drive
• Primary storage—stores programs and data that are
currently active
• High-speed
• Smaller storage capacity
• Implemented with semiconductor memory
• Partitioning of Primary Storage
• Program storage memory—holds instructions of the program
and constant information such as look-up tables
• EPROM (BIOS in PC)
• FLASH memory
• DRAM (volatile code storage in a PC)
• Data storage memory—holds data that frequently changes
such as the informationand
The 8088 and 8086 Microprocessors,Triebel to be processed by a program
Singh 3
• SRAM
• DRAM (PC)
 9.2 Read-Only Memory- Types
Read-only memory (ROM)
• Used for storage of machine code of program
• Stored information can only be read by the MPU
• Information is nonvolatile—not lost when power turned off
• Types:
• ROM—mask-programmable read only memory
• Programmed as part of manufacturing process
• Lowest cost
• High volume applications
• PROM—one-time programmable read-only memory
• Permanently programmed with a programming instrument
• EPROM—erasable programmable read-only memory
• Programmed like a PROM
• Erasable by Ultraviolet light
• Electrically alterable ROM-like devices
• FLASH memory
• EEROM (E2ROM)

The 8088 and 8086 Microprocessors,Triebel and Singh 4

9.2 Read-Only Memory- Block Diagram
Block diagram of the ROM, PROM, and EPROM are
essentially the same
Signal interfaces
• Address bus (A10-A0 )—MPU inputs address
information that selects the storage location to be
accessed
• Data Bus (D7-D0)—information from the accessed
storage location output to be read by MPU
• Control bus—enables device and/or enables output
from device
• CE* = chip enable—active 0; 1 low-power stand
by mode
• OE* = output enable—active 0; 1 high-Z state
• Byte capacity- number of bytes a device can store
• Calculated from number of address bits
EX: Address = 11-bit address
Storage capacity = 211 = 2048 bytes
• Organization—how the size of a ROM is described
• Formed from capacity and data bus width
EX: 2048 X 8 or just 2K X 8
• Storage density—number of bits of storage in a ROM
• Calculated from byte capacity and data width
The 8088 a EX: Storage density = 2048 X 8 = 16384 bits (16K bits)
 9.2 Read-Only Memory- Organization and
Capacity
Example:
A ROM device has 15 address lines and 8 data lines. What are the
address range, byte capacity, organization, and storage density?

Solution:
• Address range
A14-A0 = 000 0000 0000 00002 111 1111 1111 11112
= 0000H 7FFFH
• Byte capacity
215 = 32,768 bytes = 32K bytes
• Organization
32,768 X 8 bit
• Storage density
32,768 x 8 = 262144 bits = 256K bits

The 8088 and 8086 Microprocessors,Triebel and Singh 6

9.2 Read-Only Memory- Operation
Read operation
• MPU outputs address and control
information on its bus.
• Interface circuit applies Address A10-A0
to the address inputs of the ROM to
select a specific byte wide storage
location
• Interface circuits decode additional
address bits to produce a chip select
output
• Logic 0 at CS* applied to the CE* input of
the ROM to enable it for operation
• Memory interface circuitry produces
appropriately timed MEMR* output
• MEMR* applied to OE* input of the ROM
to enable the information at the
addressed storage location onto the
output bus D7-D0
• Memory interface supplies the byte of
data from the ROM to the MPUs data bus
• MPU reads the byte of data from the ROM
from its data bus
The 8088 and 8086 Microprocessors,Triebel and Singh 7
9.2 Read-Only Memory- Standard EPROM ICs
EPROM part numbers formed by adding the
prefix “27” to the device total Kbits of storage
capacity
• Examples:
• 16K bit EPROM 2716
• 32K bit EPROM 2732
• 1M bit EPROM 27C010
• Most EPROM available in byte wide organization
• Examples:
• 2764 8K X 8
• 27C020 256K X8
• NMOS versus CMOS process
• Manufacturing processes used to make
EPROMs
• NMOS=N-channel metal-oxide
semiconductor
• CMOS= complementary symmetry metal-
oxide semiconductor
• “CMOS” designated by “C” in part
number
• NMOS—older devices such as 2716 and 27328
The 8088 and 8•86 Microprocessors,Triebel
CMOS—all newer and Singh 27C64 and up
devices
9.2 Read-Only Memory- Pin Layouts
EPROM pin layouts are designed
for compatibility
• Permit easy upgrade from
lower to higher density
• Publish pin layouts of future
densities
• Allows design of circuit
boards to support drop in
upgrade to higher densities
• Most pins are independent and
serve a common function for all
densities
• Examples:
pin 10- A0
pin 11--O0
pin 14- Gnd
• Some have one multi-function
pin• OE*/Vpp
• Vpp mode during
programming only
The 8088 and 8086 Microprocessors,Triebel and Singh 9
9.2 Read-Only Memory- EPROM Switching
Waveforms Timing of the read operation
• Output data is not immediately
available at the outputs
• Delays exist between the
application of the address,CE* and
OE* signals and the occurrence of
a valid output
• tacc= access time—address to
valid output delay time
• tCE= chip-enable time—chip enable
to valid output delay
• tOE=output-enable time—output
enable to valid data delay
• To assure that the MPU reads valid
data, these inputs must be applied at
the appropriate times
• Responsibility of the memory
interface circuitry
• Another delay occurs at the removal of
OE* before the outputs lines are
returned to the high-Z state
• tDF= chip-deselect
The 8088 and 8086 Microprocessors,Triebel and Singh time—time for10
the outputs to recover
9.2 Read-Only Memory- Expanding Byte
Capacity Many applications require more ROM
capacity than is available in a single device
• Need more bytes of storage
• Connects to a wider data bus
• Expanding byte capacity with 2 EPROMS
• Connect address bus lines in parallel
• Connect output lines in parallel
• Connect OE* in parallel
• Enable chips with separate chip selects
• Address bit A15 decoded to produce
CS0* and CS1*
• A15=0 CS0*
• A15=1 CS1*
• Implemented with inverting
buffer
• Byte capacity
216 = 64K bytes
• Organization
64K X 8 bit
• Storage density
The 8088 and 8086 Microprocessors,Triebel
2 X 32K x 8 and Singhbits
= 512K 13
9.2 Read-Only Memory- Expanding Word
Length Expanding word length with 2 EPROM
• Connecting to 8086 16-bit data bus
• Connect address bus lines in
parallel
• Connect CE* in parallel
• Connect OE* in parallel
• 8 data outputs of EPROM 0
used to supply the lower data
bus lines D0-D7
• 8 data outputs of EPROM 1
used to supply the upper 8
data bus lines D8-D15
• Byte capacity
2 X 215 = 64K byte
• Organization
32K X 16 bit
• Storage density
32K x 16 = 512K bits

The 8088 and 8086 Microprocessors,Triebel and Singh 14

 9.3 Random Access Read/Write Memories-

Types of RAMs
Random Access Read/Write Memory (RAM)
• Used for temporary storage of data and program information
• Stored information can be altered by MPU—read or written
• Information read from RAM
• Modified by processing
• Written back to RAM for reuse at a later time
• Information normally more frequently randomly accessed than ROM
• Information is volatile— lost when power turns off
• Types:
• Static RAM (SRAM)— data once entered remains valid as long as power supply is not
turned off
• Lower densities
• Higher cost
• Higher speeds
• Dynamic RAM (DRAM)—data once entered requires both the power to be maintained and
a periodic refresh
• Higher densities
• Lower cost
• Lower speeds
• Refresh requires additional circuitry

The 8088 and 8086 Microprocessors,Triebel and Singh 17

9.3 Random Access Read/Write Memories-
SRAM Block Diagram
Signal interfaces
• Address bus (A12-A0 )—MPU inputs
address information that selects the
storage location to be accessed
• Data Bus (I/O7-I/O0)—input/output of
information for the accessed storage
location from/to MPU
• Control bus—enables device, enables
output from device, and selects read/write
operation
• CE* = chip enable—active 0
• OE* = output enable—active 0
• WE* = write enable
0 = write to RAM
1 = read from RAM

The 8088 and 8086 Microprocessors,Triebel and Singh 18

9.3 Random Access Read/Write Memories-
Standard SRAM ICs
Part numbers vary widely by
manufacturer—Hitachi/NEC use “43xxx
SRAMs are available in a variety of
densities and organization
• Typical SRAM densities
• 64K bit
• 256K bit
• 1M bit
• Typical organizations of the 64K bit
SRAM • 64K X 1 bit
• 16K X 4 bit
• 8K X 8 bit

The 8088 and 8086 Microprocessors,Triebel and Singh 19

9.3 Random Access Read/Write Memories- Pin
Layout of SRAMs
4364 and 43256A pin layouts are
designed for compatibility
4364 pin configuration (Fig a)
• A12-A0 13-bit address
213 = 8K bytes
• I/O7-I/O0 byte wide
• Pin 1 NC = no connect
• Pin 27 WE*
• Pin 20 CE1* active 0
• Pin 26 CE2 active 1
• Pin 22 OE*
• Pin 28 Vcc
• Pin 14 GND
• 43256A differences (Fig b)
• Pin 1 A14
• Pin 26 A13
• Pin 20 called CS* (function
unchanged)

The 8088 and 8086 Microprocessors,Triebel and Singh 20

9.3 Random Access Read/Write Memories-
Expanding Word-Width and Capacity
Most SRAM subsystems
• Require both word-width and bit capacity
expansion
• Require the ability to write on byte-wide or
word wide basis- design only supports
words
• Expansions performed in a similar way as for
EPROMs
• 16K X 16-bit SRAM circuit
• A0-A12 in parallel
• A13 decoded to form CS0* and CS1*
• CS0* enable Bank 0
• CS1* enable Bank 1
• SRAMs 0 & 2—input/outputs connected in
parallel and supply low byte of data bus
• SRAMs 1 & 3—input/ outputs connected in
parallel and supply high byte of data bus
• MEMW* and MEMR* produces
independent write and read enables
MEMW* MEMR* Data Transfer
0 0 Invalid
0 1 Word write
1 0 Word read
1 1 Inactive
•
The 8088 and 8086 Micro roHow can the circuit be modified to support
byte wide write?
9.3 Random Access Read/Write Memories-
Standard Read/Write Cycle Times
Speed of a SRAM identified as
read/write cycle time
• Variety of speeds available—4364
available in speeds ranging from
100ns to 200ns
• Shorter the cycle time the better.
Designated by a dash speed indicator
following the part number
-10 = 100ns
-12 = 120ns

The 8088 and 8086 Microprocessors,Triebel and Singh 22

9.3 Random Access Read/Write Memories-
DRAM Block Diagram
DRAM signal interfaces
Address multiplexed in external circuitry into a
separate row and column address
Row address = A7-A0
Column address = A15-A8
Special RAS* and CAS* inputs used to strobe
address into DRAM
Row and column addresses applied at different
times to address inputs A0 through A7
Row address first
Column address second
Known as “RAS before CAS”
Address reassembled into 16-bit address inside
DRAM
Frequently data organizations are X1, X2, and X4
Separate data inputs and outputs
Data input labeled D
Data output labeled Q
Read/write (W) input signals read or write
operation
The 8088 and 8086 Microprocessors,Triebel and Singh 30
9.3 Random Access Read/Write Memories-
Standard DRAM ICs
DRAMs are available in a variety of densities
and organization
• Typical DRAM densities
• 64K bit
• 256K bit
• 1M bit, Etc.
• Modern DRAMS as large as 1G bit
• Typical organizations of the 4M bit DRAM
• 4M X 1 bit
• 1M X 4 bit
• Modern higher density devices also
available in X8, X16, and X32
organizations

The 8088 and 8086 Microprocessors,Triebel and Singh 31

9.3 Random Access Read/Write Memories-
Circuit Design using DRAMS
Sixteen 64KX1-bit DRAMs interconnected to form a
64K word memory subsystem—1M-bits of memory
Circuit connections
• 8 multiplexed address inputs of all devices
connected in parallel
• RAS and CAS lines of all devices
connected in parallel
• Data input and output lines
• Independent data lines arranged to
form a 16-bit wide output bus
• Independent input lines arranged to
form a 16-bit wide input bus
• In most microprocessor applications
input and output lines are connected
together
• Read/write lines
• W inputs of upper 8 DRAMs connected
together and driven by WR0*
• W inputs of lower 8 DRAMs connected
together and driven by WR1*
• Permits byte-wide or word-wide reads
and writes
The 8088 and 8086 Microprocessors,Triebel and Singh 33
􀂄 The primary memory section of a
microcomputer system is normally formed
from both read-only memories and random
access read/write memories (RAM)
􀂄 RAM is different from ROM in two ways:
􀂄 Data stored in RAM is not permanent in nature.
􀂄 RAM is volatile – that is, if power is removed from
RAM, the stored data are lost.
􀂄 RAM is normally used to store temporarily
data and application programs for execution.
􀂄 Static and dynamic RAMs
􀂄 For a static RAM (SRAM), data remain
valid as long as the power supply is not
turned off.
􀂄 For a dynamic RAM (DRAM), we must
both keep the power supply turned on
and periodically restore the data in each
location.
􀂄 The recharging process is known as
refreshing the DRAM.
9.4 Parity, The Parity Bit, and Parity-
Checker/Generator Circuit- Parity and the
Parity Bit
Data exchange between the MPU and data memory subsystem
in a microcomputer must be done without error
Sources of errors
Emissions that affect data on the data bus line
Electrical noise signals—spikes or transients that
affect data on data lines
Defective bit in a DRAM
Soft errors of DRAM
Solutions for improving data integrity
1. Parity
2. Error correction code (ECC)
Parity most frequently used
Parity bit
Add an additional bit of data to each byte or word of
data so that all elements of data have the same parity
Extra bit is known as the “parity bit”
• Even parity—element of data has an even
number of bits at the 1 logic level
• Odd parity—element of data has an odd number
of bit that are logic 1
Circuitry added to the DRAM memory interface to
generate an appropriate parity bit on writes to memory
Extra DRAM required to store the parity bit
Circuitry checks element of data from correct parity
during read operations
Parity errors (PE) reported to MPU usually as an
The 8088 and 80interrupt rocessors,Triebel and Singh 35
9.4 Parity, The Parity Bit, and Parity-
Checker/Generator Circuit- Parity
Generator/Checker Circuitry
Parity generator/checker circuit—circuit
added to the data memory interface to
implement parity
May be implemented with a 74AS280
parity generator/checker IC
9 inputs A through I
Two outputs Σodd and Σeven
Operation:
• Even number of inputs are
logic 1
- Σeven = 1 and Σodd = 0
- Signals that input has
even parity
• Odd number of inputs are
logic 1
- Σeven = 0 and Σodd = 1
- Signals that input has
odd parity

The 8088 and 8086 Microprocessors,Triebel and Singh 36

9.4 Parity, The Parity Bit, and Parity-
Checker/Generator Circuit- Parity
Generator/Checker Circuitry
Even parity generator circuit
Circuit configuration
Inputs A through H attach in parallel
to data bus lines D0 through D7
Input I is attached to the data output
of the parity DRAM
• Only activated during read operations
Σodd output is attached to the data
input of parity DRAM
MPU write operation
Accepts byte of data to be written to
memory as input from the data bus
Data also applied in parallel to the
input of the DRAMs for data lines D0
through D7
Circuit checks parity and generates
Σodd and Σeven outputs
Σodd output supplied to input of
parity DRAM for storage along with
the byte in memory
If parity is even—Σodd = 0 and 9-bit
value saved in memory still has
even parity
If parity is odd—Σodd = 1 and parity
The 8088 and 8086 Microprocof 9-bit value changed to even and 37
saved in memory
9.4 Parity, The Parity Bit, and Parity-
Checker/Generator Circuit- Parity
Generator/Checker Circuitry
Read operation:
Accepts 9-bit wide input from data
outputs of the DRAM subsystem
Checks the number of bits that are at
the 1 logic level
Produces appropriate logic level
signals at odd parity and even parity
outputs
If parity is even—Σeven = 1 and
parity is correct
• Memory operation completes
normally
If parity is odd—Σeven = 0 and a
parity error is detected
• Error condition signaled to
MPU by logic 0 at PE*
• Usually applied as NMI input to
the MPU
• Must get serviced before
executing next instruction
• MPU may
- Reattempt memory
access
- Initiate an orderly shut
The 8088 and 8086 Microprocessors,Triebedown of application 38
􀂄 Data storage memory
􀂄 Information that frequently changes is
normally implemented with random access
read/write memory (RAM).
􀂄 If the amount of memory required in the
microcomputer is small, the memory subsystem
is usually designed with SRAMs.
􀂄 DRAMs require refresh support circuit which
is not warranted if storage requirement are
small.
EXAMPLE
Design a memory system
consisting of 32Kbytes of R/W memory
and 32Kbytes of ROM memory. Use
SRAM devices to implement R/W
memory and EPROM devices to
implement ROM memory. The memory
devices to be used are shown below.
R/W memory is to reside over the
address range 00000H through
07FFFH and the address range of ROM
memory is to be F8000H through
FFFFFH. Assume that the 8088
microprocessor system bus signals
that follow are available for use: A0
through A19, D0 through D7, MEMR’,
MEMW’.
SOLUTION:
First let us determine the number of SRAM devices
needed.
No. of SRAM devices = 32Kbyte/(16K x 4) = 4
To provide an 8-bit data bus, two SRAMs must be connected
in parallel. Two pairs connected in this way are then placed in
series to implement the R/W address range, and each pair
implements 16Kbytes.
Next let us determine the number of EPROM devices
needed.
No. of EPROM devices = 32Kbyte/16Kbyte = 2
These two devices must be connected in series to implement
the ROM address range and each implement 16Kbytes of
storage.
SOLUTION:

Memory map of the system

SOLUTION:

RAM memory organization for the system design

SOLUTION:

ROM memory organization for the system design

SOLUTION:

Address range analysis for the design of chip select signals

SOLUTION:

Chip-select logic