DEPARTMENT OF INSTRUMENTATION AND CONTROL ENGINEERING
NATIONAL INSTITUTE OF TECHNOLOGY, TIRUCHIRAPPALLI- 620 015
DEGREE: [Link].
III SEMESTER (Section-B)
COURSE: DIGITAL ELECTRONICS THEORY
SUBJECT CODE: ICPC 14
ASSESMENT-II
Duration: 90 Minutes Date: 18.11.2021
Total: 20 Marks Time: 03.00 PM to 4.30 PM
1. Minimize and implement the multiple output function using basic gates (AND,OR,NOT)
F1(A,B,C)=∑m(0,1,2,5,6,7), F2(A,B,C)= ∑m(2,4,5,6)
2. Reduce the following and implement using (AND, OR, NOT). ∏M(3,6,8,11,12,14).d(1,5,7,10).
3. Design and implement half adder using NAND gates
4. Design and implement Full adder
5. Design and implement Full subtractor
6. Design and implement half subtractor using NAND gates
7. Design and Implement 2 bit look ahead carry generator.
8. Design and implement a 4 bit Binary to Gray code converter.
9. Design and implement a 4 bit Gray to Binary code converter
10. Design and implement half subtractor using NOR gates
11. Design and implement half adder using NOR gates
12. Design a circuit to detect the decimal numbers 0,1,3,4,6,7,8,in a 4 bit XS-3 code input.
13. Design an even parity generator and checker for a 3 bit data input.
14. Design an odd parity generator and checker for a 3 bit data input
15. Implement the following using 8x1 MUX. F(A,B,C,D,E)=∑m(2,7,8,13,15,16,21,23,26,31)
16. Implement F (A,B,C,D)= AB’+C’D+B’CD’ using 8x1 MUX.
17. Implement F (A,B,C,D)= AB’+AC’D+B’C+D’ using 8x1 MUX
18. Implement F (A,B,C,D)= A’B+CD’+AD’+C’ using 8x1 MUX .
19. Design and implement a logic circuit with 4 I/Ps A,B,C,D that will produce o/p 1, only
whenever two adjacent I/P variables are 1’s. (A & D are also to be treated as adjacent).
20. A BCD code is being transmitted to a remote receiver. The bits are A3,A2, A1, and A0, with
A3 as the MSB. The receiver circuitry includes a BCD error detector circuit that examines the
received code to see if it is a legal BCD code. Design this circuit to produce a HIGH for any error
condition
21. An analog-to-digital converter is monitoring the dc voltage of a 12-V storage battery on an
orbiting spaceship. The converter’s output is a four-bit binary number, ABCD, corresponding to the
battery voltage in steps of 1 V, with A as the MSB. The converter’s binary outputs are fed to a logic
circuit that is to produce a HIGH output as long as the binary value that is, the battery voltage is
greater than 6 V. Design this logic circuit
22. Design and implement a 4 bit BCD to Gray code converter
23. Design and implement a 4 bit Binary to Gray code converter
24. Implement F(A,B,C,D,E)=∑m(2,7,8,13,15,16,21,23,26,31) using 8x1 MUX
25. Implement F(A,B,C,D,E)=∑m(2,7,8,13,15,16,21,23,26,31) using 8x1 MUX
26. Implement F (A,B,C,D)= AB’+AC’D+AB’C+AD’ using 8x1 MUX
27. Implement F (A,B,C,D)= AB’C+AC’D+B’CD’+A’BD using 8x1 MUX
28. Design and implement full subtractor using NAND gates
29. Design and implement NAND gate using 2X1 MUX