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Basic Electronic Circuits by Proteus Simulating Software

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 Basic Electronic Circuits
Mohammed Mareai

by Proteus Simulating Software

Writer: Mohammed Abdullah Ahmed Mareai

Mohammed Mareai

This Page is Intentionally Left Blank

Mohammed Mareai

COPYRIGHT NOTICE

This book is protected by copyright law. No part of this book may be reproduced, or distributed in
any form or by any means, including printing, without the prior written permission of the author.
This book is only authorized for online reading and may not be distributed as a printed copy.

© [Mohammed Mareai], [2024]

All rights reserved.

For permissions, contact: [Link]

Mohammed Mareai

PREFACE

This book is a collection of electronic circuit simulation projects. It is intended to introduce anyone
new to the field of electronics with the field’s basic background about the main components and
circuits. This work was done with the help of the Proteus Design Suite. Each circuit in this book was
simulated, and then its output was recorded with a brief explanation of the nature of the circuit and
its outcome. All circuits included in this book are very basic, and the explanation for each is very
brief because this book intends to give a fundamental overview for the reader about electronic
circuitry and simulations, not a detailed explanation of the field.
This book covers 19 electronics-related topics. Each topic has a separate proteus file. For a proteus
file, we can create multiple sheets in which each sheet can have different headlines and circuits. In
our work, each topic includes one or more sheets, each of which has a sub-topic headline. Some
sheets may have different circuits if they belong to the same sub-topic.
This book has two sections:
• Section One: Basic Electronic Components in Proteus (7 Simulation Files).
• Section Two: Electronic Circuits (12 Simulation Files).

The simulation files are available in the repository in Link.

In Section One, electronic components such as operational amplifiers, diodes, transistors, logic gates,
etc. were discussed. This section's goal is to provide an overview of the working nature of these
components. In Section Two, different electronic circuit topics were discussed, such as ADC, DAC,
encoders, decoders, flip-flops, counters, etc. Each topic has its own individual simulation file. In
reality, each topic of these circuits has so many ways of being designed. For this book, basic design
examples in each sheet were only included with brief explanations.
Be careful: many circuits in this book can’t be implemented experimentally without further
consideration for the limitations of voltages and currents. Otherwise, the used components might get
overloaded. You can return to the datasheets of the used components and ICs in case you want to
implement the simulated circuits experimentally.
This work was conducted with reference to Michael H. Tooley's "Electronic Circuits: Fundamentals
and Applications" as a guiding resource [1].

Basic Background about Proteus Design Suite

Proteus Design Suite is PCB Design and Simulation Software. It can also be used for other
applications as well. In this book, Proteus was used for simulating electronic circuits only. Proteus
Simulation is based on playing the simulation in real-time. It plays the simulation from a starting
point, and then it keeps playing the simulation as a video.
In Proteus' Design Tab, we can create multiple sheets. Each one corresponds to its own simulation.
We can also modify and access sheets via the Design tab.
On the left side of the proteus main window, we have three main sections:
1. Components’ libraries.

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2. Simulation tools (measurements, graphs, sources, etc.)

3. Flow chart shapes

To select elements, we can go to components on the left and pick a component by clicking on the
letter (P).

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TABLE OF CONTENTS

Preface.................................................................................................................................................... 1
Basic Background about Proteus Design Suite ............................................................................... 1
A1 DC Basic Circuits........................................................................................................................... 10
Used Components ......................................................................................................................... 10
Sheet 1 Source Switch Load ............................................................................................................. 10
Schematic ...................................................................................................................................... 10
Results ........................................................................................................................................... 10
Sheet 2 Capacitor and Inductor ........................................................................................................ 12
Schematic ...................................................................................................................................... 12
Results ........................................................................................................................................... 12
Sheet 3 Relay .................................................................................................................................... 13
Schematic ...................................................................................................................................... 13
Results ........................................................................................................................................... 14
A2 AC Basic Circuits........................................................................................................................... 15
Used Components ......................................................................................................................... 15
Sheet 1 Oscilloscope ......................................................................................................................... 15
Schematic ...................................................................................................................................... 15
Results ........................................................................................................................................... 15
Sheet 2 Graphs .................................................................................................................................. 16
Schematic ...................................................................................................................................... 16
Results ........................................................................................................................................... 16
A3 Operational Amplifiers .................................................................................................................. 17
Sheet 1 Comparators ......................................................................................................................... 17
Schematic ...................................................................................................................................... 17
Results ........................................................................................................................................... 18
Sheet 2 Inverting and Non-Inverting Op-amps ................................................................................ 18
Schematic ...................................................................................................................................... 18
Results ........................................................................................................................................... 18
A4 Diodes ............................................................................................................................................ 20
Used Components ......................................................................................................................... 20
Sheet 1 Common Type Diodes ......................................................................................................... 20

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Schematic ...................................................................................................................................... 20
Results ........................................................................................................................................... 21
Sheet 2 Zener Diodes ........................................................................................................................ 22
Schematic ...................................................................................................................................... 22
Results ........................................................................................................................................... 22
A5 Transistors ...................................................................................................................................... 24
Used Components ......................................................................................................................... 24
Sheet 1 BJT ....................................................................................................................................... 24
Schematic ...................................................................................................................................... 24
Results ........................................................................................................................................... 25
Sheet 2 JFET ..................................................................................................................................... 25
Schematic ...................................................................................................................................... 25
Results ........................................................................................................................................... 26
A6 Logic Gates .................................................................................................................................... 27
Use Components ........................................................................................................................... 27
Sheet 1 "74xx" series ........................................................................................................................ 27
Schematic ...................................................................................................................................... 28
Results ........................................................................................................................................... 28
Sheet 2 "CD40xx" series .................................................................................................................. 29
Schematic ...................................................................................................................................... 29
Results ........................................................................................................................................... 30
A7 Controlled Switches ....................................................................................................................... 31
Used Components ......................................................................................................................... 31
Sheet 1 Thyristors ............................................................................................................................. 31
Schematic ...................................................................................................................................... 31
Results ........................................................................................................................................... 32
Sheet 2 Tri-state Buffer .................................................................................................................... 33
Schematic ...................................................................................................................................... 33
Results ........................................................................................................................................... 33
B1 Analog to Digital Converter (ADC) ............................................................................................... 36
Used Components ......................................................................................................................... 36
Sheet 1 Use Comparators as ADC .................................................................................................... 36
Schematic ...................................................................................................................................... 36

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Results ........................................................................................................................................... 37
B2 Digital to Analog Converter (DAC) ............................................................................................... 39
Used Components ......................................................................................................................... 39
Sheet 1 IC DAC0808 ........................................................................................................................ 39
Schematic ...................................................................................................................................... 39
Results ........................................................................................................................................... 40
B3 Encoders ......................................................................................................................................... 42
Used Components ......................................................................................................................... 42
Sheet 1 Logic Gates Encoder............................................................................................................ 43
Schematic ...................................................................................................................................... 43
Resutls ........................................................................................................................................... 44
Sheet 2 Sub Circuit Encoder ............................................................................................................. 45
Schematic ...................................................................................................................................... 46
Results ........................................................................................................................................... 46
Sheet 3 IC74LS148 Encoder ............................................................................................................ 47
Results ........................................................................................................................................... 47
B4 Decoders ......................................................................................................................................... 49
Sheet 1 Common Cathode IC4511 ................................................................................................... 49
Schematic ...................................................................................................................................... 49
Results ........................................................................................................................................... 50
Sheet 2 Common Anode IC7447 ...................................................................................................... 50
Schematic ...................................................................................................................................... 50
Sheet 3 Common Cathode IC7448 ................................................................................................... 51
Schematic ...................................................................................................................................... 51
B5 Analog Input to display .................................................................................................................. 52
Sheet 1 Subcircuit 9 to 1 Encoder .................................................................................................... 52
Schematic ...................................................................................................................................... 52
Results ........................................................................................................................................... 52
Sheet 2 IC74148 7 to 1 Encoder ....................................................................................................... 53
Schematic ...................................................................................................................................... 53
Results ........................................................................................................................................... 53
B6 Flip-Flops and Latches ................................................................................................................... 54
Used Components ......................................................................................................................... 54

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Sheet 1 SR Latch .............................................................................................................................. 54

Schematic ...................................................................................................................................... 55
Results ........................................................................................................................................... 55
Sheet 2 Gated SR Latch .................................................................................................................... 56
Schematic ...................................................................................................................................... 57
Results ........................................................................................................................................... 57
Sheet 3 D Latch ................................................................................................................................ 57
Schematic ...................................................................................................................................... 58
Results ........................................................................................................................................... 58
Sheet 4 Flip Flop............................................................................................................................... 60
Schematic ...................................................................................................................................... 60
Results ........................................................................................................................................... 60
B7 Counters ......................................................................................................................................... 62
Used Components ......................................................................................................................... 62
Sheet 1 Asynchronous (Ripple) Counters ........................................................................................ 62
Schematic ...................................................................................................................................... 63
Results and Discussion .................................................................................................................. 63
Sheet 2 Synchronous Counters ......................................................................................................... 63
Schematic ...................................................................................................................................... 63
Sheet 3 Asynchronous Counters D-type Flip flop ............................................................................ 64
Schematic ...................................................................................................................................... 64
Sheet 4 Decade Counter ................................................................................................................... 65
Schematic ...................................................................................................................................... 65
Results ........................................................................................................................................... 65
Sheet 5 Ring Counter ........................................................................................................................ 65
Schematic ...................................................................................................................................... 66
Results ........................................................................................................................................... 66
B8 Shift registers.................................................................................................................................. 67
Used Components ......................................................................................................................... 67
Sheet 1 Serial-In, Serial-Out Shift Register (SISO) ......................................................................... 67
Schematic ...................................................................................................................................... 67
Results ........................................................................................................................................... 67
Sheet 2 Serial-In, Parallel-Out Shift Register (SIPO) ...................................................................... 68

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Schematic ...................................................................................................................................... 68
Results ........................................................................................................................................... 69
Sheet 3 Parallel-In, Serial-Out Shift Register (PISO) ...................................................................... 69
Schematic ...................................................................................................................................... 70
Results ........................................................................................................................................... 70
Sheet 4 Parallel-In, Parallel-Out Shift Register (PIPO) ................................................................... 70
Schematic ...................................................................................................................................... 71
Results ........................................................................................................................................... 71
B9 Multiplexers and Demultiplexers ................................................................................................... 72
Used Compoenets .......................................................................................................................... 72
Sheet 1 2x1 Multiplexer ................................................................................................................... 72
Schematic ...................................................................................................................................... 72
Results ........................................................................................................................................... 73
Sheet 2 4x1 Multiplexer ................................................................................................................... 73
Schematic ...................................................................................................................................... 73
Results ........................................................................................................................................... 74
Sheet 3 Time Division Mux.............................................................................................................. 74
Schematic ...................................................................................................................................... 75
Results ........................................................................................................................................... 75
Sheet 4 1x4 Demultiplexer ............................................................................................................... 75
Schematic ...................................................................................................................................... 76
Results ........................................................................................................................................... 76
Sheet 5 Time Division Mux Demux ................................................................................................. 77
Schematic ...................................................................................................................................... 77
Results ........................................................................................................................................... 77
B10 Memory ........................................................................................................................................ 79
Used Compoenets .......................................................................................................................... 79
Sheet 1 IC74LS189 64-Bit Random Access Memory ...................................................................... 79
Schematic ...................................................................................................................................... 79
Results ........................................................................................................................................... 80
B11 IC 555 timer ................................................................................................................................. 81
Used Components ......................................................................................................................... 81
Sheet 1 Astable Multivibrator........................................................................................................... 81

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Schematic ...................................................................................................................................... 81
Results ........................................................................................................................................... 82
Sheet 2 Monostable Multivibrator .................................................................................................... 82
Schematic ...................................................................................................................................... 82
Results ........................................................................................................................................... 82
Sheet 3 Bistable Multivibrator .......................................................................................................... 83
Schematic ...................................................................................................................................... 83
Results ........................................................................................................................................... 84
B12 Oscillators and Clock ................................................................................................................... 85
Used Components ......................................................................................................................... 85
Sheet 1 Hartley Oscillator................................................................................................................. 85
Schematic ...................................................................................................................................... 85
Results ........................................................................................................................................... 86
Sheet 2 Op-Amp Schmitt Trigger Oscillator .................................................................................... 86
Schematic ...................................................................................................................................... 86
Results ........................................................................................................................................... 87
Sheet 3 Wein Bridge Oscillator ........................................................................................................ 87
Schematic ...................................................................................................................................... 87
Results ........................................................................................................................................... 88
References ............................................................................................................................................ 89

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Section One
Basic Electronic Components in Proteus

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A1 DC BASIC CIRCUITS

In this simulation, some basic DC-source electrical circuits are introduced. This file aims to guide the
user to get a general picture of what is inside Proteus Software in simple terms.

Used Components
1. AMMETER-MILLI (measures current in milliamperes)
2. BATTERY
3. CAPACITOR
4. INDUCTOR
5. LAMP
6. LED-BLUE
7. LEDGREEN
8. LED-RED
9. MOTOR
10. POT-LIN (potentiometer)
11. RELAY
12. RESISTOR
13. SW-SPDT (switch single pole double through)
14. SWITCH
15. VOLTMETER

SHEET 1 SOURCE SWITCH LOAD

This simulation consists of four circuits that aim to introduce Switch and SW-SPDT. Lamps, LEDs,
and motors are also used as loads.

Schematic

Schematic 1 Schematic 2

Schematic 3

Results

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Schematic 1

For Schematic 1, a 1k Ohm potentiometer is used. A potentiometer can control the voltage received
by the lamp in the circuit, unlike the switch, which can only make current flow or block it from
flowing all at once. After trying some variations for the potentiometer, we found these results:

Figure 1: High resistance Figure 2: Moderate resistance Figure 3: Low resistance

For Figure 1, we found that using the highest resistance in the potentiometer resulted in a high
voltage across the potentiometer itself.
In Figure 2, a lower resistance is used, which results in a lower voltage across the potentiometer.
This makes the lamp light up slightly.
In Figure 3, the lowest resistance is used. This has led to a very low voltage across the 1k Ohm
potentiometer. The lamp consequently lights up in white. This in Proteus indicates that it is operating
in its normal mode.

Schematic 2

Schematic 2 has similar findings as Schematic 1. The only difference is that instead of the lamp
lighting more brightly, the motor will spin faster when the potentiometer is set to lower resistance.

Schematic 3

In Schematic 3, SW-SPDT is used. This switch has one input for current and redirects it into two
output pins. This schematic uses two SW-SPDTs that are facing each other. In this circuit, we have
four possibilities for setting the SW-SPDTs, which are:

Figure 1 Figure 2 Figure 3 Figure 4

Based on these results, we found that for this configuration, the LEDs will be high only if both
switches are in the same state. This configuration is said to be equivalent to the logic of logic gate
XOR. Logic gates will be discussed in detail in the simulation “A6 LOGIC GATES”.

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SHEET 2 CAPACITOR AND INDUCTOR

Capacitors and inductors are more commonly used in AC circuits, but in this simulation, the effect of
capacitors and inductors in DC circuits is shown. When a capacitor is connected to a DC voltage
source, it initially starts charging until the voltage across it equals the voltage across the DC source;
then, it blocks current from flowing. An inductor initially induces voltage through its magnetism
effect. This induced voltage will initially oppose the voltage from the source. After some time, this
induced voltage will vanish, making the inductor finally act as a short circuit.

Schematic

Schematic 5
Schematic 4

Results

Schematic 4

Figure 1 Figure 2 Figure 3

Figure 4 Figure 5 Figure 6

For schematic 4, we found that:

1. When both capacitor and lamp switches are opened, there will be no current flowing to the
capacitor or the lamp, as shown in Figure 1.

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2. When the capacitor switch is closed and the lamp switch is opened, the capacitor will get
charged by the source, as shown in Figure 2. This will not happen instantaneously, as the
capacitor charging process is not linear. When the voltage across the capacitor equals the
opposite of the voltage across the source, the charging process will stop, and the capacitor
will act as an open circuit, as shown in Figure 3.
3. When the capacitor switch is opened and the lamp switch is closed, the capacitor-stored
charges will flow to the lamp, resulting in the lamp lighting up for a short time, as shown in
Figure 4. Then, the capacitor will be discharged completely, as shown in Figure 5.
4. When both the capacitor and lamp switches are closed, the capacitor will be charged. After
some time, voltage division will happen between the lamp and the capacitor, resulting in a
balanced state, as shown in Figure 6.

Schematic 5

Figure 1 Figure 2

In this circuit, we have an inductor and a resistor in series. We see that initially; the inductor blocks
the current and then allows it gradually. As shown in Figure 1, the voltage across the inductor is 3.19
volts. However, after a few seconds, the voltage across the inductor becomes zero, as shown in
Figure 2. Thus, the inductor in Figure 2 finally acts as a normal wire (short circuit).

SHEET 3 RELAY

A relay is a type of switch that allows current to flow if it receives an input signal of low voltage. In
Proteus, relays have four pins. Two pins are used for the circuit, and two pins are used for the input
signal.

Schematic

Schematic 6

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Results
We have two possible states for the circuit:

Figure 1 Figure 2

In Figure 1, we see that the SW (switch in the 5V source circuit) is open. This made the relay switch
consequently open, and no current flowed to the lamp. In Figure 2, we see that the SW is closed. This
enabled the relay to permit the flow of current to the lamp.

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A2 AC BASIC CIRCUITS

This simulation aims to introduce the use of an oscilloscope and graphs in Proteus for measurement
purposes in AC.

Used Components
1. CAPACITOR
2. INDUCTOR
3. RESISTOR
4. VSINE (sinewave AC source)

SHEET 1 OSCILLOSCOPE

The oscilloscope can be selected from ‘virtual instrument mode’ from the icons on the left.
The oscilloscope in Proteus is similar to the actual oscilloscope. The oscilloscope’s settings can be
controlled by opening it from the “Debug Tab.”. It measures the voltage from the point where the
cable is attached to the ground.

Schematic

Schematic 1

Results

Figure 1

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We can see that both the yellow graph (voltage from point A to ground) and the blue graph (voltage
from point B to ground) are in phase. However, the red graph shows a significant phase shift, which
is the voltage across the capacitor.

SHEET 2 GRAPHS

In this circuit, an Analogue Graph is used. Analogue Graph can be selected from ‘Graph Mode’ from
the icons on the left. We can make voltage and current graphs by dragging current and voltage
probes to the graph area. Current and voltage probes are used to give current and voltage
measurements. By dragging probes to the graph, we can show their values. They can be selected
from the section “probe mode” located in the icons on the left. We can make the graph show the
waveform by left-clicking on the graph and then clicking on Simulate Graph.

Schematic

Schematic 2

Results
The result can be shown in the graph of Schematic 2.
We can calculate the magnitude of the current and phase shift as follows:
𝑣 = 10∠0 𝑉, 𝑓 = 5𝐻𝑧
𝑅 = 1𝑜ℎ𝑚, 𝐿 = 0.0228169𝐻, 𝐶 = 0.314159𝐹
10∠0
𝑖= = 8.516∠ − 31.6
1
1 + 2𝜋𝑓𝐿𝑖 +
2𝜋𝑓𝐶𝑖
Based on these calculations, we expect the current to have a phase shift of 31.6 degrees. In addition,
the voltage in our calculations is 10V, whereas the current is 8.5A. This means that the current's
amplitude will be less than the voltage by 1.5.
In Schematic 2, we can see that voltage and current have a slight phase shift, which can be estimated
at 31 degrees. In Schematic 2, we can also see that the voltage amplitude is 10 volts, while the
current is slightly lower than the voltage amplitude. Based on this, we can estimate the current to be
8.5 volts, which matches our calculations.

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A3 OPERATIONAL AMPLIFIERS

Operational amplifiers (Op-Amps) are an analog circuit block that takes a differential voltage input
and produces a single-ended voltage output. Op-Amps are not a single electronic component. The
internal structure of Op-Amps consists of many basic electronic components, such as transistors,
resistors, diodes, and capacitors. All of these components are connected in one small circuit called an
integrated circuit (IC).
In general, Op-Amps have five main pins. Two pins are connected to power and ground. Thirdly,
there is an inverting pin, which is categorized by a ‘-’ sign. Fourthly, there is a non-inverting pin that
is categorized by a ‘+’ sign. Fifthly, there is the output pin. By making proper adjustments to the
connections of the pins, we can make the Op-Amp act as a comparator, inverting or non-inverting.
In this simulation, operational amplifiers (Op-Amps) will be used in two sheets. Firstly, it will be
shown how to use them as comparators. Then, they will be used in inverting and non-inverting states.

Used Components

1. 741 (Op-Amps IC)

2. BATTERY
3. LOGICPROBE(BIG)
4. RESISTOR
5. VSINE

SHEET 1 COMPARATORS

A comparator is a type of IC that uses op-amps to convert analog to digital data. This can be done by
connecting both inverting and non-inverting pins to two different voltage levels. If the non-inverting
‘+’ pin has a larger voltage input than the inverting ‘-’ pin, the output of the Op Amp is high. If not,
it will be low. The logic probe is used to check the output of the digital circuit, whether it is low or
high.

Schematic

Schematic 1

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Results
We can see in Schematic 1 that two comparators are used.
1. In the first comparator, the ‘+’ pin is set to the source, and the ‘-’ pin is set to the ground, so
the voltage at the ‘+’ pin is larger than the pin ‘-’. Thus, the output of the comparator is high.
2. In the second comparator, the ‘+’ pin is set to the ground and the ‘-’ pin is set to the source,
so the voltage at pin ‘-’ is bigger than that at pin ‘+’. Thus, the output of the comparator is
low.

SHEET 2 INVERTING AND NON-INVERTING OP-AMPS

Op-Amp circuits come in two configurations: inverting and non-inverting. They serve a variety of
purposes. One of them is amplifying the input signal. Non-inverting Op-Amp returns the output
signal amplified and in the same phase as the input signal. Inverting Op-Amp Amp returns the output
signal amplified with a phase shift of 180 degrees.

Schematic

Schematic 2: Non-inverting Schematic 3: Inverting

Results

Schematic 2

Figure 1

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The output signal in Figure 1 is shown in a blue color graph, while the yellow color graph is used for
the input signal. We see that the non-inverting configuration gives us an output signal that is
amplified with a 0° phase shift.

Schematic 3

Figure 2

In Figure 2, the input signal is shown in the yellow graph, while the output signal is shown in the
blue graph. We see that the inverting configuration gives us an output signal that is amplified with a
180-degree phase shift.

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A4 DIODES

Diodes are one of the most fundamental electronic components that contain semiconductors. Diodes,
unlike operational amplifiers, are individual components rather than ICs. In Proteus, different codes
can correspond to different diode models. These codes refer to information such as operating
voltages, maximum currents, diode factories, etc. You can also obtain more detailed information by
checking the diode code datasheet.
In this section, diodes will be introduced. Also, different components’ codes in proteus for diodes are
used to emphasize how Proteus can have different codes for the same component.

Used Components
1. IN914
2. IN4001
3. IN4148
4. IN5333BRL
5. IN54U
6. BY127
7. BUCIC
8. BZX85C
9. BZY88C
10. OA47
11. OA91
12. RESISTOR
13. VSINE
14. VSOURCE

SHEET 1 COMMON TYPE DIODES

A common type of diode is one that allows current to flow in only one direction. In this simulation,
the following diode codes are used: 1N4148, 1N914, AA113, OA47, OA91, 1N4001, and 1N5404.
Those types can be used for various purposes, and each allows a range of voltages. Specific details
are mentioned in each diode code datasheet.

Schematic

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Schematic 1

Results

Figure 1: 5V Input

Figure 2: 50V Input

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Figure 3: 100V Input

We see that diodes allow current to flow in one direction. As we know, a sinusoidal AC wave has
positive and negative components. We can see in Figure 1 that only a positive wave can pass. If the
voltage is increased, some diodes reach their breakdown point. In Figure 1, a 5V input is used, and
all diodes worked just fine. Figure 2 depicts the diode's wave in both positive and negative
directions. This can be interpreted as meaning that the diodes have broken down. Figure 3 shows that
several diodes have reached their breakdown point due to 100V input.

SHEET 2 ZENER DIODES

Despite the source's voltage, Zener diodes maintain constant voltage differences across them. They
are useful for voltage regulation applications. In the simulation, four Zener diode codes are used,
which are BZY88, BZX61, BZX85, BZY93, and 1N5333. In the simulation, 5 volt Zener diodes are
used, meaning there will be a constant 5 volt difference between them.

Schematic

Schematic 2

Results

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Figure 1: 5V input Figure 2: 50V Input Figure 3: 100V Input

We can see that when a 5V input voltage is used in Figure 1 with a 5V Zener diode, we have a
voltage of 4.9V. That is due to the internal forward voltage in the Zener diode. When 50V and 100V
are used in Figure 2 and Figure 3, we see that the voltage is almost the same, which is 5V across the
Zener diodes. We also see that the four different types of Zener diodes do not exhibit significantly
different behavior in the simulation. For more information, please read the datasheets for these Zener
diode codes.

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A5 TRANSISTORS

Transistors are one of the most important components in the electronic device industry. There are so
many types of transistors, as well as many uses for them. In this simulation, only very basic transistor
circuits are introduced to demonstrate how transistors can control a large output voltage based on an
input voltage signal.
For simplicity, only two types are used, which are bipolar junction transistors (BJT) and junction
field effect transistors (JFET). In addition, the same voltage that is applied to the collector-
emitter/drain source is applied to the base-emitter/gate source to show how transistors can be used as
switches.

Used Components
1. 2N2608
2. 2N3370
3. BC108
4. BCY70
5. BUTTON
6. LED-RED
7. VSOURCE

SHEET 1 BJT

A bipolar junction transistor (BJT) is a transistor that has three pins, namely the collector, emitter,
and base. We have two main types of BJT transistors, which are PNP and NPN. The two types
operate as follows:
For an NPN, a high voltage is applied across the collector and emitter. Then, if a small voltage is
applied across the base and emitter, the current will flow normally from the base and collector to the
emitter. If no voltage is applied to the base, no current will flow through it; as a result, no current will
flow from the collector to the emitter.
For the PNP type, the polarity of the pins is flipped. A high voltage will be applied between the
emitter and collector. Then, if a small voltage is applied between the emitter and the base, current
will flow from the emitter to the collector. If no voltage is applied to the base, the current will not
flow.

Schematic

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Schematic 1: NPN Transistor

Schematic 2: PNP Transistor

Results

Figure 1 Figure 3 Figure 4

Figure 2

In Figure 1 and Figure 2, an NPN transistor is used. If there is no voltage applied to the base, current
will not flow, as shown in Figure 1. We can see that if the button is clicked, a voltage will be applied
to the base. This voltage will allow current to flow from the collector to the emitter, resulting in the
LED turning on, as shown in Figure 2.
In Figure 3 and Figure 4, an PNP transistor is used. If there is no voltage applied to the base, current
will not flow, as shown in Figure 3. If voltage is applied to the base, current will flow from the
emitter to the collector, as shown in Figure 4.

SHEET 2 JFET

This transistor type has three pins, which are drain, gate, and source. It has two main types, which are
N-Channel JFET and P-Channel JFET. If a voltage difference is applied across the gate and source,
the JFET will allow current to flow from the drain to the source. The polarity is the difference
between the P-channel and the N-channel. If the gate is connected to a positive terminal, current will
flow from the drain to the source in the N-channel JFET. In P-Channel JFET, current will flow from
the source to the drain if the gate is connected to the negative terminal.

Schematic

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Schematic 3: N-Channel JFET Schematic 4: P-Channel JFET

Results

Figure 1 Figure 2 Figure 3 Figure 4

In Figure 1 and Figure 2, an N-channel transistor is used. If there is no voltage applied to the gate,
the current will not flow, as shown in Figure 1. We can see that when the button is clicked, a voltage
will be applied to the gate. This voltage will allow current to flow from the drain to the source,
resulting in the LED turning on, as shown in Figure 2.
In Figure 3 and Figure 4, a P-channel transistor is used. If there is no voltage applied to the gate, the
current will not flow, as shown in Figure 3. We can see that current will flow from source to drain if
a negative voltage is applied to the gate, as shown in Figure 4.

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A6 LOGIC GATES

Logic gates are integrated circuits (ICs) that are used to perform binary operations on a digital input.
Logic gates can have Quad 2-input, Triple 3-input, Dual 4-input, and single 8 inputs, meaning we
can have the same logical operation on 2, 3, 4, or even 8 inputs at the same time. Two common types
of ICs are used as logic gates, which are the “74xx” and “40xx” series.

Use Components
1. 74HC86
2. 74HC4078
3. 4001
4. 4011
5. 4023
6. 4025
7. 4049
8. 4070
9. 4071
10. 4072
11. 4073
12. 4078
13. 4081
14. 7400
15. 7402
16. 7404
17. 7408
18. 7410
19. 7411
20. 7420
21. 7425
22. 7427
23. 7430
24. 7432
25. LOGICPROBE (BIG)
26. LOGICTOGGLE

SHEET 1 "74XX" SERIES

This series of ICs uses Transistor-Transistor Logic (TTL) or Complementary Metal-Oxide-

Semiconductor (CMOS) technologies.
The naming of these ICs “74xx” is as follows:

❖ Start with 74, which indicates the series you are in.

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❖ HC, LS, HTC, or any other letters. In table 1, the letter ‘x’ is used to refer to those ICs. These
letters explain the technology used in the IC.
❖ The last numbers indicate the IC code you are working with.

Typically, the "74xx" series logic gate ICs are shown in Table 1 (note that not all of these ICs are
used in the simulation of this guide book.):
Table 1: “74XX” logic gates series

Configuration AND NAND OR NOR XOR XNOR

Quad 2-input 74x08 74x00 74x32 74x02 74x86 74x7266
Triple 3-
74x11 74x10 74x4075 74x27 n/a n/a
Input
Dual 4-input 74x21 74x20 74x4072 74x29 n/a n/a
Single 8-
n/a 74x30 74x4078 74x4078 n/a n/a
input

Schematic

Schematic 2: 2-Input (Complementary)

Schematic 1: 2-Input Schematic 3: 3-Input

Schematic 4: 4-Input

Schematic 5: 8-Input

Results
In the basic theory of logic gates, each logic gate circuit has a special truth table. The circuits shown
in schematics 1–5 give us an example of one case in these logic gates truth tables in which a certain

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input of binary is given to get its corresponding output. For example, in Schematic 1, we see that two
low states are given to the ‘AND’ gate, resulting in a low state. We can also see that the ‘NOT’ gate
takes low input and gives high output. You can compare other schematics 2–5 and observe how each
logic gate performs its logical binary operation.

SHEET 2 "CD40XX" SERIES

This type of IC uses only a CMOS configuration, unlike the “74xx” series. The naming of the
“CD40XX” series is as follows:

❖ The manufacturer's prefix, such as CD, is used for Texas Instruments Company.
❖ The number 40 indicates the “40” ICs.
❖ The last numbers indicate the specific type of IC you are working with.
Table 2 shows the common "40xx" series logic gate ICs (note that not all of these are used in the
simulation):
Table 2: “CD40XX” Logic Gates Series

Configuration AND NAND OR NOR XOR XNOR

Quad 2-Input 4081 4011 4071 4001 4070 4077
Triple 3-
4073 4023 4075 4025 n/a n/a
Input
Dual 4-Input 4082 4012 4072 4002 n/a n/a
Single 8-
4068 4068 4078 4078 n/a n/a
Input

Schematic

Schematic 7: 2-Input (Complementary)

Schematic 8: 3-Input
Schematic 6: 2-Input

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Schematic 9: 4-Input

Schematic 10: 8-Input

Results
We can see that the “CD40xx” logic gate series works in the same way as the “74xx” series. For
example, in Schematic 6, we see that two low states are given to the ‘AND’ gate, resulting in a low
state. We can also see that the ‘NOT’ gate takes low input and gives high output. You can check
other schematics 7–10 to see how the other logical binary operations are performed.

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A7 CONTROLLED SWITCHES

For most electronic devices, using signals to control the flow of other signals is an essential task. In
this simulation, two controlled switches are introduced:

1. Thyristors: These are controlled switches used in power control applications. Once activated,
they allow the current to flow until the thyristor stops.
2. Tri-state Buffer: This is used in digital electronic circuits to enable signal routing. When the
input signal is high, they allow digital data to flow. When the input signal becomes low, it
stops data from flowing.

Used Components
1. BUTTON
2. CLOCK
3. LAMP
4. LED-BLUE
5. LOGICPROBE (BIG)
6. LOGICTOGGLE
7. RESISTOR
8. THYRISTOR
9. TRIBUFFER
10. VSINE
11. VSOURCE

SHEET 1 THYRISTORS

For voltage regulation purposes, thyristors are used. They have three pins, which are ‘Gate’,
‘Anode’, and ‘Cathode’. Thyristors allow current to flow with high voltage between the cathode and
anode if a high-voltage signal is applied to their gate. If the gate is triggered once, the thyristors
maintain a conducting state even if the high signal is removed. They become in an unconducting
state again only if there is no longer a flow of current between 'Cathode' and 'Anode'. Then, it needs a
new trigger action to be in a conducting state.

Schematic

Schematic 1 Schematic 2 Schematic 3

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Schematic 4 Schematic 5

Results
In schematics 1–5, we can see that the thyristor circuit has two switches: a trigger switch that serves
as a trigger and a thyristor switch that is used to open the thyristor's circuit.

Schematic 1 & 2

Figure 1 Figure 2 Figure 3

In Figure 1, we can see that the lamp is off because there is no triggering signal applied. In Figure 2,
once the trigger switch is closed, we see the lamp going on. After the trigger switch is opened again
in Figure 3, the lamp is still on. The lamp will remain on until the thyristor switch is opened.
In schematic 2, the circuit will work in the same way as in schematic 1, even if the triggering signal
is an AC signal, it will work the same way as the DC signal.

Schematic 3

Figure 1 Figure 2 Figure 3

You can see that in Schematic 3, the AC source is used in the thyristor's 'cathode' and 'anode' pins. In
Figure 1, the lamp is off because there is no triggering signal applied to the thyristor. In Figure 2, the
triggering signal is applied, and the lamp becomes ON. When the trigger switch is opened in Figure
3, we see the lamp going off, unlike in Schematics 1 and 2. That is because the thyristor loses its
conductivity state if there is no longer current flowing between the ‘cathode’ and ‘anode’ pins of the
thyristor. When AC is used, the current will alternate between positive and negative, meaning it will
reach zero voltage at some point, thus, the thyristor loses its conductivity state (as if the thyristor
switch is opened).

Schematic 4 & 5

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Figure 1 Figure 2

In Figure 1, we see that the LED will not go high even if the trigger switch is closed. That is because
the LED and the thyristor are facing opposite directions. In Figure 2, we see that when the LED is
used in the correct direction, the simulation works just the same as in Schematic 1.

SHEET 2 TRI-STATE BUFFER

A tri-state buffer has three pins, which are ‘Din, ‘Dout’, and ‘Enabler’. If the ‘Enabler’ pin is set to
high, the data will go from the pin Data-in ‘Din’ to the pin Data-out ‘Dout’. If the 'Enabler' is set to
low, data will stop being transmitted.

Schematic

Schematic 7
Schematic 6

Results

Schematic 6

Figure 1 Figure 2 Figure 3

We can see that in Figure 1 and Figure 2, the data in the input pin ‘Din’ and the output pin ‘Dout’ are
the same. That's because the enabler pin is set to high. When the Enabler pin is set to low in Figure 3,

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the buffer output is not recognized as a digital high or low state, which is shown in Proteus as a ‘?’
sign.

Schematic 7

Figure 1

In schematic 7, a signal generator and a clock are used. The signal generator produces a high-
frequency square wave signal, while the clock generates alternating high and low states. In figure 1,
we see from the graph that the wave looks like a repeating sequence of high-frequency square waves
for half a period and an almost zero wave signal for the other half of the period. That is because the
signal is transmitted when the clock goes high and blocked when the clock goes low.

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Section Two
Electronic Circuits

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B1 ANALOG TO DIGITAL CONVERTER (ADC)

This type of electronic circuit converts analog input to digital. Analog data, such as the voice
recorded by a microphone, is continuous over time. Digital data, such as counters, are
discontinuous/discrete over time. Digital data is more common for calculation and computation
purposes; thus, we usually use ADC when we want to perform the calculation for analog data (ex.
from an analog sensor) using a microcontroller.
In this simulation, a very basic ADC is made using one IC, which is a comparator. If the voltage in
the '+' pin is higher than the voltage in the '-' pin (analog data as input), a comparator can output high
or low state (digital data as output).

Used Components
1. 741
2. BATTERY
3. LOGICPROBE (BIG)
4. POT-HG
5. RESISTOR

SHEET 1 USE COMPARATORS AS ADC

A potentiometer is used in this simulation to control the voltage level outputted to the comparator's
circuit. In addition, voltage division between equal-sized resistors is used to make the voltage input
on the ‘-’ pin of the comparators gradual.

Schematic

Schematic 1

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Results

Figure 1 Figure 2

Figure 3 Figure 4

Figure 5 Figure 6

In the simulation, we have six voltmeters. One voltmeter near the potentiometer is used to measure
the output voltage of the potentiometer. Five voltmeters are used to calculate the voltage on the ‘-’
pin. We can see that the voltage division for the '-' pin uses six equal-size resistors. The voltages
shown in the voltmeters are 0.84, 1.67, 2.5, 3.34, and 4.18 volts. That is because, for voltage
division, we will divide the voltage of the source by the resistors because they are equal in size; thus,
we can obtain:
𝑠𝑜𝑢𝑟𝑐𝑒 𝑣𝑜𝑙𝑡𝑎𝑔𝑒 5
= = 0.8333 ≈ 0.84
𝑛𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑟𝑒𝑠𝑖𝑠𝑡𝑜𝑟𝑠 6
0.84 × 2 = 1.68, 0.84 × 3 = 2.52, 0.84 × 4 = 3.36 0.84 × 5 = 4.2
We can see that the voltage shown in the voltmeters differs slightly from the calculation results. That
is due to the tolerance that the Proteus software introduces for internal component resistances.
The gradual voltage increase allows us to send high outputs one by one. We can see that when the
voltage of the potentiometer is higher than one of the inputs of the '-' pins, the output of the

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comparator becomes high. In Figure 1, all of the outputs are low because the potentiometer's output
voltage is zero. In Figure 2, the first comparator shows high output because the potentiometer output
voltage is 0.85V, while the ‘-’ pin has 0.83V. The same concept applies to Figures 3–6. When the
potentiometer's voltage exceeds the input of the '-' pin, the comparator's output increases.

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B2 DIGITAL TO ANALOG CONVERTER (DAC)

This type of electronic circuit converts digital input to analog. As mentioned before, analog data is
continuous over time, while digital data is discontinuous. In conversion, the digital input is classified
as the most significant bit and the least significant bit. When the most significant bit is high, the
DAC gives a higher voltage than when the least significant bit is high. This procedure can give us a
range of voltage based on the number of bits that are set to high. In this simulation, a DAC0808 IC is
used.

Used Components
DAC0808
LOGICTOGGLE
OPAMP
RESISTOR

SHEET 1 IC DAC0808

The DAC0808 IC is a digital-to-analog converter with an 8-bit resolution (it can accept 8 bits as
input). The output voltage is proportional to the DAC's input voltage.

Schematic

Schematic 1

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Results
Table 3

Schematic Input binary Output Voltage

10000000 0.07

Figure 1

11100000 0.55

Figure 2

11111000 2.42

Figure 3

11111100 4.92

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Figure 4

11111111 15

Figure 5

00000001 10

Figure 6

We can see that in DCA0808, pin A1 is the most significant, while pin A8 is the least significant.
When pin A8 is high (Figure 1), the output voltage is 0.07 volts. When pin A1 is high (Figure 6), the
output voltage reaches 10 volts. We can also observe a gradual increase happen in voltage as we
increase the number of pins that are set to high in Figure 2–5.

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B3 ENCODERS

As discussed before, ADC and DAC are used to mainly convert data from one type to another.
Encoders are digital circuits that convert a set of binary inputs into a unique binary code. Encoders
can be customized using logic gates or manufactured as ICs.
In theory, we can obtain logical equations from truth tables using various methods, such as K-map.
These logical equations are used to transform the input logic states of the variables in the logic
equations into the output desired in the truth table. The circuit designed from these logical equations
can be called an encoder if the truth table represents the conversion of input parameters to unique
code is matching with the circuit output.
In this simulation, we discussed a very specific case in which we desire to convert a sequence of
binary inputs to the binary representation of numbers. This is shown in Table 2:
Table 4

Input Output
Decimal
1 2 3 4 5 6 7 8 9 O1 O2 O3 O4
No.
1 0 0 0 0 0 0 0 0 1 0 0 0 1
1 1 0 0 0 0 0 0 0 0 1 0 0 2
1 1 1 0 0 0 0 0 0 1 1 0 0 3
1 1 1 1 0 0 0 0 0 0 0 1 0 4
1 1 1 1 1 0 0 0 0 1 0 1 0 5
1 1 1 1 1 1 0 0 0 0 1 1 0 6
1 1 1 1 1 1 1 0 0 1 1 1 0 7
1 1 1 1 1 1 1 1 0 0 0 0 1 8
1 1 1 1 1 1 1 1 1 1 0 0 1 9

As we can see, we want an encoder that can convert the inputs in Table 2, which are sequences of
ones (high states), to binary representations of decimal numbers from 1 to 9. When there is one high
state, we want a binary representation of one (Binary: 1000); when there are two high states, we want
a binary representation of two (Binary: 0100); and so on.

Used Components
1. 74LS148
2. AND
3. LOGICPROBE (BIG)
4. LOGICTOGGLE
5. NOR
6. OR
7. XOR

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SHEET 1 LOGIC GATES ENCODER

In this simulation, we have designed a customized encoder based on the above truth table. This
customized encoder is based on the logical equations:
𝐼1 ⊕ 𝐼2 ⊕ 𝐼3 ⊕ 𝐼4 ⊕ 𝐼5 ⊕ 𝐼6 ⊕ 𝐼7 ⊕ 𝐼8 ⊕ 𝐼9 = 𝑂1
Equation 1

(𝐼2 + 𝐼3 ) ⋅ (𝐼4 + 𝐼5 )′ + (𝐼6 + 𝐼7 ) ⋅ (𝐼8 + 𝐼9 )′ = 𝑂2

Equation 2

(𝐼4 + 𝐼5 + 𝐼6 + 𝐼7 ) ⋅ (𝐼8 + 𝐼9 )′ = 𝑂3
Equation 3

𝐼8 + 𝐼9 = 𝑂4
Equation 4

Using logic gates, we can design the encoder based on these logic equations.

Schematic

Schematic 1 Schematic 2

Schematic 4

Schematic 3

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Schematic 5

Resutls
We can see that building a logic circuit from Equations 1-4 can be done directly. Figure 1 is the
circuit taken from Equation 1. Figures 2-4 represent circuits derived from Equations 2-4. All of the
equations are merged in Figure 5. We can see that Figure 5 has a circuit that takes 9 pins as input and
returns 4 pins as output. This is exactly what is required in the truth table (Table 2).
Table 5

Output
Schematic Input
Binary Decimal

1100 0000 0 0100 2

Figure 1

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1111 0000 0 0010 4

Figure 2

1111 1110 0 1110 7

Figure 3

1111 1111 1 1001 9

Figure 4

From Table 3, we can see that the input of ones is being converted to a binary that matches the
number of ones in the sequence. Schematic 5 has been zoomed in to have a better visualization of the
results.

SHEET 2 SUB CIRCUIT ENCODER

As shown before, the logic gate circuit can be designed using logic gates. All those logic gates can be
inserted inside one small component named sub-circuit in Proteus. To make a subcircuit, use
Subcircuit mode from the Proteus icons on the left. Then, we can give it input and output pins for the
sub-circuit mode as well. Then, we can use Terminals Mode to provide input and output terminals
inside the subcircuit. Make sure the names of terminals and pins are the same to make an actual
connection.
Note that sub-circuit internal components can’t be copied from file to file. Plus, if the sub-circuit
name is changed, all its content will be wiped out.

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Schematic

Schematic 7

Schematic 6

Results
In Schematic 6, the four equations 1-4 are designed inside the subcircuits. Each subcircuit has one
equation to represent. The internal components of the four subcircuits in Schematic 6 are shown
below:

Figure 1 Figure 2

Figure 3 Figure 4

We can see that Figures 1–4 have the same circuit as Schematics 1–4 in SHEET 1 LOGIC GATES
ENCODER. The only difference is that in this case, we are using terminals to make the connection.

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In Schematic 7, the whole encoder is designed inside one small subcircuit. This subcircuit's input and
output are the same as the truth table (Table 2) because it has the same design as Schematic 5 in
SHEET 1 LOGIC GATES ENCODER.

SHEET 3 IC74LS148 ENCODER

The IC74LS148 is a priority encoder IC. Priority encoders are used in digital systems to convert
multiple binary inputs into a smaller set of outputs based on the priority of each input. Its primary
function is to encode multiple binary inputs into a priority-encoded output. The device prioritizes the
highest-order active input, providing a binary code that represents the input with the highest priority.
This is particularly useful in applications where it is necessary to determine the most significant
active input among several simultaneously active inputs.
In our case, we want to convert the number of ones in sequence to binary. While IC 74LS148 is not
designed for this purpose, it can give us a conversion from 1 to 7. It can effectively take 7 pins as
input and convert them to 3 pins as output. In our case, the truth table is identical to Table 4 with the
limit of numbers from 1 to 7.
Table 6

Output Input
Decimal
1 2 3 4 5 6 7 O1 O2 O3 O4
No.
1 0 0 0 0 0 0 1 0 0 0 1
1 1 0 0 0 0 0 0 1 0 0 2
1 1 1 0 0 0 0 1 1 0 0 3
1 1 1 1 0 0 0 0 0 1 0 4
1 1 1 1 1 0 0 1 0 1 0 5
1 1 1 1 1 1 0 0 1 1 0 6
1 1 1 1 1 1 1 1 1 1 0 7

Results

Figure 1
Figure 2

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Figure 3 Figure 4

Figures 1-4 show us some variations that are made using IC74LS148. We can see that Figure 1 has
the input of 0000 01 and the output of 001 (Decimal 1). Figure 2 has an input of 0001 11 and an
output of 011 (Decimal 3). We can see that the number of ones is the same as the binary number. In
Figure 3 and Figure 4, we can see also that the number of ones is the same as the binary number.
This is the same output as required in Table 4.

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B4 DECODERS

The encoder in B3 is discussed before as a circuit that converts binary input into a unique code. A
decoder is a circuit that converts or translates a code into a set of signals. To understand decoders,
binary-coded decimal (BCD) ICs are used in this simulation. BCD ICs are circuits that convert
binary input to binary output that can be displayed on a 7-segment display.
The 7-Segment display is one of the most basic displays that can show numbers from 0 to 9 (from
0000 to 1001). The 7-segment display contains seven LEDs. There are two types of 7-Segment
displays:
1. Common Cathode: In this type, the 7-segment LEDs are grounded to the same ground, and
the input pin receives data input ‘High’ to be ON.
2. Common Anode: In this type, the 7-segment LEDs share the same ‘High’ state, and the input
pins receive data input ‘Low’ to be ON.

This simulation uses a BCD to 7-segment decoder to show how a binary input can be decoded into a
signal.

Used Components:

1. 7SEG-COM-ANODE
2. 7SEG-COM-CATHODE
3. 4511
4. 7447
5. 7448
6. BUTTON
7. LOGICTOGGLE
8. RESISTOR
9. VSOURCE

SHEET 1 COMMON CATHODE IC4511

IC 4511 is used to convert 4 binary inputs to 7 outputs that can be used with the Common Cathode 7-
Segment display to show numbers in decimal. IC 4511 has A, B, C, and D pins to take the binary
input. It uses QA and QG to produce the output. LT and BI are set to high input, while LE is set to
low input.

Schematic

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Schematic 1

Results

Figure 1 Figure 2

The above circuit shows that pins A, B, C, and D are used to give the binary input. LT and BT are set
to high, while LE is set to low. Two variations have been chosen to show us how IC4511 works. In
Figure 1, the input is 0101 (Decimal 5), and the display shows 5. In Figure 2, the input is 1000
(decimal 8), and the display shows 8. We can see that the binary input is decoded into a signal that
can be displayed in the 7-segment. A common cathode type of 7-Segment is used because we see
that the output of IC4511 is high to make the 7-Segment ON.

SHEET 2 COMMON ANODE IC7447

IC7447 is used to convert 4 binary inputs to 9 outputs that can be used in the Common Anode 7-
Segment display. IC7447 has A, B, C, and D pins to give the binary input. It uses pins from QA to
QG to provide the output. Pins BI, RBI, and LT are set to high in this decoder.

Schematic

Schematic 2

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In Schematic, we can see that IC7447 takes the input binary but gives output states, which are the
exact reverse states of Figure 1 in Sheet 1. That is because this IC is used with Common Anode 7-
Segment display. The input however is 0101 (decimal 5) which is the same as Figure 1 in Sheet 1.
The resistors in Schematic 2 are used to pull the input binary to be low if the pushbutton is not
clicked. They are called pull-down resistors. Using pull-down resistors is essential experimentally
but in the simulation sometimes, it can work without them as shown in Sheet 1.

SHEET 3 COMMON CATHODE IC7448

The IC7448 is the same as the IC4511. It is used in this simulation to show how different
manufactured ICs that are in Proteus can do the same job. In real-life applications, datasheets of
different ICs could have some unique properties or improvements, even if they do the same task.
In IC 7448, we have pins A, B, C, and D to take the binary input. It uses QA and QG to produce the
output. BI, RBI, and LT are set to high.

Schematic

Schematic 3

We can see that Schematic 3 has the same output as Figure 1 in Sheet 1. Pulldown resistors are used
here, but not with Schematic 1, because it works in simulation just fine. However, they should be
used in Schematic 1 as well in the practical experiment, but these details are being neglected as the
target of this guide is to show different electronic circuits in a simple manner using Proteus software.

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B5 ANALOG INPUT TO DISPLAY

This simulation uses several circuits that we have built in B1-B4 simulations, which are:

1. B1/Sheet 1: Comparators
2. B3/Sheet 2: Subcircuit 9 to 1 Encoder
3. B3/Sheet 3: IC74148 7 to 1 Encoder
4. B4/Sheet 1: IC4511 BCD Common Cathode 7-Segment Decoder

SHEET 1 SUBCIRCUIT 9 TO 1 ENCODER

This simulation is a complete circuit whose task is to show how analog input can be initially
converted to digital. After that, this digital input can be encoded into a unique code, which is a
representation of numbers in binary from 9 to 1. Then, the unique code can be decoded to be a signal
that can be shown as a number on a display.

Schematic

Schematic 1

Results

Figure 1: 37% Potentiometer Figure 2: 85% Potentiometer

We can see that this circuit initially shows the number zero. The more we increase the voltage
passing through the potentiometer, the higher the number. In Figure 1, 37% will pass through the
potentiometer. This makes the number 3 appear on the display. When the percentage was increased

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in Figure 2 to 85%, the number 8 appeared in the display. This shows that we can control the number
being displayed in the 7-segment display by controlling the potentiometer.

SHEET 2 IC74148 7 TO 1 ENCODER

This simulation is more limited, as it only displays numbers from 1 to 7. That's because IC74148 is
limited to this range, as shown in B3/Sheet 3.

Schematic

Results

Figure 1: 37% Potentiometer Figure 2: 85% Potentiometer

We can see that when the potentiometer is set to 37%, the number being displayed is 3. That is
similar to the results in Sheet 1. However, when the potentiometer is set to 85%, the number being
displayed is 7. That differs from Sheet 1, as the displayed number is 8. That is because this circuit
has a maximum range of 7, as it can only encode numbers into a maximum of 3 binary.

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B6 FLIP-FLOPS AND LATCHES

Flip-flops and latches are digital circuits used in sequential logic to store and transfer binary
information.

Used Components
1. 7402
2. 7473
3. 7474
4. AND
5. CLOCK
6. LOGICPROBE (BIG)
7. LOGICTOGGLE
8. NAND
9. NOT

SHEET 1 SR LATCH

An SR latch, also known as a set-reset latch or a flip-flop, is a simple digital circuit that can store one
bit of information. SR latches can be built from “NOR” or “NAND” gates.
If the latch allows data to pass through when the clock signal has a value of 1, we call it an active
high latch. The Active High Latch is built using a “NOR” gate. Alternatively, if the latch allows data
to pass through when the clock signal is 0 and holds when the clock is 1, we call it an Active Low
Latch. The Active Low Latch is built using a “NAND” gate.
It can be said that pins S (set) and R (reset) control the output of Q and Q’.

SR Latch Truth Table

Table 7

NOR Active High Latch NAND Active Low Latch

S R Q Q’ S R Q Q’
Latch Latch
0 0 0 0 1 1
(1/0) (1/0)
0 1 0 1 0 1 1 0
1 0 1 0 1 0 0 1
Latch Latch
1 1 0 0 1 1
(1/0) (1/0)

In Table 5, the state in Active High Latch when both S and R are low is named Latch State. This
state means that the circuit will make the last binary state stored in Q and Q’ remain the same,
meaning that the latch is currently storing a logic state. If the simulation initially started with this

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latch state, it will give an error. This error happens because Q and Q’ will alternate between high and
low states so fast without remaining in one state. A similar concept applies to the latch state in Active
Low Latch when both S and R are set to high.

Schematic

Schematic 1: Active High SR Latch Schematic 2: Active Low SR Latch

Results

Active High Latch

Figure 1 Figure 2 Figure 3

Figure 4 Figure 5 Figure 6

In Schematic 1, the "NOR" gate, Active High Latch, is present. This latch allows data to be stored
when both S and R pins are initially high. Then, you can use S and R pins to set the data needed to be
stored in Q and Q’. After that, make both S and R low to keep the stored states of Q and Q’. If you
try to simulate with initially “S” and “R” low (latch state) in an active high latch, you will get an
error.
Figures 1–3 show us how to store Q as low and Q’ as high. Initially, the latch input pins S and R are
high because the latch is Active High Latch. After that, the Set pin (S) is inputted with a low state,
which sets the Q pin to low and the Q’ to high. Then, both S and R pins are set to a low state, which
makes the last state of Q and Q’ (Q pin: low and Q’: high) remain the same. A similar approach is
done in Figures 4–6, but to store Q as high and Q’ as low. Setting Q as high and Q’ as low in Figures
4–6 was done by making the S input pin as high and the R input pin as low in Figure 5.

Active Low Latch

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Figure 7 Figure 8 Figure 9

Figure 10 Figure 11 Figure 12

In Schematic 2, the "NAND" gate Active Low Latch is present. This latch allows data to be stored
when both S and R pins are initially low. Then, you can use S and R pins to set the data needed to be
stored in Q and Q’. After that, make both S and R high to keep the stored states of Q and Q’. If you
try to simulate with initially “S” and “R” high (latch state) in an active low latch, you will get an
error.
Figures 7-9 show us how to store Q as low and Q’ as high. Initially, the latch input S and R pins are
low because the latch is Active Low Latch. After that, the Set pin (S) is inputted with a low state,
which sets the Q pin to low and the Q’ to high. Then, both S and R pins are set to a high state, which
makes the last state of Q and Q’ (Q pin: low and Q’: high) remain the same. A similar approach is
done in Figures 10–12, but to store Q as high and Q’ as low. Setting Q as high and Q’ as low in
Figures 10–12 was done by making the S input pin as high and the R input pin as low in Figure 11.

SHEET 2 GATED SR LATCH

We can build this latch using ‘NOR’ or ‘NAND’ gates. Both of these types of latches in gated SR
latches are considered active-high latches. This latch has an additional input pin named Enable that
can be used as a switch to turn the latch on or off. Thus, this latch has three pins, which are the
enable (E), set (S), and reset (R) pins. When the Enable pin is low, the latch enters a latch state.

Gated SR Latch Truth Table

Table 8: Gated SR Latch Truth Table

E S R Q Q’
0 X X Latch (1/0) Latch (1/0)
1 0 0 Latch (1/0) Latch (1/0)
1 0 1 0 1
1 1 0 1 0
0 (NOR Type)
1 1 1
1 (NAND Type)

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Schematic

Schematic 3 Schematic 4

Results

Figure 1 Figure 2 Figure 3

Figure 4 Figure 5 Figure 6

Figure 7 Figure 8 Figure 9

Figure 10 Figure 11 Figure 12

Figures 1–3 demonstrate how the gated SR latch can store data in the same way the active high latch
does when the E pin is high. Figures 4–6 show that S and R pins do not affect Q and Q’ when E is
low. Figures 7-9 demonstrate how the gated SR latch can store data in the same way that the active
high latch does when the E pin is high. Figure 10-12 shows us that S and R pins do not affect Q and
Q’ when E is low.
We can see the difference between ‘NOR’ and 'NAND'. Gated SR latches when both S and R are
high and Q and Q’ are high in the ‘NAND’ one, as shown in Figure 7. In contrast, when both S and R
are high in the ‘NOR’ one, Q and Q’ are low, as shown in Figure 1.

SHEET 3 D LATCH

A gated data latch (D) is a type of latch that can store one bit of memory. If pin D is high, Q is high,
and Q’ is low, If pin D is low, Q is low, and Q’ is high, There are two types of D-latches:
1. Gated D latch, which has pin Enable (E). When pin E is low, the latch turns off. When E is
high, the latch becomes on, and both pins S and R can affect Q and Q’.

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2. Clocked D latch, which has pin Clock (C). If pin C has a stable input (high or low state), the
latch output is not affected by pin D. When pin C is alternating from low to high, pin D can
now control the output of pins Q and Q’.

Clocked D Latch is also called D Type Flip Flop.

Schematic

Schematic 5: Gated D Latch Schematic 6: Gated D Latch

Schematic 7: Clocked SR Latch/ D Type Flip Flop

Results

Gated D latch

Figure 2 Figure 3
Figure 1

Figure 5 Figure 6
Figure 4

Figure 8 Figure 9
Figure 7

We have two ways of making a Gated D latch shown in Schematic 5 and Schematic 6. Both
schematics have the same behavior.

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When E is high, pin D will have the same state as pin Q, as shown in Figures 1, 4, and 7. Pin Q’ will
always be the opposite state of Q. When E is low, as shown in Figures 2–3, the gated D latch enters a
latch state, in which it keeps the state of Figure 1 no matter how pin D is. The same behavior is
shown in Figures 5–6, as the output states are the same as in Figure 4, no matter what the state of pin
D is. Similarly, the output state of Figures 8–9 is the same as Figure 7, no matter what the state of D
is.

Clocked D Latch (D Type Flip Flop)

Figure 10 Figure 11
Figure 12

Figure 13 Figure 14 Figure 15

Figure 16 Figure 17 Figure 18

In Schematic 7, we see that the clocked D latch is connected to a clock, which will alternate an input
between low and high. This IC latch is coded IC7474. This IC has three pins that can control the
output states of Q and Q', which are pins D, S, and R. Note that pin Q’ will always be in the opposite
state of Q.
We can see in Figure 10 that pin D is low while Q is high because the transition from low to high
hasn’t happened yet. After the transition occurred in Figure 11, we see that both D and Q are low
now. Figure 12 shows us that after the transition occurred and both D and Q had the same state, the
clock did not affect the state of Q. Therefore, we can consider the clock as an enable pin that can
control when the data can be passed from the Data (D) pin to Q.
A similar concept applies in Figures 13–15 when we want to make both D and Q high. Initially, D is
high, while Q is low because the transition from low to high hasn't yet occurred. Following the
transition in Figure 14, we see that both D and Q are now high. Figure 15 shows us that after the
transition occurred and both D and Q had the same state, the clock did not affect the state of Q.
Figures 16–17 show us how pins S and R can affect the output. Figure 16 shows that if S is low, it
will force Q to be high, no matter how D or C are. Figure 17 shows that if R is low, it will force Q to

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be low, no matter how low D or C are. If both S and R pins are low, it will make both Q and Q’ high,
which is an invalid state as shown in Figure 18.

SHEET 4 FLIP FLOP

Similar to the latch, a flip-flop is used to store one bit of memory data. It has two main types:
1. D-type flip flop (IC 7474)
2. JK-type flip flop (IC 7473)

The D-type flip flop is discussed in Sheet 3 as a Clocked D latch. In this simulation, only a JK-type
flip-flop will be discussed.

Schematic

Schematic 8

Results
This type of flip flop has four pins to control the output (Q and Q’) which are J, K, CLK, and R.

Figure 1 Figure 2 Figure 3

Figure 4 Figure 5 Figure 6

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Figure 7

Figures 1–6 demonstrate that J and K pins can control the output when the transition in pin CLK
occurs from high to low.
Figure 1 shows us that output Q is not affected by pin J initially. After the transition occurs from
high to low in Figure 2, we see that pin Q becomes high. After that, when we made both J and K pins
low, the flip flop entered a hold state in which the last previous states of output Q and Q’ were
maintained.
Figure 4 shows us that output Q is not affected by pin K initially. After the transition occurs from
high to low in Figure 5, we see that pin Q becomes low. After that, when we set both the J and K
pins low in Figure 6, the flip flop entered a hold state.
Figure 7 shows us that if pin R is low, it will force the output state of Q to be low no matter how the
states of the J, K, and CLK pins are.
In short, pin J drives Q to be high, and pin K drives Q to be low after the transition from high to low
occurs. The reset pin (R) forces output Q to be low. If both J and K are high, the output Q will
alternate between high and low states each time the transition from high to low occurs.

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B7 COUNTERS

A counter IC is an electronic device that is designed for counting external input clock pulses. There
are many types of counters. Some of them are:

1. Asynchronous (Ripple) Counters

2. Synchronous counters
3. Asynchronous Counters D-type Flip-Flop
4. Decade counter
5. Ring counter

Used Components
1. 7SEG-COM-CATHODE
2. 4017
3. 7448
4. 7474
5. 74107
6. AND
7. BUTTON
8. CLOCK
9. LOGICPROBE (BIG)
10. LOGICTOGGLE
11. VSOURCE

SHEET 1 ASYNCHRONOUS (RIPPLE) COUNTERS

This counter uses a series of JK-type flip flops to count the number of pulses in the signal and output
its binary value. They provide sequential binary outputs in response to clock pulses, with each stage
transitioning independently.
This type is called asynchronous because not all the flip-flops are directly controlled by the clock
signal. Only the first flip-flop is clocked, and the rest are controlled sequentially.

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Schematic

Schematic 1

Results and Discussion

In Schematic 1, we see that the circuit initially starts with binary 0000, and the 7 segments show 0.
After each time the clock signal has transitioned from high to low, the counter goes up by one
number.

Figure 1 Figure 2

After simulating for some time, the counter will go 0000, 0001, 0010, 001, 0100, and so on. In
Figure 1, we see that the binary 0100 (Decimal 4) will be shown on the counter. A BCD decoder is
used to show the decimal value on a 7-segment display.
Because 4 flip flops can give 4 binary values, which are up to the decimal number 15, this circuit will
only show numbers up to 9 correctly, then it will make random LEDs in the 7-segments high, as
shown in Figure 2. These random values will continue until the counter returns to zero after reaching
the number 15.

SHEET 2 SYNCHRONOUS COUNTERS

In this counter, the input of each flip-flop clock is controlled directly by the original clock signal.

Schematic

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Schematic 2

This counter will work exactly as the counter in Sheet 1.

SHEET 3 ASYNCHRONOUS COUNTERS D-TYPE FLIP FLOP

This type of counter uses a D-type flip-flop.

Schematic

Schematic 3

This counter will give the same output as Sheet 1.

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SHEET 4 DECADE COUNTER

The decade counter generates high states sequentially. For this simulation, Decade Counter IC4017 is
used.

Schematic

Schematic 4

Results

Figure 1 Figure 2 Figure 3

We can see that IC4017 has 10 output pins, from pin Q0 to pin Q9. The decade counter will initially
start with Q0 high and all other output pins low, as shown in Schematic 4. Then, it will raise Q1 and
lower all other pins, as shown in Figure 1. This will continue sequentially, as shown in Figures 2 and
3, until the counter reaches Q9 as high. After that, it will go back to Q0 being high and all other pins
are low.
Decade counters don't return actual numbers, unlike previous counters. It just starts with Q0 high and
all other pins low, then Q1 high and all other pins low, and so on.

SHEET 5 RING COUNTER

A Ring counter is a type of shift register circuit where the output of the last flip-flop is connected to
the input of the first flip-flop in the circuit, forming a closed loop or ring.

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Schematic

Schematic 5

Results

Figure 1 Figure 2 Figure 3

This type of counter is used to show a binary of high in circular order, similar to the decade counter.
In Schematic 5, we see that we have a button connected to the first D pin in the D-type Flip Flop.
This button is used to initialize the counter. After initialization, as shown in Figure 1, the Ring
Counter starts with the first D-type flip flop sending high data output, while all other flip flops send
low data output. Then, Figure 2 shows that the second D-type flip flop sends data high while all other
flip flops send information low. The process continue in Figure 3, with the third flip-flop sending the
high data. After the fourth flip-flop becomes high, the counter will loop again from the first counter.
This counter has an advantage over the Decade Counter as its output pins are not fixed and can be
adjusted as needed by increasing or decreasing the number of flip flops.

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B8 SHIFT REGISTERS

Shift registers are used for the storage and movement of data. They use flip-flops to store and move
data in serial or parallel order. There are many types of shift registers. Some of these types are:

1. The Serial-In, Serial-Out Shift Register (SISO)

2. The Serial-In, Parallel-Out Shift Register (SIPO)
3. The Parallel-In, Serial-Out Shift Register (PISO)
4. The Parallel-In, Parallel-Out Shift Register (PIPO)

Used Components
1. 74HC595
2. 7474
3. 74165
4. BUTTON
5. CLOCK
6. LED-BLUE
7. LOGICPROBE (BIG)
8. LCGCTCGGLE
9. RESISTOR

SHEET 1 SERIAL-IN, SERIAL-OUT SHIFT REGISTER (SISO)

This shift register stores data from serial input and gives the output of the data in serial. It uses a
series of D-type flip flops that take an input of one bit and store it in one of its flip flops once the
clock goes from low to high. The number of flip-flops determines the number of bits that can be
stored in the circuit. The speed of the clock determines the rate at which the data is stored and
transmitted.

Schematic

Schematic 1

Results

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Figure 1 Figure 2

Figure 3

In Schematic 1, we used four flip-flops, which can store 4 bits of data. The D pin is used to input the
data. To give proper input, give the input as high or low; then, wait for the transition of the clock
from low to high; after that, give the second input, and so on. In Figure 1, we see the input data was
1010.
Making pin S low will force all output data to be high, as shown in Figure 2. Making pin R low will
force all data to be low, as shown in Figure 3.

SHEET 2 SERIAL-IN, PARALLEL-OUT SHIFT REGISTER (SIPO)

This shift register takes the input data as serial and gives the output in parallel form. Here,
IC74HC595 is used as the shift register. It works by adjusting the following pins:

1. Set pin MR high and OE low.

2. Initially, set ST_CP to low.
3. If DS is high and SH_CP is clicked, one bit will be stored.
If DS is low and SH_CP is clicked, 0 bits will be stored.
This IC can store a total of 8 bits.
4. After 8 bits are inputted to the IC, set ST_CP high, and the stored data will be viewed from
pin Q0 to Q7.

Schematic

Schematic 2

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Results

Figure 1

Figure 2 Figure 3 Figure 4

Figure 5

Figure 6 Figure 8
Figure 7 Figure 9

In Figure 1, we see that to work with the IC74HC595 shift register, you need to make MR high and
OE low. Then, initially, make SH_CP, DS, and ST_CP in low state. To store and move one bit of
data, you need to do the following:
To store a bit of high state, make DS high, as shown in Figure 2. Then, make the SH_CP transition
between high and low states by making the SH_CP high as shown in Figure 3, then low as shown in
Figure 4. Make also DS low as shown in Figure 4. Finally, set ST_CP high to display the stored data,
as shown in Figure 5. In Figure 5, we can see that Q0 is storing a high-state input.
To store a bit of a low-low state, make DS low, as shown in Figure 6. Then, make the SH_CP
transition between high and low states by making the SH_CP high, as shown in Figures 7, and then
low, as shown in Figure 8. Finally, set ST_CP high to display the stored data, as shown in Figure 9.
In Figure 9, we can see that Q0 is storing a low-state input while the previous high-state is now
passed to Q1.
By continuing this procedure, 8 bits that are inputted in series can be stored and moved as outputs in
parallel.

SHEET 3 PARALLEL-IN, SERIAL-OUT SHIFT REGISTER (PISO)

The PISO shift register takes the input from 8 pins and gives the output from one pin serially. In this
simulation, IC74165 is used. It operates by adjusting the following pins:

1. Set the data you want to pass in from pins D7 to D0. The data will be shifted from D7 to D0.
2. Use a clock to determine the speed at which the data is transmitted.
3. Make SH/LD (Shift/Load) high, and then the data will be shifted and loaded to pin SO.

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4. Make SH/LD low to pass another sequence of data, and then make it high again to shift it to
Pin SO.

Schematic

Schematic 3

Results

Figure 1 Figure 2

We can see that in Figure 1, the input data from pins D7 to D0 is given in a specific sequence. In
Figure 2, the SH/LD pin is set to high. This will make the LED light up whenever a high input is
passed from the sequence in D7 to D0 pins. In Figure 2, an LED is used to view the output. It will be
01010111 after pin SH/LD is set to high. The speed of passing the data is determined by the
frequency of the clock.

SHEET 4 PARALLEL-IN, PARALLEL-OUT SHIFT REGISTER (PIPO)

This shift register uses a series of D-type flip-flops that are connected separately. Each flip-flop
passes one piece of data from pin D (input parallel) to pin Q (output parallel).

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Schematic

Schematic 4

Results

Figure 1 Figure 2

To work with the PIPO Shift Register, initially set the sequence of data you want to pass in pins D1
to D4, as shown in Figure 1. The data will not be passed to the output unless the transition of the
clock occurs from a low to a high state, as shown in Figure 2. Figure 2 shows us that the data is
already being passed from each D pin to the Q pin in each flip-flop. The speed of this passing
process is determined by the frequency of the clock.

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B9 MULTIPLEXERS AND DEMULTIPLEXERS

A multiplexer (Mux) is an IC used to select input pins from many inputs and give its binary states as
output.
A demultiplexer (Demux) is an IC used to select one output from many outputs and give its binary
states as input.

Used Compoenets
1. 74153
2. 74155
3. 74157
4. CLOCK
5. LOGICPROBE(BIG)
6. LOGICTOGGLE
7. NOT
8. RESISTOR

SHEET 1 2X1 MULTIPLEXER

This multiplexer has two input pins, one selection pin, and one output pin. IC74157 is used in this
simulation, which has four 2x1 multiplexers inside it. Pins A and B are the input pins. Pin A’/B is
used to select between inputs of A or B. If pin A'/B is low, pin A will be the output. If pin A/B is
high, pin B will be the output. Y1, Y2, Y3, and Y4 are the outputs corresponding to their A and B
inputs.

Schematic

Schematic 1

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Results

Figure 1 Figure 2

In Figure 1, we can see that the sequence 1010 is used in 1A-4A pins, while 0101 is used in 1B-4B
pins. A’/B is set to low in Figure 1. Thus, the 1A-4A sequence will be outputted in 1Y-4Y, as shown
in Figure 1. In Figure 2, the 1B-4B sequence (0101) will be outputted because pin A’/B is set to high.

SHEET 2 4X1 MULTIPLEXER

This multiplexer has a similar concept as the 2x1 mux, but here it has 4 input pins, two selection
pins, and one output pin. For this simulation, IC74153 is used, which consists of two 4x2
multiplexers.

Schematic

Schematic 2

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Results

Figure 1 Figure 2

Figure 3 Figure 4

In Figures 1–4, the sequence 0110 is used for pins 1x, and the sequence 1001 is used for 2x pins. In
IC74153, we also have two selection pins and two output pins.
Figure 1 shows that pins A and B are low. This means that 1x0 and 2x0 states (0 and 1, respectively)
will be outputted. We can see that the 1x0 state is 0, which is outputted in 1Y. Additionally, the 2x0
state is 1, which is outputted in 2Y.
In Figure 2, pin A is high, and pin B is low. This means that 1x1 and 2x1 states (1 and 0,
respectively) will be outputted. We can see that the 1x1 state is 1, which is outputted in 1Y.
Additionally, the 2x1 state is 0, which is outputted in 2Y.
In Figure 3-4, the same concept as in Figure 1-2 applies, as pins A and B are used to select the input
that will be shown in pins 1Y and 2Y.

SHEET 3 TIME DIVISION MUX

This mux is used to combine two input binary signals into one signal based on the frequency of a
clock signal.

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Schematic

Schematic 3

Results

Figure 1

The clock signal has a frequency of 1/5 Hz. This means that the clock signal will be low for 2.5s and
high for 2.5s. We can see the clock signal's high and low states in Figure 1 (blue color graph).
From Figure 1 in the yellow color graph, when the clock is low, we see that the low-frequency signal
is being output. When the clock signal is high, we see the high-frequency signal being output.

SHEET 4 1X4 DEMULTIPLEXER

This demultiplexer uses one input pin, four output pins, and two selection pins. In this simulation,
IC74155 is used. It consists of two 1x4 Demux; one Demux passes the same input to the output pin,
and another Demux makes a conversion from high to low or from low to high for the input before
passing it to the output pin.

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Schematic

Schematic 4

Results

Figure 1 Figure 2

Figure 3 Figure 4

We can see that IC74155 has two input pins, which are 1C and 2C. There are two selection pins: A
and B. The output pins are 1Y0-1Y3 and 2Y0-2Y3. This means that we have one Demux from input
1C to 1Y0–1Y3 and another Demux from input 2C to 2Y0–2Y3. The dimux of input 1C makes the
conversion to the state from high to low or low to high before passing it to output pins 1Y0-1Y3.
In Figure 1, pins A and B are low, indicating that 1Y0 and 2Y0 will receive the input states 1C and
2C. Figure 1 shows that the input of 2C is low, similar to the output of 2Y0. We also see that the
input of 1C is high, while the output of 1Y0 is low because of the conversion mentioned earlier.

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In Figure 2, pin A is high and pin B is low, which means that 1Y1 and 2Y1 will receive the input
states of 1C and 2C. Figure 2 shows that the input of 2C is low, similar to the output of 2Y1. We also
see that the input of 1C is high, while the output of 1Y1 is low because of the conversion.
In Figure 3 and Figure 4, a similar concept applies when we want to pass data from input pins 1C and
2C to output pins 1Y2, 1Y3, 2Y2, and 2Y3. To achieve this, we can change the selection pin states of
A and B pins.

SHEET 5 TIME DIVISION MUX DEMUX

In this simulation, the Time Division Mux in Sheet 3 is used with a Demux IC.

Schematic

Schematic 5

Results

Figure 1

We can see in Schematic 1 how a Demux is designed in the circuit output. In Figure 1, the yellow
graph shows the Time Division Mux signal, which is a combination of both the high- and low-
frequency input signals. We can also see that the blue graph is the low-frequency output, while the
red graph is the high-frequency output.

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We can see that both blue (low frequency) and red (high frequency) outputs have constant high states
(discountability in the signal), caused by limitations in our circuit design. These limitations can be
overcome by further development in the circuit design. However, because our target is to show the
basic concepts of Mux and Demux, this task can be left for the reader to figure out how to make the
appropriate changes!

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B10 MEMORY

We have seen in the previous simulation how shift registers store and move data. However, to have
an actual memory, we need to be able to store a specific binary sequence in a known location. Thus,
memory is used for this task. Memory is an IC used to store binary data. It associates each piece of
data with an address. Thus, in order to read or write any data, you must first access the data's address.
Memory ICs are complex and mostly implemented with microcontrollers. However, for this
simulation, a very simple memory IC is introduced.

Used Compoenets
1. 74LS189
2. LED-RED
3. LOGICTOGGLE
4. NOT
5. RESISTOR

SHEET 1 IC74LS189 64-BIT RANDOM ACCESS MEMORY

This memory is IC74LS189. It has four pins for the address and four other pins for binary data input.
We can switch between read and write modes using the WE pin. The output of this IC is the input's
inverted state.

Schematic

Schematic 1

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Results

Figure 1 Figure 2

Figure 3 Figure 4

We can see that when the WE pin is low, we are in write mode. In Figure 1, we write the binary
sequence 0101 at the address 0000. In Figure 2, we write the binary sequence 0111 at the address
1000.
After that, the WE pin is set to high in Figure 3 and Figure 4. In Figure 3, we read the data from
address 0000 as 0101, which is the same as what we inputted in Figure 1. In Figure 4, we read the
data from address 1000 to be 0111, which is the same that we inputted in Figure 3.
You can do this for the 64 available addresses in this IC. This means that this IC is capable of storing
4 bits of data in 64 memory addresses.

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B11 IC 555 TIMER

The IC555 timer is a widely employed IC used in electronics due to its capability to generate precise
time delays, oscillations, and pulses. It has so many applications and uses. In this simulation, three
main operating modes will be introduced, which are:

1. Astable multivibrators: generating square waves in oscillators and clocks.

2. Monostable multivibrators: producing precise time delays in electronic circuits like timers
and pulse generators.
3. Bistable Multivibrators: used in memory and flip-flop applications in digital systems.

Used Components
1. 555
2. BUTTON
3. CAP
4. LED-RED
5. RESISTOR
6. VSOURCE

SHEET 1 ASTABLE MULTIVIBRATOR

This is an oscillator that generates a square wave signal from the DC input voltage. It uses the IC555
timer. In this mode, the 555 timer operates without external triggering pulses. The output
continuously switches between high and low states, producing a square-wave signal. By adjusting the
values of resistors (R1 and R2) and capacitors (C), you can control the frequency and duty cycle of
the output waveform.
The duty cycle is the percentage in which the signal remains in a high state within one period.

Schematic

Schematic 1

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Results

Figure 1

Figure 1 shows that the oscilloscope's output is a square wave signal with an almost 50% duty cycle.
This means that 50% of the signal is high, and 50% is low.

SHEET 2 MONOSTABLE MULTIVIBRATOR

This one is not typically an oscillator, as it generates a pulse (disturbance) if a trigger (button) is
used. In this model, the 555 timer can be configured as a monostable multivibrator to generate a
single pulse of a specified duration in response to an external trigger.

Schematic

Schematic 2

Results

Figure 1: No trigger is applied Figure 2: Quick trigger is applied

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Figure 3: Constant high trigger

Figure 4: Low state trigger after high one

In Schematic 2, if the button is clicked, the signal in the oscilloscope will get a pulse and then slowly
return to its stable state.
We see in Figure 1 that the signal will remain low as long as no trigger is applied. In Figure 2, we see
that the signal was low until it received a quick trigger pulse from the button. This caused the signal
to reach a high state and then return to a low state.
In Figure 3, the button is closed. This made the signal go to high but then gradually went back to a
stable zero-voltage state. In Figure 4, when the opposite of Figure 3 is done, which is making the
trigger low, the signal is reversed, giving a negative waveform, and then gradually going to the zero-
voltage stable stage again.

SHEET 3 BISTABLE MULTIVIBRATOR

This one works by two triggers. One trigger makes the output high and another trigger makes the
output low.

Schematic

Schematic 3

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Results

Figure 1 Figure 2

Figure 1 shows us that when the low-state trigger is applied, the LED is low (off). When a high-state
trigger is applied, the LED becomes high (on).

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B12 OSCILLATORS AND CLOCK

An oscillator is an electronic circuit or device that generates repetitive oscillating signals, typically in
the form of electrical waveforms such as sine waves, square waves, or triangular waves.
A clock is a device or signal that generates regular pulses or ticks at a constant rate. These pulses
serve as a timing reference for synchronizing various operations within a system, such as CPU
instructions, data transfers, or other time-sensitive processes.
There are so many types of oscillators and clock circuits. In this simulation, three basic circuits will
be introduced.

Used Components
1. 2N3904
2. CAP
3. INDUCTOR
4. LM741
5. LOGICPROBE
6. POT-HG
7. RES
8. RESISTOR
9. VSINE
10. VSOURCE

SHEET 1 HARTLEY OSCILLATOR

This oscillator circuit is used to generate an AC sinusoidal signal from a DC source.

Schematic

Schematic 1

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Results

Figure 1

We can see in Figure 1 that the output of the Hartley Oscillator is a sinusoidal waveform.

SHEET 2 OP-AMP SCHMITT TRIGGER OSCILLATOR

This oscillator generates square-wave output from an AC sinusoidal input. The output wave is typical
for digital applications and can be used as a clock similar to the clock signal provided by the IC555
timer shown in the B11/Sheet 1 Astable Multivibrator simulation.

Schematic

Schematic 2

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Results

Figure 1

We can see in Figure 1 the output (blue graph) is a square wave coming from the sine wave input
(yellow graph). However, the duty cycle for this signal is purely not 50% as the signal remains in one
period in a high state more than in a Low state. The duty cycle can be adjusted by changing the size
of resistors in schematic 2.

SHEET 3 WEIN BRIDGE OSCILLATOR

This bridge is used to give a square wave output from the DC source input.

Schematic

Schematic 3

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Results

Figure 1

We can see in Figure 1 that we have an output of a signal that gives high and low states repetitively
coming from the Wein Bridge. However, the signal is making some noise due to limitations in the
Wein Bridge Circuit, but it can still be used as a clock signal. The parameters of the wave
(amplitude, frequency, etc.) can be adjusted by adjusting the parameters of the circuit (resistors and
capacitors) in Schematic 3.

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REFERENCES

[1] M. Tooley, “Electronic Circuits: Fundamentals and Applications, Third Edition.”

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