Scribd
Upload
82 views12 pages

3-Bit Synchronous Down Counter Design

This is a presentation containing concise information about synchronous counters, this lecture slide was prepared by a professor from IIIT institute.

Uploaded by

imanonymousdude.12345
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
82 views12 pages

3-Bit Synchronous Down Counter Design

This is a presentation containing concise information about synchronous counters, this lecture slide was prepared by a professor from IIIT institute.

Uploaded by

imanonymousdude.12345
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Synchronous (Parallel) Counters

 Synchronous (parallel) counters: the flip-flops are


clocked at the same time by a common clock pulse.
 The clock inputs of all the flip-flops are connected
together so that the input clock signal is applied
simultaneously to each flip-flop.

1
2
4-bit Ring Counter
A single 1 is made to circulate around the
counter it is called ring counter. It has 4 states,
so Mod-4 ring counter

3
4-bit Ring Counter timing diagram

It is simple circuit, Only D flip flop is required.


Only four of the 16 states are being utilized.

4
4-bit Jonshon Counter

End of segment

5
4-bit Jonshon Counter

It is also called Switch-tail ring counter. It has 8


states, so Mod-8 counter.
Advantage :it requires only half number of flip
flops that of a ring counter uses, to design the
same Mod.

6
3-bit Synchronous down counter with JK flip-flops

7
3-bit Synchronous down counter with JK flip-flops

8
3-bit Synchronous down counter with JK flip-flops

9
3-bit Synchronous down counter with JK flip-flops

10
3-bit Synchronous down counter with JK flip-flops
(contd.)

11
Sequential Circuit Design (cont’d)
n A more general counter
design
u Does not step in
sequence

0→3→5→7→6→0

n Same design process


n One significant change
u Missing states
v 1, 2, and 4
v Use don’t cares for
these states

You might also like