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Problems in Chapter 11

Microelectronic circuits problem

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96 views7 pages

Problems in Chapter 11

Microelectronic circuits problem

Uploaded by

ohdongyeol752
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF or read online on Scribd
se 566 Chapter 11. Frequency Reso” 63, we wish t0 GD 11.2. In the circuit of Fis. MEE NC Griz achieve a -3-dB bandwi oo with a load capacitance of 20F if is the maximum (low-frequency) fi that can be achieved with 2 PON®S &, sipation of 2mW? Assume Vec = 25 and neglect the Early effect and ol capacitances. 11.8. Yeo Ay Vout Vine a, iT oO Figure 11.63 11.3, Determine the ~3 dB bandwidth of the citeuits shown in Fig. 11.64, Assume V., = 00 but A> 0. Neglect other capaci- tances. “11.10. Sec. 11.1.3 Bode’s Rules 11.4, Construct the Bode plot of |Vju:/Vinl for the stages depicted in Fig. 11.64. A circuit contains two coincident (ie., equal) poles at «1. Construct the Bode Plot of |Vou/Vinl ns. Veo a, Vout Yortoor a, @ Figure 1.68 Fo’ ¥, YinoAAfE ma, al NTS. Figure 11.65 2 11.6. 7. 11.9. “111. amplifier exhibits. two ANMHz and 10GHz amt ae 1GHz. Construct the Boge f° Vout Vinl a n ideal integrator contains a ee ibn 0 Construct ete plot of IVou/ Vile Whats the pay circuit at arbitrarily low frequengiea"® An ideal differentiator provides, at the origin, ie. @, = 0. Construct iv Bode plot of |Vour/Vinl. Whats the »” of the circuit at arbitrarily higy, cies? Figure 11.65 illustrates a cascade two identical CS_ stages. Negleie channel-length modulation and gjy¢ capacitances, construct the Bode pig Of Vou/Vinl. Note that ¥,,/V, < (WVx/ Vin Vou! Vx)- In Problem 11.9, derive the trans function of the circuit, substitute s=ja, and obtain an expression for [Vy /V4. Determine the -3 dB bandwidth of tie circuit. the, ein fregue, Consider the circuit shown in Fig. 116 Derive the transfer function assuniag 4 > 0 but neglecting other capactancs Vout Vine, Tt Co Figure 11.66 Scanned with CamScanner Explain why the circuit opera jdeal integrator if 49, "8 as an Due toa manufacturing error, a the source of M, in Fig. 11,67, ‘Assumin a=Oand neglecting other capacitances determine the input and output poles the circuit. opts Figure 11.67 1143, Repeat Problem 11.13 for the circuit shown in Fig. 11.68, Figure 11.68 M14, Repeat Problem 11.12 for the CS stage depicted in Fig. 11.69. Yoo Po Vout Bs mo Ts My = Cy nT 14 Fgure 11.69, "MS. Derive a relationship for the figure of merit defined by Eq. (11.8) for a CS stage. Consider only the load capacitance. Problems 567 See.11,1 11.16, -5 Miller's Theorem Apply Miller's theorem to resistor Ry in Fig. 11.70 and estimate the voltage gain Of the circuit. Assume V4 = oo and Ry is large enough to allow the approximation Vout Vx = — Bm Re. Figure 11.70 11.17. Repeat Problem 11.16 for the source fol- lower in Fig. 11.71. Assume 4 =Oand Rp is large enough to allow the approxima- tion Vou/¥x = RyRy, + Sm). Yoo Rs x Ves a, Vet R rT, Figure 11.71 “11.18. Consider the common-base stage illus- trated in Fig. 1172, where the output resistance of Q, is drawn explicitly. Uti- lize Miller's theorem to estimate the gain. Assume rg is large enough to allow the approximation Vj4,/¥x = &,Re- Yoo Re: You ror ol vy Yara Figure 11.72 11.19. Using Miller's theorem, estimate the input capacitance of the circuit depicted in Fig, 11.73. Assume 4 > 0 but neglect other capacitances. What happens if 40? Scanned with CamScanner SS a re . 568 Chapter11 Frequency Reson Use Miller’s theorem to eg ima input and output poles of the = he shown in Fig. 11.76. Assume y,.< cing “3 neglect other capacitances, Note that . circuit in fact has only one poe. the py My eae + Yeo 11.22. R Cn c, Fe Figure 11.73 a Vox I- Vins Q, 11.20. Repeat Problem 11.19 for the source fol f ‘ lower shown in Fig, 11.74, Figure 11.76 Yoo ott My "11.23. Repeat Probie 11.22 for the ciety ce 77. Cin Figure 11.74 GN “11.21. Using Miller’s theorem, explain how the common-base stage illustrated in Fig. 11.75 provides a negative input capacitance. Assume V4=00 and neglect other capacitances, Figure 11.77 Re’ Sec. 11.2 High-Frequency Models of Transistors CG Yy a, 11.24, For the bipolar circuits depicted a re Fig. 11.78, identify all of the transi Cy or capacitances and determine whith Foils Ones are in parallel and which ones a &rounded on both ends. @ Figure 11.78, Scanned with CamScanner % od Vets % ¥, ot inet, ve ae t 5 Figure 11.79 For the MOS circuits shown in Fj 1135. enti all of the transistor capa z ie and determine which ones are in par. allel and which ones are grounded on both ends. 11.26. In arriving at Eq. (1152) for the fp of transistors, we neglected C, and Cap: Repeat the derivation without this approximation. 11.27, It can be shown that, if the minority car- riers injected by the emitter into the base take tr seconds to cross the base region, then Cy = 8mtp- (a) Writing C,=C,+C,, assuming that Cj is independent of the bias current, and using Eq. (11.52), derive an expression for the fr of bipolar transistors in terms of the collector bias current. (b) Sketch fy as a function of Ic. "1128. It can be shown that Cgs * (2/3)WLCox for a MOSFET operating in saturation. Using Eq. (11.52), prove that = 3 Mn a 11.183) 2 fr=573Vos Vm. ( ) Note that f; increases with the overdrive voltage. ‘N19, Having solved Problem 11.28 success fully, a student attempts a different substitution for gq: 2!p/(Vas~ Vru) arriving at 2p _1__. WLC. Vos — Vin decreases a8 es! Explain een Eqs. (11.184) Qe fps ‘This result suggests that fr the overdrive voltage increas this apparent discrepancy betw’ (11.183) and (11.184). Problems 569 “11,30. Using Eq, (11.52) and the results of Prob- lems 11.28 and 11.29, plot the fy of a MOSFET (a) as a function of W for a constant Jp, (b) as a function of fp for a constant W. Assume L remains constant in both cases. "11.31, Using Eq, (11.52) and the results of Prob- Tems 11.28 and 11.29, plot the fr of a MOSFET (a) asa function of Ves ~ Vrzr for a constant Jp, (b) as a function of Ip for a constant Ves — Vr. Assume L remains constant in both cases. *11.32. Using Eq, (11.52) and the results of Prob- lems 11.28 and 11.29, plot the fr of a MOSFET (a) as a function of W for a constant Ves — V1, (b) as a function of Vas ~ Vy for a constant W. Assume L remains constant in both cases. “11.33. In order to lower channel-length mod- ulation in a MOSFET, we double the device length. (a) How should the device width be adjusted to maintain the same overdrive voltage and the same drain current? (b) How do these changes affect the fy of the transistor? *11.34. We wish to halve the overdrive voltage of a transistor so as to provide a greater voltage headroom in a circuit. Determine the change in the fr if (a) Jp is constant and W is increased, or (b) W is constant and [p is decreased. Assume L is con- stant. Using Miller's theorem, determine the input and output poles of the CE and CS stages depicted in Fig, 11.31(a) while including the output impedance of the transistors. 11.35. Scanned with CamScanner 570 Chapter 11 Sec. 11.4 Frequency Response o| Stage 11,36. 1137. "11.38, 11.39, Frequency Response fCEand CS 0 The common-emitter stage of Fe, ke ini employs a currentsource load 10 2ch16°P ahigh gain (at low frequencies), ASU ing V, 0 and using Miller's theorem, determine the input and output poles of the stages depicted in Fig, 11.89, In the CS stage of Fig. 1131(@), Ry = 200 Q, Rp =1kQ, Ip, =1 mA, Cos = 50 IF, CGp = 10 fF, Cyg = 15 fF, and Vas~Vry=200 mV. Determine the Poles of the circuit using (a) Miller's le transfer func. ). Compare the Figure 11.62 4140. Consider the amplifier "11.43, Yoo 0 My i 2 vfs Vout rn nN a, weft al 1 he ® . ) Shown Fig. 11.83, where Vy = 00, Dor” in ete the poles of the circuit using (a) Mint approximation, and (b) the transfert tion expressed by Eq. (11.73), Compa the results. ‘ate Veo Figure 11.83, 1141, Repeat Problem 11.40 but use the dominant-pole approximation. How 4s the results compare? “11.42, The circuit depicted in Fig. 11.84 is caleg an “active inductor.” Neglecting other capacitances and assuming 2=0, com. pute Z;,. Use Bode’s rule to plot [Z| as a function of frequency and explain viy it exhibits inductive behavior, Figure 11,84 Determine the and _outpit input prPedances of the stage depicted it Fig. 11.85 without using Miller's theore™ Assume V4 = 9, Scanned with CamScanner lien sea luau Zn” Figure 11.85 wy1as. Compute the transfer function ofthe cir cuit shown in Fig. 11.86 without using Miller's theorem. Assume 4 > 0, Yoo m, Rs : Vin Vout Hy Figure 11.86 "1145. Calculate the input impedance of the stage illustrated in Fig. 11.87 without using Miller’s theorem. Assume A = 0. Yoo Mp Yous J Hen gure 1147 Sec.11.5 Frequency Response of CB and CG Stages 1146. Determine the transfer function of the circuits shown in Fig. 11.88. Assume 4=0for My. Yoo Yoo Vor Me Me Vout Vout ¥, Mlk % pelticlt + As. Yaoi a O) @ Figure 11.88 Problems 571 Sec. 11.6 Frequency Response of Followers 11.47. Consider the source follower shown in GED | Fig. 11.89, where the current source is mistakenly replaced with a diode- connected device. Taking into account only Ces, compute the input capaci- tance of the circuit. Assume 4 # 0. ' Cm te Figure 11.89 11.48. Determine the output impedance of the emitter follower depicted in Fig. 11.90, including C,. Sketch |Zy,| a8 a function of frequency. Assume V4 = co. Yoo Fo Vos a + Zou Figure 11:90 Sec. 11.7 Frequency Response of Cascode stage 11.49. In the cascode of Fig, 11.91, Qs serves as a constant current source, providing 75% of the bias current of Qy. Assum- ing V4 = 0° and using Miller's theorem, determine the poles of the circuit. Is Miller's effect more or less significant here than in the standard cascode topol- ogy of Fig. 11.502)? Yoo Vout myc % Ube fs Vues ae © Scanned with CamScanner 572 Chapter'11__ Frequency Response Yeo A Moe . Vout Q Mine Oy Ay ot Figure 11.91 41,50, Due to manufacturing error, a parasitic resistor R,, has appeared in the cascode stage of Fig. 11.92. Assuming 4 = 0 and using Miller's theorem, determine the poles of the circuit. Yoo Fo Vout Vyetfn Rs Vige—e—fa My Rp Figure 11.92 11,51. In analogy with the circuit of Fig. 11.91, a student constructs the stage depicted in Fig. 11.93 but mistakenly uses an NMOS device for Ms. Assuming 2 = Oand using Miller’s theorem, compute the poles of the circuit. Yoo Voor Ro oid, M2 Vige—t—Hf Ae Figure 11.93 Design Problems 11.52. Using the results obtained in Problems 11.9 and 11.10, design the two-stage amplifier of Fig. 11.65 for a total volt- age gain of 20 and a ~3 dB bandwidth of 1GHz. Assume each stage can bias current of IMA, C, =59 qa Mn Cos = 100pA/V?. » ang We wish to design the CE gq, Fig. 11.94 for an input pote at ogy, and an output pole at 2 GHz, Ass, of Ie =1mA, C, = 201F, C, = Sip, os 10 fF, and Va = 00, and using ifs theorem, determine the values of p, °° Re such that the (low-frequency) yo gain is maximized. You may need tg, 11.53. ing iteration. Yoo Fe Re Vout Vins ay Figure 11.94 411.54. Repeat Problem 11.53 with the adé- tional assumption that the circuit mt drive a load capacitance of 20 fF. 11.55. We wish to design the common-base stage of Fig, 11.95 for a -3 dB bandwidth of 10 GHz. Assume Jc = 1 mA, V,= ss Rs =50 &, Cy=20 fF, C, =5 IF, asd Ccs = 20 fF. Determine the maximum allowable value of Re and hence the maximum achievable gain. (Note thst the input and output poles may alfectthe bandwidth.) Veo Re Vout Vo rs [% Vino Figure 11.95 11.56. Theemitter follower of Fig. 96M designed for an input capacitan®” Oi, than 50 fF. If C, = 10 fF, Ce Mie Vg = c0,and Ie £1 mA, what sthe™ imum tolerable value of Ry? Scanned with CamScanner

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