STM32 Seminar Peripherals

Agenda
09:00 09:30 09:40 09:45 10:30 11:30 11:45 12:45 13:30 15:00 15:15 15:45 16:15 Registration Introduction to ST STM32 Overview ARM an introduction to Cortex-M3 STM32 Cortex-M3 Core and System Coffee Hitex Tools, DMA, RTOS Lunch STM32 Peripherals Coffee STM32 Libraries examples and Usage STM32-Primer demo Summary, Questions, and Close
8th October 2007
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STM32 Seminar

Agenda
09:00 09:30 09:40 09:45 10:30 11:30 11:45 12:45 13:30 15:00 15:15 15:45 16:15 Registration Introduction to ST STM32 Overview ARM an introduction to Cortex-M3 STM32 Cortex-M3 Core and System Coffee Keil Tools Lunch STM32 Peripherals Coffee STM32 Libraries examples and Usage STM32-Primer demo Summary, Questions, and Close
8th October 2007
3

STM32 Seminar

STM32 Peripherals
Communications Peripherals Analog to Digital Converter Timers Demo: USB Device Firmware Upgrade

STM32 Seminar

8th October 2007

STM32 Communication Peripherals

STM32 Seminar

8th October 2007

STM32F10x Series Block Diagram

Nine Communications Peripherals: 2 x SPI 2 x I2C 3 x USART CAN2.0B USB 2.0 Full Speed
JTAG/SW Debug JTAG/SW Debug Nested vect IT Ctrl Nested vect IT Ctrl 1x SysTick Timer 1x SysTick Timer DMA DMA 7 Channels 7 Channels Flash I/F Flash I/F

CORTEXM3 CORTEXM3 CPU CPU 72 MHz 72 MHz

ARM Lite Hi-Speed Bus ARM Lite Hi-Speed Bus Matrix Arbiter (max 72MHz) Matrix //Arbiter (max 72MHz)

32kB-128kB 32kB-128kB Flash Memory Flash Memory 512kB to come 512kB to come e/o 2007 e/o 2007

Power Supply Power Supply Reg 1.8V Reg 1.8V POR/PDR/PVD POR/PDR/PVD XTAL oscillators XTAL oscillators 32KHz + 4~16MHz 32KHz + 4~16MHz Int. RC oscillators Int. RC oscillators 32KHz + 8MHz 32KHz + 8MHz PLL PLL

Up to 20kB SRAM Up to 20kB SRAM 64kB to come e/o 64kB to come e/o 2007 2007 20B Backup Regs 20B Backup Regs Reset Clock Reset Clock Control Control ARM Peripheral Bus Bridge Bridge (max 36MHz)

RTC //AWU RTC AWU

1x USB 2.0FS 1x USB 2.0FS 1x bxCAN 2.0B 1x bxCAN 2.0B 2x USART/LIN 2x USART/LIN Smartcard //IrDa Smartcard IrDa Modem Control Modem Control 1x SPI 1x SPI 2x I22C 2x I C

ARM Peripheral Bus

Synchronized AC Synchronized AC Timer Timer

1x 16-bit PWM 1x 16-bit PWM

Bridge Bridge 3x 16-bit Timer 3x 16-bit Timer (max 72MHz) Independent Independent Watchdog Watchdog Window Watchdog Window Watchdog 2x 12-bit ADC 2x 12-bit ADC 16 channels //1Msps 16 channels 1Msps Temp Sensor Temp Sensor

Up to 16 Ext. ITs Up to 16 Ext. ITs 32/49/80 I/Os 32/49/80 I/Os 1x SPI 1x SPI 1x USART/LIN 1x USART/LIN Smartcard/IrDa Smartcard/IrDa Modem-Ctrl Modem-Ctrl

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SPI Serial Peripheral Interface

Two SPIs: SPI1 on high speed APB2 and SPI2 on low speed APB1 Up to 18 MHz data rate in either Master or Slave modes Full duplex and simplex synchronous transfers supported Programmable data frame size: 8/16-bit transfer frame format selection Programmable data order: MSB-first or LSB-first shifting Programmable clock polarity & phase Hardware or software nSS management Interrupt/DMA request generation:
Tx Buffer Empty, Rx Buffer Not Empty, Bus Fault, Overrun

Hardware CRC support: CRC8 / CRC16-CCITT standard

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SPI Data Frame Format

Programmable data frame size: 8 or 16-bit frame format Programmable data order: MSB or LSB-first

0xD7

MSB first LSB first

Master
SCK MISO MOSI NSS

8-bit long
0xD7

VDD

0xD739

MSB first LSB first

16-bit long
0xD739

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SPI Full Duplex Communication

Standard full duplex 3-wire transfer

Master
SCK MISO MOSI NSS VDD NSS SCK MISO MOSI

Slave

Full Duplex

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SPI Simplex Communication

Simplex modes for pin saving Bi-directional: two wire, direction control bit Slave Rx-Only: two wire, uni-directional

Master
SCK MISO MOSI NSS VDD NSS SCK MISO MOSI

Slave

Master
SCK MISO MOSI NSS VDD NSS SCK MISO MOSI

Slave

Bi-directional

Rx Only

(Slave)

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SPI NSS Hardware & Software Management

Hardware NSS

Software NSS

Slave

Slave

Full Duplex pin saving mode Frees Master and Slave NSS pins
SCK MISO MOSI NSS SCK MISO MOSI NSS

Dynamic Master/Slave reVDD SCK MISO MOSI NSS SCK MISO MOSI NSS

configuration

Master
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Master
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SPI Single Master: SS Output Management

Slave
Enable SS output capability

Slave
Each device can be a unique master by enabling its NSS as output and driving it low: all other devices became slaves.

SCK MISO MOSI NSS

SCK MISO MOSI NSS

No need for external GPIO pin to drive slaves NSS pins

SCK MISO MOSI NSS SCK MISO MOSI NSS

Master
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Slave
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SPI SD/MMC Card Support

Basic SD/MMC support (SPI protocol): Performance: speed up to 18MHz Error checking: hardware CRC calculation
VDD R = 4.7 K VDD

Master
MISO SCK MOSI CS

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SPI CRC Calculation

Example of n data transfer between two SPIs followed by the CRC transmission of each one in Full-duplex mode

Taken from SPI1 TXCRC register and sent to SPI2

MOSI

Data 1

Data 2

Data n

CRC[1..n]
Taken from SPI2 TXCRC register and sent to SPI1

MISO

Data 1

Data 2

Data n

CRC[1..n]

SCK

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Inter Integrated Circuit (I2C)

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I2C Features (1/3)

Multi-Master and Slave capability Controls all IC bus specific sequencing, protocol, arbitration and timing Standard and fast IC modes (up to 400kHz) 7-bit and 10-bit addressing modes Clock stretching supported Dual addressing capability to acknowledge 2 slave addresses Configurable PEC (Packet Error Checking) Generation or Verification:
PEC value can be transmitted as last byte in Tx mode PEC error checking for last received byte

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I2C Features (2/3)

Error flags:
Arbitration lost condition for master mode Acknowledgement failure after address/ data transmission Detection of misplaced start or stop condition Overrun/Underrun if clock stretching is disabled

2 Interrupt vectors:
1 Interrupt for successful address/ data communication 1 Interrupt for error condition

SMBus 2.0 (System Management Bus) Compatibility [Link] PMBusTM (Power Management Bus) Compatibility [Link]

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I2C Features: DMA (3/3)

DMA supported for TX and RX Requests mapped on separate DMA channels, supporting simultaneous bidirectional transfers Calculated PEC value is automatically transmitted at end of frame

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I2C Dual Addressing Mode

I2C supports dual addressing capability to acknowledge 2 slave addresses

VDD

Master
SDA SCL SDA SCL

Slave
Slave address1 Slave address2

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I2C SMBus Mode

Intel System Management Bus SMBus 2.0 Compatibility Low cost, more robust than standard IC Clock stretching support for different speed devices Timeout: 25ms clock low timeout delay H/W Packet Error Checking (PEC) with ACK control Address Resolution Protocol (ARP) supported SMBALERT# line for interrupts Host Notify Protocol

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Universal Synchronous Asynchronous Receiver Transmitter (USART)

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USART Features (1/2)

Three USART: USART1 High speed APB2 and USART2/3 on Low speed APB1 Fully-programmable serial interface characteristics:
8 or 9 bit data Even, odd or no-parity generation and detection 0.5, 1, 1.5 or 2 stop bits Programmable fractional baud rate generator (12-bit Integer, 4-bit Fraction) Hardware flow control (CTS and RTS)

Dedicated transmission and reception flags (TxE and RxNE) with interrupt capability Support for DMA
Receive DMA request Transmit DMA request

Up to 4.5 Mbps

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USART Features (2/2)

10 interrupt sources to ease software implementation LIN Master/Slave compatible Synchronous Mode: Master mode only IrDA SIR Encoder Decoder Smartcard Capability Single Wire Half Duplex Communication Multi-Processor communication
USART can enter Mute mode Mute mode: disable receive interrupts until next header detected Wake up from mute mode (by idle line detection or address mark detection)

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USART DMA Capability

DMA supported for TX and RX Requests mapped on separate DMA channels, supporting simultaneous bidirectional transfers

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USART Synchronous Mode

USART supports Full duplex synchronous communication mode
Full-duplex, three-wire synchronous transfer USART Master mode only Programmable clock polarity (CPOL) and phase (CPHA) Programmable Last Bit Clock generation Transmitter Clock output (SCLK)

Master
SCLK Rx Tx SCK MISO MOSI NSS

Slave

USART
Full Duplex
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SPI

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USART Single Wire Half Duplex mode

USART supports Half duplex synchronous communication mode
Only Tx pin is used (Rx is no longer used)

Used to follow a single wire Half duplex protocol.

VDD R = 10 K

USART1
Tx

Half Duplex

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Tx

USART2

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USART Smart Card mode

USART supports Smart Card Emulation ISO 7618-3
Half-Duplex, Clock Output (SCLK) 9Bits data, 0.5 Stop Bit in receive, 1.5 Stop Bits in transmit Parity Error Generation with NACK transmission Programmable Guard Time Programmable Clock Prescaler to guarantee a wide range clock input

USART
Tx

SCLK

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USART IrDA SIR Encoder Decoder

USART supports the IrDA Specifications
Half-duplex, NRZ modulation, Max bit rate 115200 bps 3/16 bit duration for normal mode Low power mode: 1.42MHz<USART Prescaler<2.12MHz

USART
SIR Transmit Encoder
Tx/ SW_Rx
IrDA OUT

USART Tx

SIR Receive Decoder

IrDA IN

Half Duplex
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Controller Area Network (bxCAN)

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CAN Features (1/2)

Main features:
Supports CAN protocol version 2.0 A, B Active Bit rates up to 1Mbit/s Supports Time Triggered Communication

Transmission
Three transmit mailboxes Configurable transmit priority Time Stamp on SOF transmission

Reception
Two receive FIFOs with three stages 14 scalable filter banks Identifier list features Configurable FIFO overrun Time Stamp on SOF reception

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CAN Features (2/2)

Time Triggered Communication option
Disable automatic retransmission mode 16-bit free running timer Configurable timer resolution Time Stamp sent in last two data bytes

Management
Maskable interrupts Software-efficient mailbox mapping at a unique address space 512 bytes reserved RAM size 4 dedicated interrupt vectors: transmit interrupt, FIFO0 interrupt, FIFO1 interrupt and status change error interrupt

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STM32 CAN Block Diagram

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Filter Bank Scale and Mode Configuration

Up to 14 filter banks Scale configuration: either 16-bit or 32-bit filter size Mode configuration: either Id/Mask or Id/List mode

32-bit filter Id/Mask Id Mask 16-bit filter Id/Mask Id Mask Id Mask

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32-bit filter Id/List Id Id 16-bit filter Id/List Id Id Id Id

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Universal Serial Bus Interface (USB Device)

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USB Features
Full speed USB 2.0 transfer. Configurable endpoints transfer mode type: control, bulk, interrupt and Isochronous. Configurable number of endpoints: up to 8 bidirectional endpoints and 16 mono-directional endpoints. USB suspend/resume support. Dedicated SRAM Area (Packet Memory Area) up to 512bytes (shared with bxCAN). Dynamic buffer allocation according to the user needs. Special double buffer support for Isochronous and Bulk transfers.

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Double Buffering transfer mode

Up to 7 mono-directional Double-buffered endpoints Highest possible transfer rate Number of NAKed transactions governed by the Application elaboration time.

PMA

Endpointx Buff 1

USB IP
Endpointx Buff 0

CPU

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STM32F10x USB Developers Kit

STM32 USB Library
USB 2.0 full speed certified Strict ANSI-C Toolchain independent Independent from Firmware library Self documented

STM32 USB Developers Kit demos

Covers all USB transfer types Independent from any SW tool chain Running on STM32F10x-EVAL board Can easily be tailored to other target h/w

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STM32 Device Firmware Upgrade (DFU) Demo

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Analog-to-Digital Converter (ADC)

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STM32F10x Series Block Diagram

Up to 2x12-bits 1Msps ADC Up to 16 external channels Embedded temperature sensor, +/-1.5 linearity with T
JTAG/SW Debug JTAG/SW Debug Nested vect IT Ctrl Nested vect IT Ctrl 1x SysTick Timer 1x SysTick Timer DMA DMA 7 Channels 7 Channels Flash I/F Flash I/F

CORTEXM3 CORTEXM3 CPU CPU 72 MHz 72 MHz

ARM Lite Hi-Speed Bus ARM Lite Hi-Speed Bus Matrix Arbiter (max 72MHz) Matrix //Arbiter (max 72MHz)

32kB-128kB 32kB-128kB Flash Memory Flash Memory 512kB to come 512kB to come e/o 2007 e/o 2007

Power Supply Power Supply Reg 1.8V Reg 1.8V POR/PDR/PVD POR/PDR/PVD XTAL oscillators XTAL oscillators 32KHz + 4~16MHz 32KHz + 4~16MHz Int. RC oscillators Int. RC oscillators 32KHz + 8MHz 32KHz + 8MHz PLL PLL

Up to 20kB SRAM Up to 20kB SRAM 64kB to come e/o 64kB to come e/o 2007 2007 20B Backup Regs 20B Backup Regs Reset Clock Reset Clock Control Control ARM Peripheral Bus Bridge Bridge (max 36MHz)

RTC //AWU RTC AWU

1x USB 2.0FS 1x USB 2.0FS 1x bxCAN 2.0B 1x bxCAN 2.0B 2x USART/LIN 2x USART/LIN Smartcard //IrDa Smartcard IrDa Modem Control Modem Control 1x SPI 1x SPI 2x I22C 2x I C

ARM Peripheral Bus

Synchronized AC Synchronized AC Timer Timer

1x 16-bit PWM 1x 16-bit PWM

Bridge Bridge 3x 16-bit Timer 3x 16-bit Timer (max 72MHz) Independent Independent Watchdog Watchdog Window Watchdog Window Watchdog 2x 12-bit ADC 2x 12-bit ADC 16 channels //1Msps 16 channels 1Msps Temp Sensor Temp Sensor

Up to 16 Ext. ITs Up to 16 Ext. ITs 32/49/80 I/Os 32/49/80 I/Os 1x SPI 1x SPI 1x USART/LIN 1x USART/LIN Smartcard/IrDa Smartcard/IrDa Modem-Ctrl Modem-Ctrl

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ADC Features (1/2)

Single (Access Line) and Dual (Performance Line) ADC options Conversion rate 1MHz, 12-bit resolution ADC supply requirement: 2.4V to 3.6 V ADC input range: VREF- VIN VREF+ (VREF pins only on 100pin pkg) Up to 18 multiplexed channels
16 external channels 2 internal channels: temperature sensor and voltage reference

Grouped channels for conversion:

Regular group up to 16 channels Injected group up to 4 channels

Single, continuous and discontinuous conversion modes Dual modes (on devices with 2 ADCs): 8 variations

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ADC Features (2/2)

Sequencer-based Scan Mode for both Regular and Injected groups External trigger options for both Regular and Injected groups Channel-by-channel programmable sampling time Selectable Left/Right data alignment +/- Signed results from Injected groups Analog Watchdog with high and low thresholds Interrupt generation on:
End of Conversion (Regular groups) End of Injected Conversion (Injected groups) Analog Watchdog

DMA capability Self-calibration

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ADC Block Diagram

VREF+ VREFVDDA VSSA

ADCCLK

ADC Prescalers: Div2, Div4, Div6 and Div8

PCLK2

ADC_IN0 ADC_IN1

ADC GPIO Ports

Up to 4

DMA Request Address/data bus

Injected data registers (4x12bits) Regular data register (12bits)
End of conversion End of injected conversion

. . .
ADC_IN15

ANALOG MUX

Injected Channels
Up to 16

Regular Channels

Temp Sensor VREFINT

Analog Watchdog
TIM1_TRGO TIM1_CC4 TIM1_TRGO TIM2_CC1 TIM3_CC4 TIM4_TRGO Ext_IT_15 JEXTSEL[2:0] bits JEXTRIG bit Start Trigger (injected group)

High Threshold register (12bits) Low Threshold register (12bits)

Analog watchdog event

AWD

EOC

JEOC

Flags

AWDIE
TIM1_CC1 TIM1_CC2 TIM1_CC3 TIM2_CC2 TIM3_TRGO TIM4_CC4 Ext_IT_11 EXTSEL[2:0] bits EXTRIG bit Start Trigger (regular group)

EOCIE

JEOCIE

Interrupt enable bits

ADC interrupt to NVIC

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ADC Regular Conversion Group

Programmable number of Regular channels: up to 16 channels Programmable sample time and channel order Conversion started by either:
Software through start bit External trigger
Timer1 CC1 Timer1 CC2 Timer1 CC3 Timer2 CC2 Timer3 TRGO Timer4 CC4 EXTI Line11

Interrupt/DMA request at End of Conversion

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ADC Injected Conversion Group

Programmable number of Injected channels: up to 4 channels Programmable sample time and channel order Conversion started by either:
Software through start bit JAUTO: automatic Injected group conversion after Regular group completes External trigger
Timer1 TRGO Timer1 CC4 Timer2 TRGO Timer2 CC1 Timer3 CC4 Timer4 TRGO EXTI Line15

Programmable zero-offset for +/- signed conversions

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ADC Conversion Modes: Single & Continuous

Start Start Start CHx CHx CHx Stop

. . .

Start

CHx

One channel Single conversion mode

One channel Continuous conversion mode

. . .

CHn CHn

Stop

Multi-channels (Scan) Single conversion mode

Multi-channels (Scan) Continuous conversion mode

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ADC Conversion Modes: Discontinuous

Splits channel conversion sequence into sub-sequences Available for either Regular or Injected groups: Up to 8 conversions per sub-sequence for Regular groups Up to 3 conversions per sub-sequence for Injected groups

Example: - Conversion of channels: 0, 1, 2, 4, 5, 8, 9, 11, 12, 13, 14 and 15 - Discontinuous mode Number of channel is 3

1st trigger

2nd trigger

3rd trigger

Channel0

Channel1

Channel2

Channel4

Channel5

Channel8

Channel9

Channel11

Channel12

4th trigger Channel13 Channel14 Channel15

5th trigger

Note: Do not use discontinuous mode for both regular and injected together. It can be used only for one group Channel1 Channel2

Channel0

channel

End of Conversion

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Analog Sample Time

ADCCLK up to 14MHz derived from PCLK2 via prescaler (Div2,Div4,Div6,Div8) Programmable sample time for each channel:
1.5 cycles 7.5 cycles 13.5 cycles 28.5 cycles 41.5 cycles 55.5 cycles 71.5 cycles 239.5 cycles
239.5 cycles

ADC
1.5 cycles 7.5 cycles Sample Time Selection Sample Time Selection 13.5 cycles

PCLK2

ADC Prescaler: Div2, Div4, Div6 and Div8

ADCCLK

28.5 cycles 41.5 cycles 55.5 cycles 71.5 cycles

SMPx[2:0]

Total conversion = Sample time + 12.5 cycles At 14MHz, sample time of 1.5cycles, total conversion time = 1 s (14 cycles)
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Sequencer

Up to 16 conversions with different order, different sampling time and oversampling possibility.
Example: - Conversion of channels: 1, 2, 8, 4, 7, 3 and 11 - Different sampling time. - Oversampling of channel 7.
Channel1 Channel2 Channel8 Channel4 Channel7 Channel7 Channel7 Channel3 Channel11

1.5 cycles

13.5 cycles

7.5 cycles

7.5 cycles

71.5 cycles

28.5 cycles

1.5 cycles

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ADC Data Alignment

One bit data align selection: right or left Sign extension for Injected group

Right alignment

SEXT SEXT SEXT SEXT D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Injected group

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Regular group

Left alignment

SEXT D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Injected group

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Regular group

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ADC Analog Watchdog

12-bit programmable analog watchdog with high and low thresholds Enabled on zero, one or all channels, regular and/or injected Interrupt generation on low or high threshold detection

ADC_IN0 ADC_IN1

. . .
ADC_IN15

Analog Watchdog
Low Threshold High Threshold

AWD

Status Register

Temp Sensor VREFINT

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DMA
DMA request generated on each ADC1 end of regular channel conversion In dual modes, ADC2 and ADC1 results transferred in 32-bits of ADC1_DR

DMA Request Channel0 Channel1

DMA Request Channel2

DMA Request Channel3

DMA Request Channel4

DMA Request Channel5

DMA Request Channel6

DMA Request Channel7

DMA Request Channel8

DMA Request

ConvertedValue_Tab[9]
Channel0 conversion result Channel1 conversion result Channel2 conversion result

Example: - Conversion of Regular group - DMA triggered by End of Conversion - Results transferred to SRAM array by DMA - DMA Destination address auto incremented - EOC flag cleared by DMA access to ADCR1_DR

ADC1 DR register ADC1 DR register

.. .. ..

Channel3 conversion result Channel4 conversion result Channel5 conversion result Channel6 conversion result Channel7 conversion result Channel8 conversion result

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ADC Dual Modes (1/9)

Available in devices with two ADCs: ADC1 master and ADC2 slave Independent Dual Mode 8 Synchronised Dual Modes
ADC_IN15 Temp Sensor ADC_IN1 ADC_IN0

Up to 4 injected channels

External event (Regular group)

External event (Injected group)

VREFINT

GPIO Ports

ANALOG MUX
Up to 16 regular channels

ADC1 Analog
External event synchronization

ADC2 Analog

Data register

Digital Master

Digital Slave

EOC/JEOC

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ADC Dual Modes (2/9)

Regular Simultaneous Mode
Converts Regular groups External trigger source routed via ADC1 (simultaneous trigger provided to ADC2) End of Conversion flag is generated when group conversions are complete Results for both ADCs stored in ADC1 Regular data register (32bits) Use DMA for efficient data transfer

Regular simultaneous mode on 16 regular channels

Sampling ADC2
CH0 CH1 CH2 CH3 CH15

Conversion

ADC1

CH15

CH14

CH13

CH12

CH0

End of Conversion on ADC1 and ADC2 Trigger for regular channels Note: Do not sample the same channel at the same time on each ADC

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ADC Dual Modes (3/9)

Injected Simultaneous Mode
Converts Injected groups External trigger source routed via ADC1 (simultaneous trigger provided to ADC2) End of Injected Conversion flags are generated when group conversions are complete Results stored in Injected data registers of each ADC

Injected simultaneous mode on 4 injected channels

Sampling ADC2
CH0 CH1 CH2 CH3

Conversion

ADC1

CH15

CH13

CH1

CH2 End of Injected Conversion on ADC1 and ADC2

Trigger for injected channels Note: Do not convert the same channel on the two ADCs

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ADC Dual Modes (4/9)

Slow Interleaved Mode
Converts Regular groups (only one channel) External trigger source routed via ADC1
Trigger routed to start ADC2 conversion immediately ADC1 conversion begins after 14cycle delay

End of Conversion flag is generated after each conversion is complete Results for both ADCs stored in ADC1 Regular data register (32bits) Next conversion on each ADC automatically started after 28 cycles Use DMA for efficient data transfer

Slow Interleaved mode on 1 regular channel

End of Conversion on ADC2

ADC2

CH0

CH0

Sampling Conversion

ADC1
14 ADCCLK cycles Trigger for regular channel

CH0

CH0 End of Conversion on ADC1

28 ADCCLK cycles

Note: - Sampling time must be less than 14 ADC clock cycles

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ADC Dual Modes (5/9)

Fast Interleaved Mode
Converts Regular groups (usually one channel) External trigger source routed via ADC1
Trigger routed to start ADC2 conversion immediately ADC1 conversion begins after 7cycle delay

End of Conversion flag is generated when each conversion is complete Results for both ADCs stored in ADC1 Regular data register (32bits) Use DMA for fast & efficient data transfer

Fast Interleaved mode on 1 regular channel in continuous conversion mode conversion

Sampling ADC2
CH0 CH0 CH0

Conversion
CH0

End of Conversion on ADC2

ADC1

CH0 7 ADCCLK cycles

CH0

End of Conversion on ADC1

Trigger for regular channels Note: - Sampling time must be less than 7 ADC clock cycles

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ADC Dual Modes (6/9)

Alternate Trigger Mode
Converts Injected groups External trigger source routed via ADC1
ADC1 and ADC2 conversions triggered alternately Scan or Discontinuous Modes

End of Conversion flags are generated when group conversions are complete Results stored in Injected data registers of each ADC

Alternate Trigger mode on 4 injected channels (injected discontinuous mode enabled) discontinuous
1st Trigger 3rd Trigger CH1 5th Trigger CH2 7th Trigger CH3 JEOC on ADC1

Sampling Conversion

ADC1

CH0

ADC2
2nd Trigger

CH10

CH11

CH12

CH13 JEOC on ADC2

4th Trigger

6th Trigger

8th Trigger

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ADC Dual Modes (7/9)

Combined Regular/Injected Simultaneous Mode
Converts Regular and Injected groups External trigger source routed via ADC1
Simultaneous trigger fed to ADC2 Trigger for Injected conversions interrupts running Regular conversion

End of Injected Conversion flags generated when Injected group conversions are complete End of Conversion flags are generated when Regular group conversions are complete Injected group results stored in Injected data registers of each ADC Regular group results stored in Regular data register of ADC1 (32 bits)

Combined Regular/Injected simultaneous mode on 4 regular channels and 2 injected channels channels
ADC2
regular simultaneous

Sampling
CH3

CH0

CH1

CH1

CH2

mode interrupted by injected simultaneous one

Conversion

ADC1

CH3

CH2

CH2

CH1

CH0 End of Conversion on ADC1 and ADC2

ADC2
Trigger for regular channels

CH10

CH11

ADC1

CH15

CH14 End of Injected Conversion on ADC1 and ADC2

Note: Do not sample the same channel at the same time on each ADC

Trigger for injected channels

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ADC Dual Modes (8/9)

Combined Regular Simultaneous & Alternate Trigger Mode
Converts Regular and Injected groups External trigger source routed via ADC1
Simultaneous trigger fed to ADC2 Trigger for alternate Injected conversions interrupts running Regular conversion

End of Injected Conversion flags generated when Injected group conversions are complete End of Conversion flags are generated when Regular group conversions are complete Injected group results stored in Injected data registers of each ADC Regular group results stored in Regular data register of ADC1 (32 bits)

Combined Regular simultaneous + Alternate trigger mode on 4 regular channels and 2 injected channels regular
ADC1
CH0 CH1 1st injected Trigger CH1 CH3 CH3

Sampling Conversion
End of Conversion on ADC1 and ADC2

End of Injected Conversion

ADC1 ADC2
CH3 CH2

CH10

on ADC1

CH2

CH0

CH0

Note: For Regular Simultaneous mode, do not sample the same channel at the

Regular simultaneous mode interrupted by the

Trigger for regular channels

Injected alternate trigger

ADC2

CH11

same time on each ADC End of Injected Conversion on ADC2

2nd injected Trigger

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ADC Dual Modes (9/9)

Combined Fast Interleaved & Injected Simultaneous Mode
Converts Regular and Injected groups External trigger source routed via ADC1
Trigger routed to start ADC2 conversion immediately, ADC1 conversion begins after 7cycle delay Trigger for simultaneous Injected conversions interrupts running Regular conversion

End of Injected Conversion flags generated when Injected group conversions are complete End of Conversion flags are generated when Regular group conversions are complete Injected group results stored in Injected data registers of each ADC Regular group results stored in Regular data register of ADC1 (32 bits)
Combined Injected simultaneous + Interleaved mode on 1 regular (continuous conversion) channel and 2 injected channels (continuous
End of Conversion on each ADC at the end of CH0 conversion CH0

ADC2 ADC1

CH0 CH0

CH0 CH0 CH10 CH11 CH11 CH10

CH0 CH0

CH0

Sampling Conversion

ADC2
Trigger for regular channel

End of Injected Conversion on ADC1 and ADC2

ADC1

Note: For Injected Simultaneous mode, do not sample the same channel at the

Interleaved mode interrupted by

Trigger for injected channel

same time on each ADC

Injected simultaneous

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STM32 Timers

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STM32F10x Series Block Diagram

Flash I/F Flash I/F

4 Timers w/ advanced control features Embedded low power RTC with VBAT capability Dual Watchdog Architecture Cortex-M3 SysTick Timer

CORTEXM3 CORTEXM3 CPU CPU 72 MHz 72 MHz

ARM Lite Hi-Speed Bus ARM Lite Hi-Speed Bus Matrix Arbiter (max 72MHz) Matrix //Arbiter (max 72MHz)

32kB-128kB 32kB-128kB Flash Memory Flash Memory 512kB to come 512kB to come e/o 2007 e/o 2007

Power Supply Power Supply Reg 1.8V Reg 1.8V POR/PDR/PVD POR/PDR/PVD XTAL oscillators XTAL oscillators 32KHz + 4~16MHz 32KHz + 4~16MHz Int. RC oscillators Int. RC oscillators 32KHz + 8MHz 32KHz + 8MHz PLL PLL

JTAG/SW Debug JTAG/SW Debug Nested vect IT Ctrl Nested vect IT Ctrl 1x SysTick Timer 1x SysTick Timer DMA DMA 7 Channels 7 Channels

Up to 20kB SRAM Up to 20kB SRAM 64kB to come e/o 64kB to come e/o 2007 2007 20B Backup Regs 20B Backup Regs Reset Clock Reset Clock Control Control ARM Peripheral Bus Bridge Bridge (max 36MHz)

RTC //AWU RTC AWU

1x USB 2.0FS 1x USB 2.0FS 1x bxCAN 2.0B 1x bxCAN 2.0B 2x USART/LIN 2x USART/LIN Smartcard //IrDa Smartcard IrDa Modem Control Modem Control 1x SPI 1x SPI 2x I22C 2x I C

ARM Peripheral Bus

Synchronized AC Synchronized AC Timer Timer

1x 16-bit PWM 1x 16-bit PWM

Bridge Bridge 3x 16-bit Timer 3x 16-bit Timer (max 72MHz) Independent Independent Watchdog Watchdog Window Watchdog Window Watchdog 2x 12-bit ADC 2x 12-bit ADC 16 channels //1Msps 16 channels 1Msps Temp Sensor Temp Sensor

Up to 16 Ext. ITs Up to 16 Ext. ITs 32/49/80 I/Os 32/49/80 I/Os 1x SPI 1x SPI 1x USART/LIN 1x USART/LIN Smartcard/IrDa Smartcard/IrDa Modem-Ctrl Modem-Ctrl

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General Purpose & Advanced Control Timers

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General Purpose Timer Overview

TIM2, 3, 4 on Low Speed APB (APB1) Internal clock up to 72 MHz 16-bit Counter
Up, down and centred counting modes Auto Reload
ETR
Clock ITR 1 ITR 2 ITR 3 ITR 4

Trigger/Clock
Trigger Output

Controller

4 x 16-bit Capture/Compare Channels

Programmable channel direction: input/output Input Capture, PWM Input Capture Modes Output Compare, PWM, One Pulse Modes

16-Bit Prescaler Auto Reload REG +/- 16-Bit Counter

Synchronization
Timer Master/Slave Synchronisation with external trigger Triggered or gated modes Serial and Parallel Multi-timer Cascade

Encoder interface Hall sensor interface Independent IRQ/DMA Requests:

At each Update Event At each Capture Compare Events At each Input Trigger

CH1 CH2 CH3 CH4

CH1

Capture Compare Capture Compare Capture Compare Capture Compare

CH2 CH3 CH4

Debug mode
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Advanced Timer Overview

TIM1 on High Speed APB (APB2) Internal clock up to 72 MHz As GP Timers, plus Complementary outputs Repetition counter Channel programmable polarity Channel programmable idle state Preload bits (e.g. 6-step PWM generation) Break Event
Break Input (BKIN) Clock Security System
ETR
Clock ITR 1 ITR 2 ITR 3 ITR 4

Trigger/Clock
Trigger Output

Controller

16-Bit Prescaler Auto Reload REG +/- 16-Bit Counter

CH1 CH2 CH3

Capture Compare Capture Compare Capture Compare Capture Compare

Configurable lockable levels

CH4 BKIN

CH1 CH1N CH2 CH2N CH3 CH3N CH4

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Counter Clock Selection

Clock can be selected from 8 sources
Internal clock TIMxCLK provided by the TIMxCLK RCC Internal trigger input 1 to 4:
ITR1 / ITR2 / ITR3 / ITR4 Using another timer as a prescaler
Trigger Controller

External Capture Compare pins

Pin 1: TI1FP1 or TI1F_ED Pin 2: TI2FP2

ETR ITR1 ITR2 ITR3 ITR4

Polarity selection & Edge Detector & Prescaler & Filter

Controller TRGO

External pin ETR

Enable/Disable bit Programable polarity 4 Bits External Trigger Filter External Trigger Prescaler:
Prescaler off Division by 2 Division by 4 Division by 8

TI1F_ED TI1FP1 TI2FP2

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Input Capture Mode

TI1
Input Filter & Edge detector
TRC IC1

Prescaler

16 bit Capture/Compare 1 Register

TI2

Input Filter & Edge detector

TRC

IC2

Prescaler

16 bit Capture/Compare 2 Register

TI3

Input Filter & Edge detector

TRC

IC3

Prescaler

16 bit Capture/Compare 3 Register

TI4

Input Filter & Edge detector

TRC

IC4

Prescaler

16 bit Capture/Compare 4 Register

IC1, IC2, IC3 and IC4 are specific as they can be independently mapped by software on TI1, TI2, TI3 or TI4. 4x16-bit capture compare registers are programmable to be used to latch the value of the counter after a transition detected by the corresponding Input Capture. When a capture occurs, the corresponding CCXIF flag is set and an interrupt or a DMA request can be sent if they are enabled. Overcapture flag set if second capture occurs before previous capture is cleared

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Output Compare Mode

The Output Compare is used to control an output waveform or indicate when a period of time has elapsed.

When a match is found between the capture/compare register and the counter:
The corresponding output pin is assigned to the programmable Mode, it can be: Timer Clock Set
Reset Toggle Remain unchanged
Interrupt Interrupt

OC1 New CCR1 CCR1

Set a flag in the interrupt status register Generates an interrupt if the corresponding interrupt mask is set Send a DMA request if the corresponding enable bit is set

The CCRx registers can be programmed with or without preload registers

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PWM Mode
The PWM mode allows to generate:
4 independent signals for TIM1, plus 3 complementary signals with individually programmable dead time insertion. 4 independent signals for TIM2, 3 and 4 The frequency and a duty cycle determined as follow:
One auto-reload register to defined the PWM period. Each PWM channel has a Capture Compare register to define the duty cycle.

Example: to generate a 40 KHz PWM signal w/ duty cycle of 50% on TIM1 clock at 72MHz:
Load Prescaler register with 0 (counter clocked by TIM1CLK/(0+1)), Auto Reload register with 1799 and CCRx register with 899

There are two configurable PWM modes:

Edge-aligned Mode Center-aligned Mode

Edge-aligned Mode
Timer Clock AutoReload Capture Compare
Update Event

Center-aligned Mode
Timer Clock AutoReload Capture Compare OCx
Update Event

OCx

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Counter Modes
Three Counter Modes
Up Counting Down Counting Centre-Aligned Mode Center Aligned
RCR = 0

Up counting

Down counting

UEV

RCR = 2

UEV RCR = Repetition Counter, Advanced Control Timer only STM32 Seminar 8th October 2007
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Advanced Control timer TIM1 Complementary PWM outputs for motor control
This mode allows the TIM1 to:
Output two complementary signals for each three channels. Output two independent signals for each three channels. Manage the dead-time between the switching-off and the switching-on instants of the outputs.

One reference waveform OCxREF to generate 2 outputs OCx and OCxN for the three channels. Full modulation capability (0 and 100% duty cycle), edge or center-aligned patterns Dedicated interrupt and DMA requests for TIM1 period and duty cycles updating. Three programmable write protection levels
Level1: Dead Time and Emergency enable are locked. Level2: Level1 + Polarities and Off-state selection for run and Idle state are locked. Level3: Level2 + Output Compare Control and Preload are locked.

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Advanced Control timer TIM1 Dead Time Insertion & Timer Write Protection

Dead Time Insertion

Rising edges of both OC and OC_N delayed by programmable dead time

Timer Write Protection

Level1: Dead Time and Emergency enable are locked. Level2: Level1 + Polarities and Off-state selection for run and Idle state are locked. Level3: Level2 + Output Compare Control and Preload are locked.

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Advanced Control timer TIM1 The break function

The break can be generated by:
The BRK input which has a programmable polarity and an enable bit BKE The Clock Security System

When a break occurs:

The MOE bit: Main Output Enable is cleared Each output channel is driven with the level programmed in the OISx bit The break status flag is set. An interrupt or a DMA request can be generated if the BIE bit is set or if the BDE bit is set.

Break applications:
If the AOE: Automatic Output Enable bit is set, the MOE bit is automatically set again at the next update event UEV This can be used to perform a regulation. If the AOE is Reset, the MOE remains low until you write it to 1 again In this case, it can be used for security and you can connect the break input to an alarm from power drivers, thermal sensors or any security components.
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PWM Input Mode

PWMI Configuration tips:

IC1 and IC2 must be configured

together to the PWM signal:

Timer Clock to be connected PWM

IC1 and IC2 are redirected internally to be mapped to the same external pin TI1 or TI2. IC1 PWM IC2 Counter

IC1 and IC2 active edges must have opposite

polarity.

IC1 - DUTY CYCLE

IC2 - PERIOD IC1 or IC2 is selected as trigger input and the slave mode controller is configured in reset mode.

10

The PWM Input functionality enables the measurement of the period and the pulse width of an external waveform. STM32 Seminar 8th October 2007
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One Pulse Mode

TI2

One Pulse Mode (OPM) is a particular case of the previous modes: Ouput Compare and Input Capture. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. There are two One Pulse Mode waveforms selectable by software:
Single Pulse Repetitive Pulse

OC1REF

OC1

TIM_ARR

TIM_CCR1

tDelay

tPulse

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Encoder Interface
Encoders are used to measure position and speed of motion systems (either linear or angular) The encoder interface mode acts as an external clock with direction selection The counter provides information on the current position (for instance angular position of an electric motors rotor) To obtain dynamic information (speed, acceleration) on must measure the number of counts between two periodic events, generated by another timer Encoders and Microcontroller connection example:
An external incremental encoder can be connected directly to the MCU without external interface logic. The third encoder output which indicates the mechanical zero position, may be connected to an external interrupt and trigger a counter reset.
TI1 TI2 Polarity Select & Edge Controller Polarity Select & Edge Controller

Trigger Controller

Controller

Encoder Interface

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Hall sensor Interface

TI1F_ED

Trigger & Slave Mode Controller

Hall A Hall B Hall C

XOR
Input Filter & Edge detector
TRC IC1

Prescaler

Capture/Compare 1 Register

Input Filter & Edge detector

TRC

IC2

Prescaler

Capture/Compare 2 Register

Input Filter & Edge detector

TRC

IC3

Prescaler

Capture/Compare 3 Register

TI4

Input Filter & Edge detector

TRC

IC4

Prescaler

Capture/Compare 4 Register

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Timer Link System

The four Timers are linked together for timer synchronization or chaining.

TIM1

TIM2

TIM1CLK TRG2 TRG3 TRG4

Trigger Controller

TRGO

TRG1

TIM2CLK TRG1 TRG3 TRG4

Trigger Controller

TRGO

TRG2

TI1FP1 TI2FP2

TI1FP1 TI2FP2

TIM3

TIM4

TIM3CLK TRG1 TRG2 TRG4

Trigger Controller

TRGO

TRG3

TIM4CLK TRG1 TRG2 TRG3

Trigger Controller

TRGO

TRG4

TI1FP1 TI2FP2

TI1FP1 TI2FP2

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Synchronization Mode Configuration

Clock Master ARR Master CNT

The Trigger Output can be controlled on:

Counter reset Counter enable Update event OC1 / OC1Ref / OC2Ref / OC3Ref / OC4Ref signals

Triggered Mode

Master Trigger Out

Slave CNT

The slave timer can be controlled

in two modes:
Gated Mode

Clock New Master CCR1 Master CCR1 Master CNT Master CC1

Triggered mode : only the start of the counter is controlled. Gated Mode: Both start and stop of the counter are controlled.

Slave CNT

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Synchronization Configuration examples (1/3)

Cascade mode:
TIM1 used as master timer for TIM2, TIM2 configured as TIM1 slave and master for TIM3.

MASTER Timer 1
CLOCK prescaler Update counter

Trigger Controller

TRG 1

SLAVE / MASTER Timer 2

ITR 1 ITR 3 ITR 4

prescaler

Trigger Controller
Update

TRG 2

SLAVE
counter
ITR1 ITR2

Timer 3
prescaler counter

ITR 4

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Synchronization Configuration examples (2/3)

One Master several slaves: TIM1 used as master for TIM2, TIM2 and TIM4.
MASTER Timer 1
CLOCK prescaler Update counter

SLAVE 1 Timer 2
TRG1 ITR1 ITR 3 ITR 4

Trigger Controller

prescaler

counter

SLAVE 2 Timer 3
ITR 1 ITR 2 ITR 4

prescaler

counter

SLAVE 3
ITR1 ITR 2

TIM4
prescaler counter

ITR 3

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Synchronization Configuration examples (3/3)

Timers and external trigger synchronization
TIM1, TIM2 and TIM3 are slaves for an external signal connected to respective Timers inputs.

TIM1

TIM2

TIM3

Trigger Controller

TRGO

Trigger Controller

TRGO

Trigger Controller

TRGO

External Trigger

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Other Timers

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Real Time Clock (RTC)

Clock sources 32.768 kHz dedicated oscillator (LSE) Low frequency (32kHz), low power internal RC(LSI) HSE divided by 128 3 Event/Interrupt sources Second Overflow Alarm (also connected to EXTI Line 17 for Auto Wake-Up from STOP) Register protection against unwanted write operations RTC core & clock configuration in Backup domain Independent VBAT voltage supply Reset only by Backup domain reset RTC config kept after reset or wake-up from STANDBY Calibration Capability RTC clock can be output on Tamper pin for calibration Then the clock can be adjusted from 0 to to 121ppm by a step of 1ppm
Alarm IT Overflow IT Second IT RTC Control Register (CR) RTC Counter RTC Divider RTC Alarm RTC Prescaler = fRTC LSE OSC or EXT Clock
RTCSEL [1:0]

HSE OSC LSI RC 1/128

Backup Domain

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Window Watchdog (WWDG)

Configurable time-window, can be programmed to detect abnormally late or early application behavior Conditional reset
Reset (if watchdog activated) when the down counter value becomes less than 40h (T6=0) Reset (if watchdog activated) if the down counter is reloaded outside the time-window
WWDG Reset WWDG_CFR comparator = 1 when T6:0 > W6:0 W6 W5 W4 W3 W2 W1 W0

Write WWDG_CR WDGA T6 T5 T4 T3 T2 T1 T0

CMP

To prevent WWDG reset: write T[6:0] bits (with T6 equal to 1) at regular intervals while the counter value is lower than the time-window value (W[6:0]) Early Wakeup Interrupt (EWI): occurs whenever the counter reaches 40h can be used to reload the down counter WWDG reset flag (in RCC_CSR) to inform when a WWDG reset occurs Min-max timeout value @36MHz (PCLK1): 113s / 58.25ms
Best suited to applications which require the watchdog to react within an accurate timing window
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T6 bit Reset T[6:0] CNT down counter

WWDG_CR

6-Bit Down Counter

PCLK1 (up to 36MHz)

PRESCALER (WDGTB)

W[6:0] 3Fh

Refresh not allowed

Refresh Window

time

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IWDG features
Selectable HW/SW start through option byte Advanced security features:
IWDG clocked by its own dedicated low-speed clock (LSI) and thus stays active even if the main clock fails Once enabled the IWDG cant be disabled (LSI cant be disabled too) Safe Reload Sequence (key) IWDG function implemented in the VDD voltage domain that is still functional in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY)
LSI (40KHz) 8-bit PRESCALER 12-bit down counter
VDD voltage domain 1.8V voltage domain

Prescaler Register

Status Register

Reload Register

Key Register

12-bit reload value

IWDG Reset

To prevent IWDG reset: write IWDG_KR with AAAAh key value at regular intervals before the counter reaches 0 IWDG reset flag (in RCC_CSR) to inform when a IWDG reset occurs Min-max timeout value @40KHz (LSI): 100s / 26.2s
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Best suited to applications which require the watchdog to run as a totally independent process outside the main application

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System Timer (SysTick)

Flexible system timer 24-bit self-reloading down counter with end of count interrupt generation 2 configurable Clock sources Suitable for Real Time OS or other scheduled tasks

In STM32F10x the SysTick clock can be: CPU clock or CPU clock/8
externally by the Reset Clock Control )

(provided

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Appendices

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STM32F10x Series Block Diagram

ARM 32-bit Cortex-M3 CPU Nested Vectored Interrupt Controller (NVIC) w/ 43 maskable IT + 16 prog. priority levels Embedded Memories : FLASH: up 128 Kbytes, 512kB to come e/o 2007 SRAM: up 20 Kbytes, 64kB to come e/o 2007 7 Channels DMA Power Supply with internal regulator and low power modes : 2V to 3V6 supply 4 Low Power Modes with Auto Wake-up Integrated Power On Reset (POR)/Power Down Reset (PDR) + Programmable voltage detector (PVD) Backup domain w/ 20B reg Up to 72 MHz frequency managed & monitored by the Clock Control w/ Clock Security System Rich set of peripherals & IOs Embedded low power RTC with VBAT capability Dual Watchdog Architecture 5 Timers w/ advanced control features (including Cortex SysTick) 9 communications Interfaces Up to 80 I/Os (100 pin package) w/ 16 external interrupts/event Up to 2x12-bits 1Msps ADC w/ up to 16 channels and Embedded temperature sensor w/ +/-1.5 linearity with T 1x 16-bit PWM 1x1616-bit PWM Bridge Bridge 3x 16-bit Timer 3x 16-bit Timer ARM Peripheral Bus (max 72MHz) Independent Independent Watchdog Watchdog Window Watchdog Window Watchdog 2x 12-bit ADC 2x 12-bit ADC 16 channels //1Msps 16 channels 1Msps Temp Sensor Temp Sensor 1x bxCAN 2.0B 1x bxCAN 2.0B 2x USART/LIN 2x USART/LIN Smartcard //IrDa Smartcard IrDa Modem Control Modem Control 1x SPI 1x SPI 2x I22C 2x I C DMA DMA 7 Channels 7 Channels JTAG/SW Debug JTAG/SW Debug Nested vect IT Ctrl Nested vect IT Ctrl 1x SysTick Timer 1x SysTick Timer Flash I/F Flash I/F

CORTEXM3 CORTEXM3 CPU CPU 72 MHz 72 MHz

ARM Lite Hi-Speed Bus ARM Lite Hi-Speed Bus Matrix Arbiter (max 72MHz) Matrix //Arbiter (max 72MHz)

32kB-128kB 32kB-128kB Flash Memory Flash Memory 512kB to come 512kB to come e/o 2007 e/o 2007

Power Supply Power Supply Reg 1.8V Reg 1.8V POR/PDR/PVD POR/PDR/PVD XTAL oscillators XTAL oscillators 32KHz + 4~16MHz 32KHz + 4~16MHz Int. RC oscillators Int. RC oscillators 32KHz + 8MHz 32KHz + 8MHz PLL PLL

Up to 20kB SRAM Up to 20kB SRAM 64kB to come e/o 64kB to come e/o 2007 2007 20B Backup Regs 20B Backup Regs Reset Clock Reset Clock Control Control ARM Peripheral Bus Bridge Bridge (max 36MHz)

RTC //AWU RTC AWU

1x USB 2.0FS 1x USB 2.0FS

Synchronized AC Synchronized AC Timer Timer

Up to 16 Ext. ITs Up to 16 Ext. ITs 32/49/80 I/Os 32/49/80 I/Os 1x SPI 1x SPI 1x USART/LIN 1x USART/LIN Smartcard/IrDa Smartcard/IrDa Modem-Ctrl Modem-Ctrl

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STM32F10x Series Block Diagram

ARM 32-bit Cortex-M3 CPU Nested Vectored Interrupt Controller (NVIC) w/ 43 maskable IT + 16 prog. priority levels Embedded Memories : FLASH: up 128 Kbytes, 512kB to come e/o 2007 SRAM: up 20 Kbytes, 64kB to come e/o 2007 7 Channels DMA Power Supply with internal regulator and low power modes : 2V to 3V6 supply 4 Low Power Modes with Auto Wake-up Integrated Power On Reset (POR)/Power Down Reset (PDR) + Programmable voltage detector (PVD) Backup domain w/ 20B reg Up to 72 MHz frequency managed & monitored by the Clock Control w/ Clock Security System Rich set of peripherals & IOs Embedded low power RTC with VBAT capability Dual Watchdog Architecture 5 Timers w/ advanced control features (including Cortex SysTick) 9 communications Interfaces Up to 80 I/Os (100 pin package) w/ 16 external interrupts/event Up to 2x12-bits 1Msps ADC w/ up to 16 channels and Embedded temperature sensor w/ +/-1.5 linearity with T 1x 16-bit PWM 1x 16-bit PWM Bridge Bridge 3x 16-bit Timer 3x 16-bit Timer ARM Peripheral Bus (max 72MHz) Independent Independent Watchdog Watchdog Window Watchdog Window Watchdog 2x 12-bit ADC 2x 12-bit ADC 16 channels //1Msps 16 channels 1Msps Temp Sensor Temp Sensor 1x bxCAN 2.0B 1x bxCAN 2.0B 2x USART/LIN 2x USART/LIN Smartcard //IrDa Smartcard IrDa Modem Control Modem Control 1x SPI 1x SPI 2x I22C 2x I C DMA DMA 7 Channels 7 Channels JTAG/SW Debug JTAG/SW Debug Nested vect IT Ctrl Nested vect IT Ctrl 1x SysTick Timer 1x SysTick Timer Flash I/F Flash I/F

CORTEXM3 CORTEXM3 CPU CPU 72 MHz 72 MHz

ARM Lite Hi-Speed Bus ARM Lite Hi-Speed Bus Matrix Arbiter (max 72MHz) Matrix //Arbiter (max 72MHz)

32kB-128kB 32kB-128kB Flash Memory Flash Memory 512kB to come 512kB to come e/o 2007 e/o 2007

Power Supply Power Supply Reg 1.8V Reg 1.8V POR/PDR/PVD POR/PDR/PVD XTAL oscillators XTAL oscillators 32KHz + 4~16MHz 32KHz + 4~16MHz Int. RC oscillators Int. RC oscillators 32KHz + 8MHz 32KHz + 8MHz PLL PLL

Up to 20kB SRAM Up to 20kB SRAM 64kB to come e/o 64kB to come e/o 2007 2007 20B Backup Regs 20B Backup Regs Reset Clock Reset Clock Control Control ARM Peripheral Bus Bridge Bridge (max 36MHz)

RTC //AWU RTC AWU

1x USB 2.0FS 1x USB 2.0FS

Synchronized AC Synchronized AC Timer Timer

Up to 16 Ext. ITs Up to 16 Ext. ITs 32/49/80 I/Os 32/49/80 I/Os 1x SPI 1x SPI 1x USART/LIN 1x USART/LIN Smartcard/IrDa Smartcard/IrDa Modem-Ctrl Modem-Ctrl

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