y Microprocessors 509 pit: Ne on binary digits ‘O° and ‘1’. These digits are pop- ularly known as bits, ce 8-bit microprocessor can handle a data of combination of bits formed by “0's and “1's eg. 10011000, 01110001, etc. The number of combinations depends on the number of bits and is given by the formula 2", where mis the namber of bits. Hence, for an 8-bit microprocessor the possible fombinations will be 2° = 256, pyre: A group formed by 8-bits is called a byte, ible: A group formed by 4 bits is called a nibble. Word: A group of bits which a processor can handle at a time is known as the word, The length of a word is measured in terms of the number of bits it pro- cesses, €.8-, 4, 8, 16, 32, etc. ‘A microprocessor forms the brain of the computer called the central pro- cessing unit (CPU), It-can be represented by’a simple diagram as shown in Fig. 13.2. A CPU has three sub-units namely (i) the Arithmetic logic Unit (ALU) (i) the Register Unit (RU), and (iii) the Control Unit (CU). They have been explained in the following sections. Arithmetic logic unit (ALU) Register unit RU) Control unit (CU) Fig. 13.2 Simple representation of a microprocessor 13.11. Arithmetic Logic Unit a, This part of the microprocessor is responsible for performing all types of ‘arithmetical (such as addition, subtraction, multiplication, division, etc.) and logical (such as AND, OR, EXOR, etc.) operations. 184.2 Register Unit This unit contains several registers meant for housing data during execution of any operation. Registers act like a data store. The data may either be stored in a Tegister or may be recalled whenever required, by executing different comm- ands, For the purpose of distinction separate names are given to the registers. ome of the registers can be used by user with the help of appropriate com- Mands and instructions. 1843. Control Unit The necessary timing and control signals required for execution of any opera-errr renner Eerste EE $12. Industrial Electronics and Control flags (or flip-flops). ‘The positions of these flip-flops can be either soy which is directly linked with the status of | the data either in the accu; in the other registers. The sel/reset condition of the flags depends o of the operation, These conditions can be checked by the user with appropriate instructions. The flags are affected by the arithmetic and logie operations in the ALU and they reflect the data conditions in the accumulator, Bit positions of the flags as shown in Fig. 13.4 are such that flags S,Z, AC, p and CY correspond to the bils Dy, Dg Dy, D and Dy respectively. The § flag represents the sign of the number. If after the execution of an arithmetic of logic operation the $ flag is set (D, = 1), the resultant number is taken as nega- tive and vice-versa. If the ALU operation results into 0, the Z flag is taken to be set and if the result is not zero this flag is reset. In an arithmetic operation if a carry is gen- erated by the bit D, and passed on to the bit D, the AC flag is set, After an arithmetic or logic operation if the result consists of an even number of ‘1's then the P flag is set, and in case of an odd number of ‘1's the P flag is reset. If the result of an arithmetic operation generates a carry, the CY flag is set and if no carry is generated then the CY. flag is reset. ; t OF reso Mulator of M the regu the help of Program Counter (PC) This is a 16-bit register which deals with the sequencing of execution of instructions for performing any operation. This acts like a pointer which indicates the subsequent memory location. After one instruction is executed the PC gets incremented by one to indicate the next memory loca- tion. Stack Pointer (SP) This is also a 16-bit register as shown in Fig. 13.4. Stack may be defined as a set of memory locations and stack pointer may be defined as the indicator to these memory locationis, These memory locations are used . by the MP for storing data temporarily during the execution of a program. A _ 16-bit memory address is loaded in the SP for defining the beginning of the Slack. ILis a first in, last-out type of register, 13.23 Control Unit (CU) ‘ This unit is responsi ; joni oS onal oy Controlling the entire functioning of the HP. It imi rom memory and decoding. The timing and control signals are 'y and executes them aftet for execution of the The control unit Of 8085 UP generates thee pees eee i ii three types of signals, viz., (i) th control signal, (i) the status signal and (ii : + - explained as follows. Gi) the special signal. TheyMicroprocessors 513 Timing and control unit Control Reset Status DMA RD WRALE Sy S, I,/M| HLDA Reset Ready Hold Reset in Fig. 13.5 Block diagrammatic representation of a timing and control unit (Source. Intel Corporation) contol signal This signal is responsible to enable the device for performing @ anicular task. 8085 can generate two control signals, viz. READ (RD) and WRITE (WR), as shown in Fig. 13.5. ‘The READ (RD) signal enables the uP in reading operation. Reading of the available data depends on the selection of either the memory location or the inqui/output device. A bar on top indicates that it is a low active control signal. ‘The WRITE (WR) signal enables the P in writing-the data on the selected memory location or on the input/output device through data bus. The bar indi- cates that this is also a low active signal. Status signal This signal, also generated by the control unit, enables the [LP to identify the operation to be processed. Intel 8085 can generate three status sig- tals, viz., 1O/M, S, and S, as shown in Fig. 13.5: 1O/M is a status signal which ‘differentiates between the I/O and the memory operations. This signal, if high, indicates an 1/O operation and if low, indicates a memory operation. Sj and Sp are also status signals which differentiate between HALT, WRITE, READ and OP-CODE FETCH CYCLE operations. Special signal 8085 uP can generate a special signal, called address latch emmble (ALE), which enables the address to identify the beginning of the oper- ation, This is a positive going pulse and is generated each time when the 8085 Starts performing an operation. Inaddition to the above, there is a provision of interrupt action in the 8085 ip. This action is possible by applying a signal, called the interrupt signal. 7 is signal is used to interrupt the execution of a program. There are five types Einerupt signals vz, INTR, RST 5.5, RST 6.5, RST 75, and Trap respee- i 'y. Out of these, Trap is the highest priority interrupt signal. The WP can ae the execution of a programme only if any of the. interrupt signals is o igh. INTR is the interrupt request signal. By applying the INTR signal nal ieSan be asked to execute some other program by interrupting the origi- 4 gram and after the new programie is over, the P automatically goes 0 the original program. INTR signal can be acknowledged by the Micy “Oprocessor with the help of another signal called the interrupt acknow!l-514 Industrial Electronics and Control edge (NTA) signal. The bar at its top indicates that the UP acknowleq, interrupt, only if the interrupt acknowledge signal is low. | ‘ ‘Apart from the above, there are certain external signals which can. accepted by the 8085 uP. They are as follows: Ready This is a high active signal and is applied to the UP for creating a cific delay to start functioning. If this signal is made low, the P goes to { state of waiting and does not perform. The }P keeps waiting until the RE; signal is made high. Hold This is a high active external signal. When the hold pin is activated 1 HP loses its control over the buses and instead, it hands over the buses to fi access of the user. The programmer may now use the buses directly as per th requirement of data transfer. To acknowledge the HOLD request, ther another high active signal, called hold acknowledge (HLDA), which is use of by the device. Reset in This is a low active external signal which is used to reset When this signal is made low at the reset in pin the program counte1 zero and the 1P is reset. Reset out This is a high active signal which indicates that the nP is reset condition. This signal can also be applied externally. 4 The external signals are generated by external devices which are interf with the P for different purposes. In addition to the above, the 8085 generate two more signals, called the serial input data (SID) signal serial output data (SOD) signal which are used for serial input and seri Put data transmission respectively. 18.2.4 Timings In the previous section various si section we will examine the timi clock of the device which pr quency. Since the timings of unit, this units is also kno generating the control signa for synchronising all the iP To understand the the sequence which it ignals of 8085 tP have been explained. ings of the various signals with respect | ‘Oduces a train of square pulses of 3-1 the various signals are linked with the wn as the timing and control unit. Ap Is, the timing and control. unit is also respo © Operations with its clock. clioning of a cane (@ fetching of the next instruction formed viz., the'fetch oa S, there are two basic operations 10 the uP in performing the exe, a The total duration required 19 instruction cycle (IC).516 Industrial Electronics and Control 85 instructions consist of I to 5S machine cycles and each machi coal the fetch-cycle, consists of 3-6 states, Fetch-cycle consi pS slates. . - ‘ ined earlier, the first machine cycle of an Asean the processor identifies the nature of the instruct » teh, baead d, The .P places the contents of the program. Counter on the adr ‘ ad reads the OPCODE of the instruction. This procera i8 also known seen esi read operation. Once this operation is Over, during the machine cycles the processor interprets the OPCODE and as per the interpre tation, further memory read or memory Write Operations are Performer depending on whether additional information/data are required of NOt. On completion of one instruction new ‘machine cycles are Benerated by the Pro. cessor in order to execute the subsequent instruction. It is to be Roted that q program contains several instructions in 4 Proper sequence, While executing the program the processor follows these instructions Strictly in that Sequence, 8085 P has in all seven types of machine cycles, They are given in Table 13.2, ‘The first cycle of 8085 ,tP always generates a status signal like 10/7, S, or Si. 101M specifies whether the operation is concerned with input/output device or with memory. S, specifies whether the operation is READ or WRITE. S, along with Sp specifies whether READ, WRITE, OPCODE FETCH CYCLE whether HALT state. Different instructions of 8085 enerate different machine cycles. Some of them have been dealt with in the instruction Set of 8085 uP. Y instruction j TeSS bus Table 13.2 The different machine cycles of 8085 iW) [4 [voREADGoR) 5_|vowrire dow INTR ACKNOWL.| EDGE, (INA) BUS IDLE (BS) DAD 13.2.5 Internal Structure of 8085 Figure 13.8 shows the detailed internal g tructure of an 8085 uP. The various blocks of an 8085 uP are explained as follows.SID soD INTA 16.5. Teap INTR ¢ RET 5.5 RSTgSt 73) ets via +4 [ Interrupt Control 7 Sear 770 pets & 2 Bit intemal dawa bust 2 TP ‘Accumulator = i=—| = (8) Register (8) ti F w @O]z @® Flas @) ‘Temp register| Temp register Flip - Flop [7 fe @ fe @ B[__Resiser | _Resiser ty sl > ale Oe Instruction 2] “Register | Register| E Arithmetic | Decoder gpa Of LO 1s Logie and gp|_Resiter__| Reiter 1 2 A Re ‘Stack pointer é 2 iA ‘Machine ao | 2 Unit Ee Cycle ‘Program counter (ALU) Encoding ag | tnerementer /Decremeater Address latch ao ee I ower supply {> Guy ax Timing and control unit , Address bute] (Data / Address] SSIGEN Control Reset It Buffer (8) ¢ Terese gerd AisAg * AD7~ADo cLK OUT! RD WRALE So S; 10/ MI HLDAT Reset out ‘Address bus. Address / Data Ready HOLD Reset in Buffer fan 8085 microprocessor (Source: Intel corporation ) Fig. 13.8 Internal structure oF518 Industrial Electronies and Control ic is It is an 8-bit register which is a sstruation register st h art of the Icon received from the memory is stored in this register. Fy Alu, Any ister its content is transferred to the decoder. It is to be noted that the j HS top. tion register is not programmable. It cannot be used by the programmer Instruction decoder and machine cycle encoding The instruction rece; : the instruction register is transferred to the decoder where it is decoded, gence oF events 10 follow” is also established by this unit by gen The fe machine cycles. The decoder is a logic circuit which identity 5 appropriate ‘ ead decides the course of action. Register array ‘This consists of the six general Purpose registers B,C, D, g, i L the stack pointer, the program-counter, he inerement/decrement register i two additional temporary registers W and Z, Out Of these all the general Dur. pose registers are of 8-bit capacity. The stack-pointer and the program-counter ere each of 16-bit capacity. All these have been explained earlier in Sec. 132.7 W and [Link] 8-bit registers and are used to store 8-bit data temporarily during the execution of some instruction. These registers are accessible intemally ang cannot be used externally by a programmer. The incrementdecrement register is of 16-bit capacity which stores the result after increment/decrement opera- tion, In increment operation the data is incremented by 1 and in decrement operation the data is decremented by 1. Address bus The address bus may be defined as a group of lines which is employed to communicate a memory address or a device address from the CPU to the memory location or some peripheral. The 8085 MP has a 16-bit address bus, meaning thereby that it contains 16 address lines through which a 16-bit address may be communicated, The address bus is a unidirectional group of lines, Data bus This may be defined as a group of lines which is employed to trans- fer data between the CPU and the memory or peripherals. The 8085 HP has an 8.-bit wide data bus. In other words, it has the capability of transferring a data of 8-bit capacity. The data bus is always bidirectional thereby enabling the data (0 be transferred from the CPU to the peripherals (or memory) and vice-verst Out of the total 16 lines available in the 8085 4.P, 8 lines are commonly wsed for data as well as address transfer. This group of lines is called the daalad- oon Hi ws = ADs Ties form this bus which is bidirectional. The rest otis by the 8 lines‘ a fe only used for address communication. The bus fo" 's~ A,sis unidirectional and is known as the address bus. puter ae is a logic circuit to amplify current or power. The signal oblt! rom the register array before being sent either to the address bus oF (0 data/adaress bus is to be amplified with the help of an appropriate bullet. *S per the basic requirement 8085 has two buffers ~ the address buffer and data/address buffer. Both these butters are of 8-bit capacity. Depending 0” type of instruction, the signal obtained from the register is sent either ' address buffer Or 10 the data/address butter. ‘The output from the addres ived f, inedMicroprocessors 519. yt 8 fed 0 me address bus and that from the data/address buffer is fed (0 gatoseress us. ve i soil! Oui nee : i Hae of the 8085 CPU is different from its tim- us and a eee as from the interrupt control. 8085 |P has the pews of bol fil a well as parallel’ data transmission, The serial jppovootPUt Oe See is responsible for the control of serial data transmis- snl In serial data transfer the data is transferred bit by bit serially. 8085 fs wo lines ~ Serial Input Data (SID) line and Serial Output Data (SOD) joe respectively. Both these lines are used for data communication. Data is ceived serially by the CPU through its SID line and data is transmitted seri- the CPU through its SOD line. The 8085 1P has the provision of an n called SIM for transmitting data serially through the SOD line. the data is to be transmitted serially, the SIM instruction is to be coved by une 8085. Similarly, for receiving data serially through the SID fine, the 8085 WP employs an instruction called RIM. SIM and RIM instruc- joashave been explained in detail in the next section. aconfguration of 8085 P The pin diagram of an 8085 CPU has been shown’ in Fig, 139. As evident from the diagram, the 8085 HP is @ 40-pin micro- jnstructiol very time 1 wa 40{ J Vee (#5) 2 39] HOLD RSEST OUTL_]3 38[—] HLDA sopL_|4 37{ J CLK OUT sips 36 [|] RESET IN TRAPC_|6 35[_] READY rst 7.5047 34[(10/M RST 6.5018 33[- Si RST 5.5019 808s 32RD INTR_]10 31 WR INTAC 11 30[—1 ALE ADol—]!2 29180 AD {C413 28( Ais _ AD2C4 14 a Ai AD3C-415 2 Ais ADs] 16 2s[ An ADsC]17 mtAn ADoC_4 18 23[- 1 Ato ADL] 19 22/1 Ag V,,(0V) 420 21 Ag OR GND (erases Fig. 13.9. Pin diagram of an 8085 4P (Source: Intel corporation)