Computer Organization and Architecture

Chapter 7
Central Processing Unit (CPU)

Central Processing Unit (CPU)

CPU structure and function Instruction Sets: Characteristics and Functions Instruction Sets: Addressing Modes and Formats

CPU structure and function

CPU Structure CPU must:

Fetch instructions CPU reads an instruction from memory Interpret instructions instruction is decoded to determine what action is required Fetch data execution instruction may require reading data from memory or I/O module Process data execution instruction may require doing arithmetic or logical operation on data Write data result of instruction may writing data to memory or I/O module

CPU Organization

CPU Organization cont

-The major components of the CPU are arithmetic and logic unit (ALU), Control Unit (CU) and registers. -The ALU does the actual computing or processing the data -The control unit controls the movement of data and instructions into and out of the CPU and control the operation of ALU. -Registers is a small storage location in the CPU.

CPU Internal Structure

Registers
CPU must have some working space (temporary storage) Called registers Number and function vary between processor designs One of the major design decisions Top level of memory hierarchy General roles are performed by CPU register:
User-visible register-Enable assembly-language programmer to minimize main memory references by optimizing use of registers. Control and status registers- Used by the control unit to control the operation of CPU and to control the execution of programs.

User Visible Registers General Purpose Data Address Condition Codes

General purpose-can be assigned to a variety of functions by the programmer. Can contain the operand for any opcode. Data register-used only to hold data. Address register-this register only hold address information.

Condition codes-values set by the CPU as the result of performing operations. Example code bits: zero, positive, negative

Control & Status Registers

Four register essential to instruction execution (control the movement of data between CPU and memory): Program counter (PC) contains the address of an instruction to be fetched

Instruction register (IR) Contains the instruction most recently fetched

Memory address register (MAR) Contains the address of a location in memory. Memory buffer register (MBR) Contains a word of data to be written to memory or the word most recently read.

Control & Status Registers cont.

All CPU design include a register or a set of registers known as Program Status Word (PSW), that contain status information Common fields or flags for PSW: Sign -contain the sign bit of the result of the last arithmetic operation. Zero -set when the result is 0. Carry -set if an operation resulted in a carry (addition) into or borrow (subtraction) out of a high-order bit. Equal -set if a logical compare result is equality

Overflow -Used to indicate arithmetic overflow

Interrupt enable/disable -used to enable or disable interrupts Supervisor -Indicates whether the CPU is executing in supervisor or user mode. Certain privileged instructions can be executed only in supervisor mode, and certain areas of memory can be accessed only in supervisor mode.

Example Register Organizations

Instruction Sets: Characteristics and Functions

What is an instruction set? The complete collection of instructions that are understood by a CPU Machine Code Binary Usually represented by assembly codes

Elements of an Instruction Operation code (Op code)

Do this

Source Operand reference

To this

Result Operand reference

Put the answer here

Next Instruction Reference

When you have done that, do this...

Where have all the Operands gone? The location for the source and destination for the operand can be in one of three areas: -Main memory (or virtual memory or cache) -CPU register -I/O device

Instruction Cycle State Diagram

Instruction Representation In machine code each instruction has a unique bit pattern For human consumption (well, programmers anyway) a symbolic representation is used
e.g. ADD, SUB, LOAD

Operands can also be represented in this way

ADD A,B

Simple Instruction Format

Instruction Types Data processing Data storage (main memory) Data movement (I/O) Program flow control

Number of Addresses (a) 3 addresses

Operand 1, Operand 2, Result a = b + c; May be a forth - next instruction (usually implicit) Not common Needs very long words to hold everything

Number of Addresses (b) 2 addresses

One address doubles as operand and result a = a + b Reduces length of instruction Requires some extra work
Temporary storage to hold some results

Number of Addresses (c) 1 address

Implicit second address Usually a register (accumulator) Common on early machines

Number of Addresses (d) 0 (zero) addresses

All addresses implicit Uses a stack e.g. push a push b add pop c c = a + b

How Many Addresses More addresses

More complex (powerful?) instructions More registers
Inter-register operations are quicker

Fewer instructions per program

Fewer addresses
Less complex (powerful?) instructions More instructions per program Faster fetch/execution of instructions

Types of Operand Addresses Numbers

Integer/floating point

Characters
ASCII etc.

Logical Data
Bits or flags

Types of Operation Data Transfer Arithmetic Logical Conversion I/O System Control Transfer of Control

Data Transfer Specify

Source Destination Amount of data

May be different instructions for different movements

e.g. IBM 370

Or one instruction and different addresses

e.g. VAX

Arithmetic Add, Subtract, Multiply, Divide Signed Integer Floating point ? May include
Increment (a++) Decrement (a--) Negate (-a)

Shift and Rotate Operations

Logical Bitwise operations AND, OR, NOT

Conversion E.g. Binary to Decimal

Input/Output May be specific instructions May be done using data movement instructions (memory mapped) May be done by a separate controller (DMA)

Systems Control Privileged instructions CPU needs to be in specific state

Ring 0 on 80386+ Kernel mode

For operating systems use

Transfer of Control Branch

e.g. branch to x if result is zero

Skip
e.g. increment and skip if zero ISZ Register1 Branch xxxx ADD A

Subroutine call
c.f. interrupt call

Branch Instruction

Instruction Sets: Addressing Modes and Formats

Addressing Modes Immediate Direct Indirect Register Register Indirect Displacement (Indexed) Stack

Immediate Addressing
Operand is part of instruction Operand = address field e.g. ADD 5
Add 5 to contents of accumulator 5 is operand

No memory reference to fetch data Fast Limited range

Immediate Addressing Diagram

Instruction Opcode Operand

Direct Addressing
Address field contains address of operand Effective address (EA) = address field (A) e.g. ADD A
Add contents of cell A to accumulator Look in memory at address A for operand

Single memory reference to access data No additional calculations to work out effective address Limited address space

Direct Addressing Diagram

Instruction Opcode Address A Memory

Operand

Indirect Addressing (1) Memory cell pointed to by address field contains the address of (pointer to) the operand EA = (A)
Look in A, find address (A) and look there for operand e.g. ADD (A) Add contents of cell pointed to by contents of A to accumulator

Indirect Addressing (2) Large address space 2n where n = word length May be nested, multilevel, cascaded
e.g. EA = (((A)))
Draw the diagram yourself

Multiple memory accesses to find operand Hence slower

Indirect Addressing Diagram

Instruction

Opcode

Address A

Memory Pointer to operand

Operand

Register Addressing (1) Operand is held in register named in address filed EA = R Limited number of registers Very small address field needed
Shorter instructions Faster instruction fetch

Register Addressing (2)

No memory access Very fast execution Very limited address space Multiple registers helps performance
Requires good assembly programming or compiler writing Likes C programming
register int a;

Same with Direct addressing

Register Addressing Diagram

Instruction Opcode Register Address R Registers

Operand

Register Indirect Addressing

EA = (R) Operand is in memory cell pointed to by contents of register R Large address space (2n) One fewer memory access than indirect addressing

Register Indirect Addressing Diagram

Instruction Opcode Register Address R Memory

Registers

Pointer to Operand

Operand

Displacement Addressing EA = A + (R) Address field hold two values

A = base value R = register that holds displacement or vice versa

Displacement Addressing Diagram

Instruction Opcode Register R Address A Registers Memory

Pointer to Operand

Operand

Relative Addressing A version of displacement addressing R = Program counter, PC EA = A + (PC) i.e. get operand from A cells from current location pointed to by PC locality of reference & cache usage

Indexed Addressing A = base R = displacement EA = A + R Good for accessing arrays

EA = A + R R++

Stack Addressing Operand is (implicitly) on top of stack e.g.

ADD Pop top two items from stack and add

Stack Addressing
Instruction

Implicit Top of stack register