ASSIGNMENT NO.

1
Q1:PCI Read Timing Diagram
Explanation of the PCI Read Timing Diagram

1. CLK: The clock signal that drives the synchronization of the transaction.

2. FRAME#: Indicates the beginning and duration of a transaction. It is asserted at the start of a
transaction and de-asserted when the initiator is ready to complete the final data phase.

3. AD: The Address/Data lines. The address phase occurs first, followed by data phases.

4. C/BE#: Command/Byte Enable lines. During the address phase, these lines carry the command;
during the data phases, they specify which bytes are valid.

5. IRDY#: Initiator Ready. Asserted by the initiator to indicate it is ready to complete the current
data phase.

6. TRDY#: Target Ready. Asserted by the target to indicate it is ready to complete the current data
phase.

7. DEVSEL#: Device Select. Asserted by the target to indicate it has decoded its address.

Steps in the PCI Read Timing Diagram

1. Address Phase:

o FRAME: is asserted by the initiator, indicating the start of a transaction.

o The address and command are placed on the AD and C/BE lines, respectively.

o DEVSEL: is asserted by the target when it recognizes its address.

2. Data Phase(s):

o Data is transferred between the initiator and the target during each data phase.

o IRDY and TRDY signals are used to control the data transfer. Both signals must be
asserted to complete a data phase.

o Multiple data phases can occur, with the initiator de-asserting FRAME when it is ready to
complete the final data phase.

3. Wait States:

o Wait states can occur if either the initiator or target is not ready. This is indicated by
IRDY or TRDY being de-asserted.
Specific Points in the Diagram

 a: Start of the address phase, FRAME is asserted.

 b: Address is placed on the AD lines.

 c: Command is placed on the C/BE# lines.

 d: Start of the first data phase, IRDY is asserted, indicating the initiator is ready.

 e: Byte enable for the first data phase is placed on the C/BE# lines.

 f: TRDY is asserted, indicating the target is ready.

 g: Start of the second data phase.

 h: FRAME is de-asserted, indicating the final data phase.

 i: End of the transaction, DEVSEL is de-asserted.

Q2: ASSIGNMENT NO.2

PCI Bus Arbitration
Key Points in the Timing Diagram

1. REQ#-A: Request signal from device A.

2. REQ#-B: Request signal from device B.

3. GNT#-A: Grant signal for device A.

4. GNT#-B: Grant signal for device B.

5. FRAME#: Indicates the start and duration of a transaction.

6. IRDY#: Initiator Ready signal.

7. TRDY#: Target Ready signal.

8. AD: Address/Data lines.

Sequence Analysis

 a: Device A asserts REQ#-A.

 b: Device B asserts REQ#-B.

 c: Arbiter grants the bus to Device A by asserting GNT#-A.

 d: Device A starts its transaction by asserting FRAME#.

  e: Device A completes its transaction, and the arbiter de-asserts GNT#-A.

 f: Device B is granted the bus as GNT#-B is asserted.

 g: Device B starts its transaction by asserting FRAME#.

Explanation

1. Bus Request by Device A (a): Device A asserts REQ#-A to request control of the PCI bus.

2. Bus Request by Device B (b): Shortly after Device A's request, Device B asserts REQ#-B to
request bus control.

3. Bus Grant to Device A (c): The arbiter grants the bus to Device A by asserting GNT#-A.

4. Device A Starts Transaction (d): Device A asserts FRAME# to start its transaction, which includes
address and data phases.

5. Bus Grant to Device B (f): After Device A completes its transaction and the arbiter de-asserts
GNT#-A, the arbiter grants the bus to Device B by asserting GNT#-B.

6. Device B Starts Transaction (g): Device B asserts FRAME# to start its transaction.

Q3: ASSIGNMENT NO.3

PCI Bus Aribter:
Operation of PCI Bus Arbitration

1. Request Phase:

o A PCI device that needs to use the bus asserts its REQ# line.

o The arbiter monitors all the REQ# lines from the PCI devices.

2. Grant Phase:

o The arbiter decides which device to grant access to based on its arbitration algorithm.

o The arbiter asserts the GNT# line for the chosen device.

3. Transaction Phase:

o The selected device begins its transaction by asserting the FRAME# signal and using the
bus for address and data transfer.

o Once the transaction is complete, the device de-asserts the FRAME# signal and releases
the bus.

4. Bus Release:

o The arbiter can now grant the bus to the next requesting device.
Example Scenario from the Diagram:

1. Device A Requests the Bus:

o Device A asserts REQ#-A.

2. Device B Requests the Bus:

o Device B asserts REQ#-B.

3. Arbiter Grants Bus to Device A:

o The arbiter asserts GNT#-A.

4. Device A Starts Transaction:

o Device A asserts FRAME# and starts the address phase, followed by data transfer.

5. Device A Completes Transaction:

o Device A de-asserts FRAME#, releasing the bus.

6. Arbiter Grants Bus to Device B:

o The arbiter asserts GNT#-B.

7. Device B Starts Transaction:

o Device B asserts FRAME# and starts its transaction.