CE222 - Digital Integrated Circuit Design
Nguyen Tran Son
ntsonvldt@[Link]
Feb 06, 2023
Nguyen Tran Son (∞) CMOS Inverter Feb 06, 2023 1 / 27
CMOS Inverter
Nguyen Tran Son (∞) CMOS Inverter Feb 06, 2023 2 / 27
Outline
1 CMOS Inverter
2 Voltage Transfer Characteristic
3 Switching Threshold
4 Input High Voltage VIH
5 Input Low Voltage VIL
6 Noise Margin vs. β Ratio
7 Design of CMOS inverter
8 Transient Analysis
Delay Definitions
9 Power Dissipation
Nguyen Tran Son (∞) CMOS Inverter Feb 06, 2023 3 / 27
Prefixes Used for Large or Small Physical Quantities
Table: Prefixes Used for Large or Small Physical Quantities
Prefix Abbreviation Scale Factor
giga- G 109
meg- or mega- M 106
kilo- k 103
milli- m 10−3
micro- µ 10−6
nano- n 10−9
pico- p 10−12
femto- f 10−15
Nguyen Tran Son (∞) CMOS Inverter Feb 06, 2023 4 / 27
CMOS Inverters
Goals
Understand the basic definition of basic circuit-level
parameters.
Understand the VTC of a CMOS inverter.
Understand in detail static analysis of the CMOS
inverter including circuit parameters, VOL, VOH,
VIL, VIH, NMH, NML, and trip-point.
Nguyen Tran Son (∞) CMOS Inverter Feb 06, 2023 5 / 27
CMOS Inverters
Nguyen Tran Son (∞) CMOS Inverter Feb 06, 2023 6 / 27
Voltage Transfer Characteristic (VTC)
Static characteristics of an inverter represented by its
voltage transfer characteristic.
Trip-point (switching threshold): Vout = Vin
Nguyen Tran Son (∞) CMOS Inverter Feb 06, 2023 7 / 27
Switching Threshold (Trip-point)
Switching threshold: point on VTC where Vout = Vin .
Also called midpoint VM
Calculate VM :
at VM , both NMOS and PMOS in saturation
Solve equation IDSN = IDSP for VM :
s
βn
V DD − |VT P | + VT N +
βp
VM = s
βn
1+
βp
Nguyen Tran Son (∞) CMOS Inverter Feb 06, 2023 8 / 27
Switching Threshold & β Ratio
WN
βn µn
LN
βr = =
βp WP
µp
LP
Nguyen Tran Son (∞) CMOS Inverter Feb 06, 2023 9 / 27
Input High Voltage VIH
Input High Voltage, VIH : Vin such that Vin > VIH =
logic 1
Calculate VIH :
at VIH , NMOS in linear and PMOS in saturation
Solve equation IDSN (Linear) = IDSP (Sat) with
dVout /dV in = −1 for VIH :
V DD + VT P + βr (2Vout + VT N )
VIH =
1 + βr
Nguyen Tran Son (∞) CMOS Inverter Feb 06, 2023 10 / 27
Input Low Voltage VIL
Input Low Voltage, VIL : Vin such that Vin < VIH =
logic 0
Calculate VIL :
at VIL , NMOS in saturation and PMOS in linear
Solve equation IDSN (Sat) = IDSP (Linear) with
dVout /dV in = −1 for VIL :
2Vout + VT P − V DD + βr VT N
VIL =
1 + βr
Nguyen Tran Son (∞) CMOS Inverter Feb 06, 2023 11 / 27
Noise Margin vs. β Ratio
Assume an inverter has: VOH = V DD, VOL − 0 :
VN M H = VOH − VIH = V DD − VIH
VN M L = VIL − VOL = VIL
βn
βr =
βp
Nguyen Tran Son (∞) CMOS Inverter Feb 06, 2023 12 / 27
Noise Margin & Example
VN M H = VOH − VIH
VN M L = VIL − VOL
Nguyen Tran Son (∞) CMOS Inverter Feb 06, 2023 13 / 27
Noise Margin & Example
Good noise margin case:
Nguyen Tran Son (∞) CMOS Inverter Feb 06, 2023 14 / 27
Design of CMOS inverter
Engineer point of view:
Black board!
sizing, switching threshold...
Nguyen Tran Son (∞) CMOS Inverter Feb 06, 2023 15 / 27
CMOS inverter: Transient Analysis
Transient Analysis:
Signal value as a function of time
Transient Parameters:
Output signal rise and fall time
Propagation delay
Nguyen Tran Son (∞) CMOS Inverter Feb 06, 2023 16 / 27
Delay Definitions
tpdr : rising propagation delay
MAX delay time:
Vin = 50%V DD → Voutrise =
50%V DD
tpdf : falling propagation delay
MAX delay time:
Vin = 50%V DD → Voutf all =
50%V DD
tpd : average propagation delay
tpd = (tpdr + tpdf )/2
tr : Rise time
From output crossing 0.2
VDD to 0.8 VDD
tf : Fall time
From output crossing 0.8
VDD to 0.2 VDD
Nguyen Tran Son (∞) CMOS Inverter Feb 06, 2023 17 / 27
Delay Definitions
tcdr : Rising contamination
delay
Minimum time from the
input crossing 50% to rising
the output crossing 50%
tcdf : Falling contamination
delay
Minimum time from the
input crossing 50% to
falling the output crossing
50%
tcd : Average contamination
delay
tcd = (tcdr + tcdf )/2
Nguyen Tran Son (∞) CMOS Inverter Feb 06, 2023 18 / 27
Components of CMOS Power Dissipation
Dynamic Power
Charging and discharging load capacitances
Short Circuit (Overlap) Current
Occurs when PMOS and NMOS devices are on
simultaneously
Static Current
Bias circuitry in analog circuits
Leakage Current
Reverse-biased diode leakage
Subthreshold leakage
Tunneling through gate oxide
Nguyen Tran Son (∞) CMOS Inverter Feb 06, 2023 19 / 27
CMOS Delay and Power Dissipation
Delay:
∆V CL V DD
∆T = C =
I ID
Total power dissipation :
Ptot = Pdyn + Psc + Pstat + Pleak
(tr + tf )
= αCV 2 f + V DD × Ipeak f
2
+ V DD × Istatic + V DD × Ileak
To reduce power, minimize each term – starting with
the biggest! Historically, biggest has been dynamic
power. . .
Nguyen Tran Son (∞) CMOS Inverter Feb 06, 2023 20 / 27
Energy Drawn From Power Supply
Z ∞ Z ∞
EV DD = PV DD (t)dt = iV DD (t)VDD dt
0 0
Z ∞ dvout
Z VDD
= VDD CL dt = CL VDD dvout
0 dt 0
2
= CL VDD
Nguyen Tran Son (∞) CMOS Inverter Feb 06, 2023 21 / 27
Energy Stored on Load Capacitor
Energy Stored on Capacitor:
Z ∞
EC = iV DD (t)vout dt
0
Z ∞ dvout
Z VDD
= CL vout dt = CL vout dvout
0 dt 0
1 2
= CL VDD
2
Compared to EV DD , Energy lost in p-channel
MOSFET during charging:
1 2
EDiss = EV DD − EC = CL VDD
2
This energy dissipation is independent of the size
(and hence the resistance) of the PMOS device
Nguyen Tran Son (∞) CMOS Inverter Feb 06, 2023 22 / 27
Dynamic Power
Each charge/discharge cycle dissipates total energy
EV DD
To compute power, account for switching the circuit
at frequency f
Typically, output does not switch every cycle, so we
scale the power by the probability of a transition α
Putting it all together, we derive the dynamic power
formula:
2
Pdyn = αCL VDD f
To reduce Pdyn :
V : voltage scaling
f : reduce frequency
CL : minimum device sizes, compact and custom
layout, ...
Reduce activity factor α: clock gating, latch module
inputs to eliminate glitches
Nguyen Tran Son (∞) CMOS Inverter Feb 06, 2023 23 / 27
CMOS Inverter Short Circuit Current
Nguyen Tran Son (∞) CMOS Inverter Feb 06, 2023 24 / 27
Short Circuit Current Triangle Approx.
2
PSC = αVDD Ipeak tSC f = CSC VDD f
Note: VDD < VT n + |VT p |, both devices can’t be on
simultaneously.
Short circuit power becoming less important in deep
submicron due to Threshold voltages not scaling as fast as
supply voltages
Nguyen Tran Son (∞) CMOS Inverter Feb 06, 2023 25 / 27
Design & Simulation
Using the 45nm PTM SPICE model is provided in this
course and Ngspice tool.
Process: TT/FF/SS
VDD : 0.9/1.0/1.1
T :-40/25/125
Use length of NMOS and PMOS is 60nm.
Design and simulate this Inverter:
trise , tf all < 200ps
Measure total power
dissipation
Measure leakage current
of this circuit
Nguyen Tran Son (∞) CMOS Inverter Feb 06, 2023 26 / 27
Questions?
Thank you !
Nguyen Tran Son (∞) CMOS Inverter Feb 06, 2023 27 / 27