SCES373L− SEPTEMBER 2001 − REVISED NOVEMBER 2003

D Available in the Texas Instruments DBV OR DCK PACKAGE

NanoStar and NanoFree Packages (TOP VIEW)

D Optimized for 1.8-V Operation and Is 3.6-V

NC 1 5 VCC
I/O Tolerant to Support Mixed-Mode Signal 2
A
Operation 3 4
GND Y
D Ioff Supports Partial-Power-Down Mode
Operation NC − No internal connection
D Sub 1-V Operable
YEA, YEP, YZA, OR YZP PACKAGE
D Max tpd of 2.5 ns at 1.8 V (BOTTOM VIEW)
D Low Power Consumption, 10-µA Max ICC
GND 3 4 Y
D ±8-mA Output Drive at 1.8 V
A 2
D Latch-Up Performance Exceeds 100 mA Per DNU 1 5 VCC
JESD 78, Class II
D ESD Protection Exceeds JESD 22 DNU − Do not use
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)

description/ordering information
This single buffer/driver is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V
VCC operation.
The output of the SN74AUC1G07 is open drain and can be connected to other open-drain outputs to implement
active-low wired-OR or active-high wired-AND functions.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.

ORDERING INFORMATION
ORDERABLE TOP-SIDE
TA PACKAGE†
PART NUMBER MARKING‡
NanoStar − WCSP (DSBGA)
SN74AUC1G07YEAR
0.17-mm Small Bump − YEA
NanoFree − WCSP (DSBGA)
SN74AUC1G07YZAR
0.17-mm Small Bump − YZA (Pb-free)
Tape and reel _ _ _UV_
NanoStar − WCSP (DSBGA)
−40°C to 85°C SN74AUC1G07YEPR
0.23-mm Large Bump − YEP
NanoFree − WCSP (DSBGA)
SN74AUC1G07YZPR
0.23-mm Large Bump − YZP (Pb-free)
SOT (SOT-23) − DBV Tape and reel SN74AUC1G07DBVR U07_
SOT (SC-70) − DCK Tape and reel SN74AUC1G07DCKR UV_
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
[Link]/sc/package.
‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code,
and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

NanoStar and NanoFree are trademarks of Texas Instruments.

   !" # $%&" !#  '%()$!" *!"&+ Copyright  2003, Texas Instruments Incorporated
*%$"# $ " #'&$$!"# '& ",& "&#  &-!# #"%&"#
#"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*&
"&#"0  !)) '!!&"&#+

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1


 

    
     
SCES373L− SEPTEMBER 2001 − REVISED NOVEMBER 2003

description/ordering information (continued)

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
For more information about AUC Little Logic devices, please refer to the TI application report, Applications of
Texas Instruments AUC Sub-1-V Little Logic Devices, literature number SCEA027.

FUNCTION TABLE
INPUT OUTPUT
A Y
H H
L L

logic diagram (positive logic)

2 4
A Y

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W
YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 154°C/W
YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 132°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265


 

    
     
SCES373L− SEPTEMBER 2001 − REVISED NOVEMBER 2003

recommended operating conditions (see Note 3)

MIN MAX UNIT
VCC Supply voltage 0.8 2.7 V
VCC = 0.8 V VCC
VIH High-level input voltage VCC = 1.1 V to 1.95 V 0.65 × VCC V
VCC = 2.3 V to 2.7 V 1.7
VCC = 0.8 V 0
VIL Low-level input voltage VCC = 1.1 V to 1.95 V 0.35 × VCC V
VCC = 2.3 V to 2.7 V 0.7
VI Input voltage 0 3.6 V
VO Output voltage 0 3.6 V
VCC = 0.8 V 0.7
VCC = 1.1 V 3
IOL Low-level output current VCC = 1.4 V 5 mA
VCC = 1.65 V 8
VCC = 2.3 V 9
∆t/∆v Input transition rise or fall rate 15 ns/V
TA Operating free-air temperature −40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP† MAX UNIT
IOL = 100 µA 0.8 V to 2.7 V 0.2
IOL = 0.7 mA 0.8 V 0.25
IOL = 3 mA 1.1 V 0.3
VOL V
IOL = 5 mA 1.4 V 0.4
IOL = 8 mA 1.65 V 0.45
IOL = 9 mA 2.3 V 0.6
II A input VI = VCC or GND 0 to 2.7 V ±5 µA
Ioff VI or VO = 2.7 V 0 ±10 µA
ICC VI = VCC or GND, IO = 0 0.8 V to 2.7 V 10 µA
Ci VI = VCC or GND 2.5 V 3 pF
Co VO = VCC or GND 2.5 V 3.5 pF
† All typical values are at TA = 25°C.

switching characteristics over recommended operating free-air temperature range, CL = 15 pF

(unless otherwise noted) (see Figure 1)
VCC = 1.2 V VCC = 1.5 V VCC = 1.8 V VCC = 2.5 V
FROM TO VCC = 0.8 V
PARAMETER ± 0.1 V ± 0.1 V ± 0.15 V ± 0.2 V UNIT
(INPUT) (OUTPUT)
TYP MIN MAX MIN MAX MIN TYP MAX MIN MAX
tpd A Y 4.7 0.3 3.3 0.2 2.4 ‡ ‡ ‡ ‡ ‡ ns
‡ This information was not available at the time of publication.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3


 

    
     
SCES373L− SEPTEMBER 2001 − REVISED NOVEMBER 2003

switching characteristics over recommended operating free-air temperature range, CL = 30 pF

(unless otherwise noted) (see Figure 1)
VCC = 1.8 V VCC = 2.5 V
FROM TO ± 0.15 V ± 0.2 V
PARAMETER UNIT
(INPUT) (OUTPUT)
MIN TYP MAX MIN MAX
tpd A Y 0.8 1.9 2.5 0.2 1.8 ns

operating characteristics, TA = 25°C

VCC = 1.2 V VCC = 1.5 V VCC = 1.8 V VCC = 2.5 V
PARAMETER TEST CONDITIONS UNIT
TYP TYP TYP TYP
Cpd Power dissipation capacitance f = 10 MHz 2 3 3 5 pF

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265


 

    
     
SCES373L− SEPTEMBER 2001 − REVISED NOVEMBER 2003

PARAMETER MEASUREMENT INFORMATION

2 × VCC
TEST S1
RL S1 Open
From Output tPLH/tPHL Open
Under Test GND tPLZ/tPZL 2 × VCC
CL tPHZ/tPZH GND
(see Note A) RL

VCC CL RL V∆
0.8 V 15 pF 2 kΩ 0.1 V
LOAD CIRCUIT 1.2 V ± 0.1 V 15 pF 2 kΩ 0.1 V
1.5 V ± 0.1 V 15 pF 2 kΩ 0.1 V
1.8 V ± 0.15 V 15 pF 2 kΩ 0.15 V
2.5 V ± 0.2 V 15 pF 2 kΩ 0.15 V
1.8 V ± 0.15 V 30 pF 1 kΩ 0.15 V
2.5 V ± 0.2 V 30 pF 500 Ω 0.15 V

VCC
Timing Input VCC/2
0V
tw
tsu th
VCC
VCC
Input VCC/2 VCC/2
Data Input VCC/2 VCC/2
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VCC VCC
Output
Input VCC/2 VCC/2 VCC/2 VCC/2
Control
0V 0V

tPLH tPHL tPZL tPLZ

Output
VOH VCC
Waveform 1
VCC/2 VCC/2 VCC/2
Output S1 at 2 × VCC VOL + V∆
VOL (see Note B) VOL

tPHL tPLH tPZH tPHZ

Output
VOH VOH
Waveform 2 VOH − V∆
Output VCC/2 VCC/2 VCC/2
S1 at GND
VOL (see Note B) ≈0 V

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.

Figure 1. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

 MECHANICAL DATA

MPDS025C – FEBRUARY 1997 – REVISED FEBRUARY 2002

DCK (R-PDSO-G5) PLASTIC SMALL-OUTLINE PACKAGE

0,30
0,65 0,10 M
0,15
5 4

0,13 NOM
1,40 2,40
1,10 1,80

1 3
Gage Plane
2,15
1,85
0,15

0°–8° 0,46
0,26

Seating Plane

1,10 0,10
0,10
0,80 0,00

4093553-2/D 01/02

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-203

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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