WHITE PAPER
Unlocking PPA Benefits of Backside Routing
Authors Introduction
Ashish Khurana The power delivery network (PDN) is a critical part of any modern semiconductor device. Even
Sr. Director, with advanced power-saving technologies, today’s chips are hungry for power. Traditionally,
Foundry Ecosystem R&D
power is distributed through metal layers on the same side of the substrate as the signal metal
layers. This creates competition for the available layers and pushes the limits of fabrication
Augustine Weaver
technology to add more metal with each new generation. The emerging approach of routing the
Principal Engineer,
Foundry Ecosystem R&D PDN on the backside of the substrate addresses these challenges. It frees up more room for
both the signals and the PDN, while reducing both static and dynamic IR drop. This white paper
provides an overview of this solution and the advantages for chip developers.
Background
Just like any electrical or electronic device, chips require power to operate. This means that
power and ground must be routed from the power supply to every element in the design. These
signals enter the chip through pins and pads just like logic signals, and are distributed similarly
using traces on metal layers. The dedicated power layers tend to be thicker with wider traces
than the signals layers to reduce the amount of loss due to IR drop, also known as voltage drop.
Routing power and ground for optimum delivery to all parts of the chip is the primary goal of the
PDN. This entails extensive analysis of electromigration, noise, and cross-coupling effects as
well as IR drop, to ensure power integrity.
Although this white paper focuses on the metal traces, it is worth noting that the PDN often
includes additional elements. If different parts of the chip operate at different voltages, voltage
converters may be required. Voltage regulators can be used to lower voltage or ensure a more
consistent power flow. In low-power design, it is common to temporarily reduce voltage for
portions of the chip not performing critical functions or to stop power entirely for inactive
circuitry. Power switches help to perform this function. It is also worth noting that the PDN term
is used for the power and ground distribution on a printed circuit board (PCB), but this white
paper concerns only on-chip power delivery.
Adding metal layers to a chip increases the cost and complexity of the fabrication process.
For every generation of semiconductor technology, there is a practical limit on how many
layers of metal may be added. Thus, signal and power/ground layers are effectively competing
for space. The fact that the two types of layers tend to have different characteristics also
complicates fabrication. Within the signal layers, connections to power and ground are required,
further reducing the space available for signal routing. Finally, the transition of power and ground
through many layers of metal increases the IR drop. All these issues compromise the power,
performance, and area (PPA) goals for the chip design.
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