Overview of packaging DRAMs and use of RDL
ECG 721 – Memory Circuit Design
Kostas Moutafis
April 2017
A die photograph of the Micron Technology MT4C1024 DRAM integrated circuit. It has a capacity of 1 megabit, equivalent of 2^20 bits or 128 kB [1]
What is Dynamic Random‐Access Memory (DRAM)
Random‐Access… because data can be accessed in the same amount of time irrespective of their
physical location
Dynamic… because data have to be refreshed periodically
DRAM stores each bit of data in a storage cell consisting of a capacitor and a transistor (1T1C DRAM
memory cell)
The DRAM cell (bottom left) has remained relatively the same, but
the manufacturing technology has kept it competitive for decades [2]
Where is it used?
Volatile memory
Fast but not too expensive memory
Billions of Gbits Bandwidth (MB/s)
Cost vs speed in memory hierarchy [4]
Growing and Diversifying DRAM Demand [3]
DRAM types
Asynchronous DRAM
Synchronous DRAM (SDRAM)
Single Data Rate (SDR)
Double Data Rate (DDR)
Samsung has begun mass production of 10‐nm class, 8‐Gbit DDR4 DRAM chips, which support speeds up
to 3.2GT/s (equal to 51.2GB/s) [5]
DDR4 high speed performance compared with DDR3 and DDR2 [5]
DRAM modules
Single Inline Memory Module (SIMM)
early 80s to late 90s
32‐bit data path (72 pins)
Crucial 16GB Kit (8GBx2) DDR4 2133 MT/s
UDIMM 288‐Pin Memory ([Link] ‐ $102.99)
Small
ll outline
l DIMM ((SoDIMM))
260‐pins used for DDR4 SDRAM
From top to bottom: SIMM (30‐pin), SIMM (72‐pin) [5]
Dual Inline Memory Module (DIMM)
contacts on both sides
64‐bit data path
288‐pins
288 pins used for DDR4 SDRAM Crucial 16GB Kit (8GBx2) DDR3/DDR3L 1866 MT/s
SODIMM 204‐Pin Memory ([Link] ‐ $89.99)
Why packaging?
Protection
Physical damage
Environmental damage
Electrical connections
Redistributes
d b I/O
/
Heat dissipation
Transfer
T f via
i convection
ti DRAM package evolution [6]
Increased surface area
DRAM packaging in time
Samsung: World’s fastest (Jan. 2016), mass produced DRAM, for HPC and graphics cards.
4GB HBM2 package structure – 4H x 8Gb dies – 256GB/s speed [8]
Intel 1101: The first MOS memory chip (July 1969).
A 1024‐bit DRAM, that made Intel a world leader in
memories for a decade [7]
Samsung: World’s largest capacity and highest energy efficiency (Nov. 2015), mass produced DRAM.
128GB TSV DDR4 RDIMM – 36 x (4H x 8) Gb dies – 2.4GB/s speed [9]
Memory Packaging Tradeoffs
Memory packaging tradeoffs [10]
DRAM Packaging Terminology and Stacking Technologies
Number of identical die in package. Opposing‐Face without RDL
SDP, DDP, 3DP, QDP
Re‐Distribution Layer (RDL), routes edge to center,
where DDR dies have the wire‐bond
wire bond sites
Challenges: gold wire cost, unbalanced signal length, thermals [12]
Fine Pitch Ball Grid Array (FBGA) Face‐Up with RDL
Board On Chip (BOC)
Challenges: RDL cost, thermals [12]
Face‐to‐Face (F2F) with RDL
[10, 11]
Chip on Board (COB) or Face‐Up without RDL
Challenges: RDL cost, thermals [10]
Di
Direct Chi
Chip A
Attach
h (DCA)
Challenges: gold wire cost, cost of Film‐over‐Wire material/process, thermals [12] Through Silicon Via (TSV)
DRAM packages in market today
DDR4 (Server, PC, Consumer*)
78, 96 FBGA, 96 TFBGA,
2 and 4‐die stacks using TSV (Samsung – Server DRAM)
1 and 2‐die
2 die stacks not using TSV (Samsung – Server DRAM)
Up to 8‐die stacking capability (Micron)
LPDDR4 (Smartphones, Tablets)
196, 200, 272, 344, 366, 376 FBGA
1 and 2‐die stack (Micron) 1Q16 Branded DRAM Market Share by Manufacturer [13]
Up to 8 GB of mobile DRAM in a single package (Samsung)
SK Hynix announced (Jan. 17) industry’s first 8 GB LPDDR4X
package, using 4‐die stack, for mobile devices
GDDR5 (Graphic)
170, 190 FBGA
Samsung DDR4 promo shot – 78 FBGA [5]
SK Hynix 8 GB LPDDR4 – 376 FBGA [14] *Consumer applications include: smart TV, digital cameras, set top box, gaming console
FBGA packages
Thin Small‐Outline Package (TSOP) for DDR SDRAM [15]
Ball Pitch Dimensions and Code (JESD30E) [17]
Fine‐pitch Ball Grid Array (FBGA) Packages [16] BGA Maximum Package Height Profile (JESD30E) [17]
FBGA packages: Features and Benefits
FBGA sample with different form factors [19]
BGA Surface Mount Technology (SMT) Reflow Profiles [17]
BGA Surface Mount Technology (SMT) Process Flow [17]
BGA stencils in different shapes and sizes [20] BGA Ball Attribute Before and After Reflow [17]
Why stacking?
“Memory wall”, “Memory Bottleneck”
“Hitting the Memory Wall: Implications of
the obvious” (1995) [21]
Increased package density (capacity)
Shorter paths => speed
The gap between memory and CPU performance [23]
But
But…
“Another Trip to the Wall” (2015)
Skepticism about both latency and
bandwidth [22]
[ ]
In‐memoryy processing,
p g sophisticated
p
memory controller functionality
Bandwidth‐latency curves of DDR3 and HMC systems [23]
Wire bonding
[26]
Percentage Share of Wire Shipped by Material Type [25]
Redistribution Layer (RDL)
Metal and dielectric layers on the surface Substrate routing to connect signals from
of the die to route the pads to the edges die(s) to solder balls
Wafer‐Level RDL process [28] BGA substrate routing [29]
Commercial DRAM chip after decapsulation (top).
Enlarged view of DRAM pads (bottom) [27]
Invensas’ no RDL approach
Invensas’ Tri‐Face Down (TFD) and Quad‐Face Down (QFD) packages [30]
Invensas’ Dual Face Down package (DFD) [12] Packaging costs comparisons (total assembly and package cost) [12]
Wire Bonding vs TSV
Shorter distance
Reduced RC Delays
Lower power consumption
[26]
More space for interconnections
Wider buses
Increased bandwidth
Lower profile
No spacers
Heat dissipation
Less power
Through vias
Stacked die package with 4 dies and 2 spacers [31]
[32]
TSV process flow
Wafer thinning and thin wafer handling make
die stacking manufacturing feasible [33] [33]
Bumping process flow post TSV formation [34]
Via Middle TSV process [34]
What’s next?
More dies stacked together DRAM on the same package as CPU
HBM3 promises stack heights > 8 Intel will add 16 GB of Multi‐Channel DRAM
Increased bandwidth and density (MCDRAM) on CPU package
Intel’s Knights Landing CPU architecture integrates high‐performance, on‐package memory directly onto the CPU package [35]
References (1)
[1] “How
“H tto «open» microchip
i hi andd what's
h t' iinside?”,
id ?” [Link],
t b 2012
2012. [O
[Online].
li ] A Available:
il bl
[Link] [Accessed: 22‐Mar‐2017].
[2] J. Mick, “Coalition of 20+ Tech Firms Backs MRAM as Potential DRAM, NAND Replacement”, [Link], 2013.
[Online]. Available:
[Link] dailytech com/Coalition+of+20+Tech+Firms+Backs+MRAM+as+Potential+DRAM+NAND+Replacement/article338
[Link]
[Link]. [Accessed: 22‐Mar‐2017].
[3] K. Marko, “Micron Has a Rosy Future, But Faces Bumpy Product Transition”, [Link], 2015. [Online]. Available:
[Link] [Accessed: 24‐Apr‐2017]
[4] “Where do SSDs fit: Servers or arrays?”, [Link], 2009. [Online]. Available:
[Link]
13/Issue_10/Features/Where_do_SSDs_fit__Servers_or_arrays_.html. [Accessed: 24‐Apr‐2017]
[5] “Samsung DDR4 SDRAM: The new generation of high‐performance, power‐efficient memory that delivers greater
reliability
li bilit for
f enterprise
t i applications,
li ti [Link], 2013
2013. [O
[Online].
li ] A Available:
il bl
[Link] [Accessed: 24‐Apr‐2017]
[6] [Link] [Accessed: 30‐Apr‐2017]
[7] “Five Intel chips that changed the world”, [Link], 2014. [Online]. Available:
[Link] [Accessed: 24‐Apr‐2017]
References (2)
[8] “S
“Samsung B
Begins
i M Mass P
Producing
d i W World’s
ld’ FFastest
t t DRAM – Based
B d on NNewestt High
Hi h B
Bandwidth
d idth M
Memory (HBM) IInterface”,
t f ”
[Link], 2016. [Online]. Available: [Link]
dram‐based‐on‐newest‐high‐bandwidth‐memory‐hbm‐interface. [Accessed: 25‐Apr‐2017]
[9] “Samsung Starts Mass Producing Industry’s First 128‐Gigabyte DDR4 Modules for Enterprise Servers”, [Link],
2015 [Online]
2015. [Online]. Available: [Link]
[Link] samsung com/semiconductor/insights/news/24441 [Accessed: 25‐Apr‐2017]
25 Apr 2017]
[10] R. Wolff, “Memory Packaging Technology & Modeling”, in DesignCon IBIS Summit 2014, Santa Clara, CA, 2014. [Online].
Available: [Link] [Accessed: 25‐Apr‐2017]
[11] “USER’S MANUAL: Chip Scale Package”, [Link], 2007. [Online]. Available:
[Link]
[Accessed: 25‐Apr‐2017]
[12] Z Sun et al., “xFD For High‐density DDR4 RDIM Module Applications”, [Link], 2015. [Online]. Available:
[Link] [Accessed: 25‐Apr‐2017]
[13] “[Market View] TrendForce: The Closing of Micron‐Merging‐Inotera Deal Has Delay; Further Update Will Report in Later
2016”, [Link], 2016. [Online]. Available: [Link]
[Accessed: 26‐Apr‐2017]
[14] A. Shilov, “SK Hynix Announces 8 GB LPDDR4X‐4266 DRAM Packages”, [Link], 2017. [Online]. Available:
[Link] [Accessed: 26‐Apr‐2017]
[15] [Link] [Accessed: 27‐Apr‐2017]
References (3)
[16] Fine
Fi Pit
Pitch/Fine
h/Fi Pit
Pitch
h IInterstitial
t titi l B Ballll G
Grid
id A
Array P
Packages
k (FBGA) and
d (FIBGA)
(FIBGA). (C
(Covers b
body
d sizes
i ≤ 21 mm),
) JEDEC
Publication 95 (JEP95) Design Registration 4.5, JEDEC Solid State Technology Association, 2017. [Online]. Available:
[Link] [Accessed: 26‐Apr‐2017]
[17] “Customer Service Note BGA: Manufacturer’s User Guide for Micron BGA Parts”, Micron Technology, 2011. [Online].
Available: [Link]
[Link] micron com/resource details/188d581c b150 439e 9957 f67969d4146e [Accessed: 26‐Apr‐2017]
26 Apr 2017]
[18] “Various Packages: FBGA (Fine pitch BGA)”, [Link]. [Online]. Available:
[Link] [Accessed: 27‐Apr‐2017]
[19] R. Leng, “The Secrets of PC Memory: Part 2”, Bit‐[Link], 2007. [Online]. Available: [Link]
[Link]/hardware/memory/2007/12/17/the_secrets_of_pc_memory_part_2/4. [Accessed: 27‐Apr‐2017]
[20] [Link]
BGA‐Accessories‐BGA‐reballing‐[Link]. [Accessed: 26‐Apr‐2017]
[ ] W. Wulf and S. McKee,, “Hittingg the memoryy wall: Implications
[21] p of the obvious”,, ACM SIGARCH Computer
p Architecture
News, Volume 23, Issue 1, 1995. [Online]. Available: [Link]
2011/DesignPrinciplesMulticoreProcessors/[Link]. [Accessed: 28‐Apr‐2017]
[22] M. Radulovic et al., “Another Trip to the Wall: How Much Will Stacked DRAM Benefit HPC?”, MEMSYS ’15, Washington
DC, DC, USA, 2015. [Online]. Available: [Link]
[Accessed: 28‐Apr‐2017]
References (4)
[23] J.
J Hruska,
Hruska “Phase
Phase change memory can operate thousands of times faster than current RAM”
RAM , [Link],
Extremetech com 2016.
2016
[Online]. Available: [Link]
times‐faster‐than‐current‐ram. [Accessed: 28‐Apr‐2017]
[24] “Technical Note 00‐22: Micron Wire‐Bonding Techniques”, Micron Technology, 2010. [Online]. Available:
[Link] [Accessed: 28‐Apr‐2017]
[25] J. Vardaman and D. Tracy, “Substrate and Interconnect Materials Trends in Packaging”, SEMI, 2014. [Online]. Available:
[Link] [Accessed: 28‐Apr‐2017]
[26] J. Choi, “Next Big Thing: DDR4 3DS”, Server Forum 2014, JEDEC, 2014. [Online]. Available:
[Link] [Accessed: 28‐Apr‐2017]
[27] F. Le et al., “3D chip stacking with through silicon‐vias (TSVs) for vertical interconnect and underfill dispensing”, Journal of
Micromechanics and Microengineering, Volume 27, Number 4, 2017. [Online]. Available:
[Link] [Accessed: 28‐Apr‐2017]
[28] W. Zohni, “Near Term Solutions for 3D Memory Stacking (DRAM)”, Invensas Corporation, 2014. [Online]. Available:
h //
[Link]
/ / df [Accessed:
[ d 28‐Apr‐2017]]
[29] E. Bogatin, Roadmaps of Packaging technology, Integrated Circuit Engineering, AZ, 1997. [Online]. Available:
[Link] [Accessed: 29‐Apr‐2017]
[30] “Invensas xFD Product Selection Guide”, Invensas. [Online]. Available: [Link]
000120R B I
000120RevB‐Invensas_xFD_Selection_Guide.pdf.
FD S l i G id df [Accessed:
[A d 29‐Apr‐2017]
29 A 2017]
[31] [Link] [Accessed: 28‐Apr‐2017]
References (5)
[32] [Link]
htt // l t i /i i ht f l di d / t t/ l d / it /4/2016/02/ l 5 j [Accessed:
[A d 28‐Apr‐
28 A
2017]
[33] B. Black, “DIE stacking is happening!”, AMD, 2013. [Online]. Available:
[Link] [Accessed: 30‐Apr‐2017]
[34] Y. Li, 3D Microelectronic Packaging: From Fundamentals to Applications, Springer Series in Advanced Microelectronics,
vol. 57, Cham, Switzerland: Springer International Publishing, 2017. [Online]. Available:
[Link] [Accessed: 30‐Apr‐2017]
[35] “High‐Performance On‐Package Memory”, Micron Technology. [Online]. Available:
[Link] [Accessed: 30‐Apr‐2017]
Questions?
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