Current Mirrors

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-1 郭泰豪, Analog IC Design, 2018
 Current Source and Sink
 Symbol of current source +
V Io
- I
 Ideal current source
V Io
 Output resistance 
I

 Practical I-V characteristics

V
 Current sink  Current source
Slope=1/Ro Slope=(-1/Ro)
I I
VP VP
+
V Io
Circuit Io Io
+ - I
I
V Io Circuit
VN - V VN VP-V
VP
{

{
VN VMIN VN VMIN VP
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-2 郭泰豪, Analog IC Design, 2018
 Simple Current Mirrors
 BJT Iout
+
Iin
V Iout

Q VMIN
-
0.0V 0.36V 0.72V 1.08V 1.44V 1.8 V
Vmin  VCE(sat) V=VCE
 MOSFET
Iout
+
Iin
Iout
V
VMIN
-
0.0V 0.36V 0.72V 1.08V 1.44V 1.8 V
Vmin  VGS  VT V=VDS
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-3 郭泰豪, Analog IC Design, 2018
 Increase Output Resistance of Current Mirrors Using
Cascode Structures
Iout Iout
Iin + Iin +

Q2 M4 M2
V V

Q1 M3 M1
 

 Output impedance
 BJT: Ro = ro2[1+(gm2+go2)(r2//ro1)]  ro2(1+gm2r2)
 MOSFET: Ro = rds2[1+(gm2+gmb2+gds2)rds1]  rds2gm2rds1
 Minimum output voltage DC gain of M2
 BJT: Vmin = VCE1 + VCE2(sat) ≈ VBE(on) + VCE2(sat)
 MOSFET (assume the same size of M1-4  same Veff):
Vg4 = Vgs3+Vgs4 = 2Veff +2VT; VDS1 = Vg4 –Vgs2 = Veff +VT
Vmin= VDS2(sat) + VDS1 = Veff + (Veff + VT) = 2Veff + VT
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-4 郭泰豪, Analog IC Design, 2018
 Wide-Swing Current Mirrors
 rds=1/λI and L↓ ⇨ λ↑
 For shorter channel lengths, L↓ ⇨ rds↓ ⇨ OPAMP gain ↓
 Cascode current mirrors can be used to increase output impedance.
However, their signal swings are reduced.
 Wide-swing cascode current mirrors are needed.
 Example VDD
 The basic idea is to bias the
Ibias Iin Iout = Iin
drain-source voltages of
transistors Q2 and Q3 to be Vbias
W /L W /L
close to the minimum possible W / L Q n n2 2

5
(n  1) Q42
Q1
without them going into the
triode region.
Q3 Q2
 Q2 and Q3 must be biased right at the
W/L W/L
edge of the triode region.

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-5 郭泰豪, Analog IC Design, 2018
 Wide-Swing Current Mirrors (Cont.)
 Let Veff be the effective transistor VDS= Veff
gate-source voltage, VGS-Vth, which is IDS
also the minimum VDS for a transistor to
VGS
be biased in the saturation region.
 Assume all of the transistor drain currents
are equal, then VDS
2ID2  n Cox W
Veff 2  Veff 3   Veff ( I D 2  (VGS  Vth ) 2 )
 n Cox ( W L) 2 L
w w 2 w  2 w  2 w 
Since       n  1    n    n  
 L  2  L 3  L 5  L 1  L 4
Veff 1  Veff 4  nVeff
VG5  VG4  VG1  (n  1)Veff  Vth
VDS2  VDS3  VG5  VGS1  VG5  (nVeff  Vth )  Veff
Vout  Veff 1  Veff 2  (n  1)Veff
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-6 郭泰豪, Analog IC Design, 2018
 Wide-Swing Current Mirrors (Cont.)
 A common choice: n = 1, Vout > 2Veff

 For a safe design

 If Iin = Ibias, VDS2 should be made a little larger (>Veff), 0.05V to
0.1V larger depending on transistor I-V or whether body effect
exists.
W W
Choose a little larger   and  
 L 2  L 3

 If Iin is a varying current, Iin ≤ Ibias must be satisfied

(i.e. VDS2 = VDS3 ≥ Veff)

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-7 郭泰豪, Analog IC Design, 2018
 Constant Transconductance Bias Circuit
 Biasing circuits that provide stable transconductances
 Transistor transconductances are matched
to the conductance of a resistor. As a result, 25 25
to a first-order effect, the transistor Q10 Q11
transconductances are independent of
25 25
power-supply voltage as well as process
and temperature variations. Q14 Q12
100
25
Q15 Q13
 Example RB
w w w w w
         
 L 10  L 11  L 12  L 13  L 14
Unity current mirror

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-8 郭泰豪, Analog IC Design, 2018
 Constant Transconductance Bias Circuit (Cont.)
Veff 13  Veff 15  I D15R B • • • the other current mirror equation
I D13  I D15
2ID13
g m13 
Veff 13

 Simple derivation

21 
W L 13 
 V  Veff 15   W L15 
 
1
g m13  2 eff 13  
 RB  Veff 13 RB

 gm13 is determined by geometric ratios only, independent of power-

supply voltages, process parameters, temperature, or any other
parameters with large variability.
 At point A, loop gain I D10 B
( W L)11 ( W L)15 I D10  I D11
 
( W L)10 ( W L)13
start up circuit
is needed
A I D11
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-9 郭泰豪, Analog IC Design, 2018
 Constant Transconductance Bias Circuit (Cont.)

w w
 For a special case,    4 
1  L 15  L 13
g m13 
RB
 Thus, not only is gm13 stablized, but all other transistor
transconductances are also stablized since the ratios of transistor
currents are mainly dependent on geometry.

 For all n-channel transistors

( W L)i I Di
g mi   g m13
( W L)13 I D13
 For all p-channel transistors
 p ( W L) i I Di
g mi   g m13
 n ( W L)13 I D13

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-10 郭泰豪, Analog IC Design, 2018
 Constant Transconductance Bias Circuit (Cont.)
 Second-order effect
 Body effect
The equations will be slightly modified
 Output impedance effect
Can be reduced using cascoded p-channel current mirror
 Temperature effect
(i) μ is proportional to T-3/2. This corresponds to a 27% μ
reduction from 27℃(300°k) to 100℃(373°k)
(ii) Since gm = 1/RB and gm = μCox(W/L)Veff
Veff will be increased by 27% if temperature effect of RB is
ignored. (positive TC of RB, if it is on-chip, can somewhat
offset this increase)
(iii) As long as Veff has not been designed to be too large (or VDD is
large enough), this limitation is tolerable in most applications.

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-11 郭泰豪, Analog IC Design, 2018
 Input Stage Bias
 Widlar current sources IREF IC10
 Bipolar
VBE11  VBE10  I C10 R4
I
 VT ln REF  I C10 R4 Q11 Q10
I C10
 Trial and error to determine I C10 R4
 I C10  19 μA
-VEE
 MOSFET
VOV 11  VOV 10  I D10  R4 ' IREF ID10
I I
assume I D  K  VOV  REF  D10  I D10  R4 '
2

K K
 
2

1 1 I
   4 R4 ' REF
I D10 
K K K
0
M11 M10
2 R4 '
R4’
1  2 R4 ' KI REF  1  4 R4 ' KI REF
 I D10 
2 K R4 ' -VEE
2

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-12 郭泰豪, Analog IC Design, 2018
 Wide-Swing Constant Transconductance Bias Circuit
 Wide-swing current mirrors + constant gm bias circuit
Vbias-p
20 1 20 1
Q7 Q11 5 1.6 Vcasc-p
Q8 Q14
20 1
20 1.6 2 20 Small W/L
20 1.6 Q6
Q9 Q18
Q10 20 1.6
10 1
10 1.6 10 1
10 1.6 10 1.6 Q15
Q4
Q1 Q16
Q13
40 1 10 1 10 1
Q2 Q5 Q12 Q17
Q3 10 1
2.5 1.6
RB 5kΩ Vcasc-n
Vbias-n

Bias loop Cascode bias Start-up circuitry

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-13 郭泰豪, Analog IC Design, 2018
Wide-Swing Constant Transconductance Bias Circuit (Cont.)
 Wide-swing :
 Minimize VDS of bias transistors to Veff
 Constant gm : gm = 1/RB
 Minimization of finite output impedance effect :
 Use cascode bias
 Start-up
 Approximate current characteristics of the bias loop

I DS ( Q8 ) I DS( Q 7 )  I DS( Q8 )

A I DS ( Q7 )

( W / L) 7 ( W / L) 2
At point A, loop gain   4
( W / L) 8 ( W / L) 3

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-14 郭泰豪, Analog IC Design, 2018
Wide-Swing Constant Transconductance Bias Circuit (Cont.)
 Start-up (Cont.)
 Positive feedback bias loop:
Two stable points, A and B.
At point A, loop gain > 1 must be satisfied.
 Operational principle of start-up circuit
 All currents in the bias loop are zero, Q17 will be off
 Q18 is always on, the gates of Q15 and Q16 will be pulled high
 Q15 and Q16 will inject currents into the bias loop, which will start
up the circuit.
 Once the loop starts up, Q17 will be on, pulling the gates of Q15
and Q16 low, and thereby turning them off so they no longer
affect the bias loop.
 This circuit is only one example of a start-up loop, and there are
many other variations.
 For example, sometimes Q18, is replaced by an actual resistor

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-15 郭泰豪, Analog IC Design, 2018
 Enhanced-Output-Impedance Current Mirrors
 General structure
 For wide-swing, Vbias ≈ Veff2 Iout
Rout
Vbias Vout
 Rout ≈ gm1rds1rds2(1+A) Iin A
 This technique for output- Q1
impedance enhancement is
not useful when bipolar
Transistors (Q1, Q2, and Q3) Q3 Q2
are used.

 Rout might be limited by Rdb.

 This parasitic conductance, Rdb, is a result of collisions between
highly energized electrons resulting in electron-hole pairs to be
generated with the holes escaping to the substrate. The
generation of these electron-hole pairs is commonly called
impact ionization.

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-16 郭泰豪, Analog IC Design, 2018
Enhanced-Output-Impedance Current Mirrors (Cont.)
 A simple implementation example : regulated cascode mirror
R out  g m1rds1rds 2 [1  g m3 (rds3 || ro )] Rout
r
where rds 3 || ro  ds 3 Ibias
2 Iin
It is not useful when bipolar ro
Q1
transistors are used. Q3
Vds2 = Veff3 + Vth(not a wide-swing source)
Q4 Q2

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-17 郭泰豪, Analog IC Design, 2018
Enhanced-Output-Impedance Current Mirrors (Cont.)
 Sackinger implementation

Iout
Iin Ib1 Ib2

Q4 ro Q1

Q6 Q3

Q5 Q2

 Use regulated cascode to increase output impedance

r
 R out  g m1rds1rds 2 [1  g m3 (rds3 || ro )] where rds 3 || ro  ds 3
2
 Q1, Q2, Q3, IB1, Iout match Q4, Q5, Q6, IB2, Iin, respectively.
 VDS2 = VDS5 = Veff3 + Vtn rather than the minimum required, which
could be equal to Veff2. This limitation is especially harmful for
modern technologies operating with power voltages of 3.3V or lower.
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-18 郭泰豪, Analog IC Design, 2018
Enhanced-Output-Impedance Current Mirrors (Cont.)
 Wide-swing + enhance output-impedance current mirrors

Iin 7Ibias 4Ibias 4Ibias

Iout=Iin
Ibias Ibias
70 70
Q5 10 10 Q1
Q7 Q8 Q4 Q3
10 10

80
Q2
Q6

 Level shift in front of the common source amplifier in the regulated

cascode current source

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-19 郭泰豪, Analog IC Design, 2018
Enhanced-Output-Impedance Current Mirrors (Cont.)
 All transistors are biased with nearly the same current density,
except for Q3 and Q7. As a result, all transistors have the same
effective gate-source voltage, Veff, except for Q3 and Q7, which have
gate-source voltage of 2Veff because they are biased at four times
the current density.
 VG3 = 2Veff + Vtn
 VDS2 = VS4 = VG3 - VGS4 = (2Veff + Vtn ) - (Veff + Vtn ) = Veff
 Vout > VDS2 + Veff1 = 2Veff

Current Mirror Symbol

 Symbol  A circuit example
VDD VDD

1 K

1:K

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-20 郭泰豪, Analog IC Design, 2018
 Increase Output Resistance of Current Mirrors Using
Emitter/Source-Degenerated Structures
 Large Ro of current source/sink => more like ideal current source/sink

 For MOSFET  For BJT

1 V
Ro  R o  AF
λI o IC
1 W
I  K ' ( )(VGS  VT ) 2 (1  λVDS ) IC  IS (1 eVBE/VI )(1 VCE /VAF )
2 L

 Negative feedback to increase Ro

 Emitter-Degenerated
 Source-Degenerated

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan App4-1

4-21 郭泰豪, Analog IC Design, 2018
 Increase Output Resistance of Current Mirrors Using
Emitter/Source-Degenerated Structures (Cont.)
 Emitter-Degenerated gmvbe
ΔI
E
Iout C +
-
R vbe rπ ro Δv
+
Iin + -
Ro

V V  I(r // R )  [I  g m I(r // R )]ro

VE 1
 Iro [ (r // R )  1  g m (r // R )]
ro
R R
 Iro [1  (g m  g o )(r // R )]
-
V
Ro   ro [1  (g m  g o )(r // R )]
I
 ro [1  g m (r // R )]
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan App4-2
4-22 郭泰豪, Analog IC Design, 2018
 Increase Output Resistance of Current Mirrors Using
Emitter/Source-Degenerated Structures (Cont.)
 Source-Degenerated

Iout ΔI
D
Iin
+ +
Ro
rds
gmvgs gmbvbs
V ΔV
S
R R R
-
-
G

V
Similarly, R o   rds 1  g m  g mb  g ds R   rds 1  g m R 
I

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan App4-3

4-23 郭泰豪, Analog IC Design, 2018
 Increase Ro Using Wilson Current Mirror
 BJT Iout Iout
Iin
I out  Iin (1  β 2 2β 1
) + +
F F
Iin
ro3β F3
rout  2
Q3 V Q4 Q3
out
Vout
Q1 Q2
 Q1 Q2

 MOSFET Iout
Iin
rout  rds3g m3 (rds1//rin ) +

 g m3rds1rds3 M4 M3
Vout

M1 M2


Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan App4-4

4-24 郭泰豪, Analog IC Design, 2018
 Increase Ro Using Widlar Current Mirror (Cont.)
 Large area ratio caused by large current ratio is reduced
Iout
VBE1  VBE2  I C2R 2 Iin +
Vt ln( )  I C2R 2
I in
I C2
Q1 Q2 V
out

R2


 Iterative method to obtain the value of IC2

rout=ro2(1+gm2R2)
(For CMOS implementation, Q1 and Q2 are NMOS)

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan App4-5

4-25 郭泰豪, Analog IC Design, 2018
 BiCMOS Cascode Current Mirrors
 BiCMOS
Q2 Ro=ro2
(same as bipolar cascode)
M1

M2

Ro=gm2ro2ro1=10M
Q1

 Vo>VBE+VCE(sat) (BJT)
 Vo>Vgs+VDS(sat) (MOSFET)
 Vo>Vgs+VCE(sat) (BiCMOS)
 Ro(BiCMOS)Ro(BJT)>Ro(CMOS)
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan App4-6
4-26 郭泰豪, Analog IC Design, 2018
 BiCMOS Double Cascode Current Mirrors
 BJT
 For =100, VA=50V, Io=100A, ro=50M Q3
 Ro= ro3
 No improvement from cascode Q2
 Vo > 2VBE + VCE(sat)=Vmin
Q1

 MOSFET
 For(W/L)2=5, nCox=40A/V2, =0.1V-1, gmro2=2M M3
 Ro=(gm3ro3)(gm2ro2)ro1
 With same parameter as before M2
 Ro=40M
 Vo > 2VGS + VDS(sat)=Vmin M1

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan App4-7

4-27 郭泰豪, Analog IC Design, 2018
 BiCMOS Double Cascode Current Mirrors (Cont.)
 BiCMOS
 Ro=(gm3ro3)ro2=1000M M3
 Pratical limit : stray conductance
 Vo > 2VBE+VDS(sat)=Vmin Q2

Q1

 The highest Ro can be realized by using BiCMOS or CMOS. However,

Ro(BiCMOS) > Ro(CMOS) & Vmin(BiCMOS) < Vmin(CMOS). (In general, Vgs>VBE)
BiCMOS provides larger voltage swing.

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan App4-8

4-28 郭泰豪, Analog IC Design, 2018
 Stability of Constant gm Bias
Vbat
R VSG1  VSG2  I ref  R
M1 M2
1：k 2 1  1 
2
(W/L)P K*(W/L)P  I ref   2 1   or 0
μ p C OX W L P R  K
Iref Iref
Vbias_l
 g m1  2μ p C OX W L P  I ref
(W/L)N (W/L)N
1 K
M4 M3  g m1   g m2 
R R

 DC loop gain, A0
 1   gm 2   1 
Vbat A 0  gm 4          
R  1 
gm 1  gm 2 R   gm 3 

1：k  1   gm 2   1 
M1 M2  gm 4          positive
 1 
gm 1  gm 2 R   gm 3 
feedback
 
 R  
Vo K R K
 1
M4 M3 1   
K R  R  1 K
Vi stable at DC
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan App4-9
4-29 郭泰豪, Analog IC Design, 2018
 Stability of Constant gm Bias (Cont.)
 AC voltage loop gain z1
VDD
Vo  gm 4 gm 2  sRCP  1
   
R Vi  gm1 gm 3  sC1 / g m 3  1sC2 / g m1  1(sRCP  g m 2 R  1)
1:k
Cp Vo p2 p3 p1
M1 M2 Loop gain
Large Cp
Vi
Small Cp
Vo
nb A0
C2 M4 M3 C1
Vi z1 p1 p2 z1' p3 p1'
f

 With large Cp  positive feedback loop and loop gain > 1  Unstable
 Pole-zero pair induced by Cp and R
 ωZ1 is always less than ωP1 : P1 Z1  1  g m2 R  1  k
 ωP1 ≤ ωP2 and ωP1 ≤ ωP3  loop gain > 1  the bias circuit unstable
 Solution: Add an on-chip capacitor at node nb , such that ωP2 ≤ ωZ1
g m3 1  n C oxn ( W L) M 3
P 2  Z1    C1  g m 3 RC p  C p Stability compensation
C1 RC p  p C oxp ( W L) M1 criteria
 Furthermore, C1↗  PSRR↗
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan App4-10
4-30 郭泰豪, Analog IC Design, 2018
Example: Stability Compensation of Constant gm Bias
 Constant gm bias circuit VDD
 T-like 0.18μm process R
1:k
 Parameter
M1 M2 Cp
gm1 53.5μS R 20kΩ
gm2 96.3μS Cp 3pF
nb
gm3,4 88μS C1 46fF C2 M4 M3 C1
Ibias 7.2μA C2 135fF 1:1

 Stability of bias circuit

1  g m2R g g
 P1   2  7.76MHz , P 2  m 3  2  304.5MHz , P 3  m1  2  63.1MHz
RC P C1 C2
ωP1 < ωP2 and ωP1 < ωP3  unstable

 Stability compensation
 Add an on-chip capacitor at node nb such that ωP2 < ωZ1
C1  g m3RC p  1.76Cp  5.28pF

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan App4-11

4-31 郭泰豪, Analog IC Design, 2018