EXPERIMENT 1

Half Adder And Full Adder

Aim:
To Design a Half Adder and Full Adder using
1. Gate-level Model Design
2. Dataflow Model Design
3. Behavioural Model Design

Apparatus Required:
➢Vivado Software
➢Windows OS

Procedure:
➢Open Vivado Software and select “Create Project”.
➢Enter the Project name and Project location.
➢Choose the Project Type to “RTL Project” and press Next.
➢In the Add Sources page, create a new Verilog File using the “Create
File” option under the “+” option.
➢In the Default Part page, select “ZedBoard Zynq Evaluation and
Development kit” from the Boards and finish the setup.
➢Enter the Code in the Design Source file and run the “Behavioural
Simulation” from the Simulation Section to observe the output and note
down the values.

1
Program:
Half Adder:
Gate-Level model
module ADDER(s,c,a,b);
input a,b;
output s,c;
xor(s,a,b);
and(c,a,b);
endmodule

Data Flow model

module DFM(s,c,a,b);
input a,b;
output s,c;
assign{c,s}=a+b;
endmodule

Behavioural model
module BFM(s,c,a,b);
input a,b;
output reg s,c;
always @(a or b)
begin
{c,s}=a+b;
end

2
Test bench
module ha_tb;
reg a,b;
wire s,c;
ADDER x3(s,c,a,b);
initial
begin
a=0;b=0;#100;
a=0;b=1;#100;
a=1;b=0;#100;
a=1;b=1;#100;
end;
endmodule

Output:

3
Full Adder
Gate-Level model
module fagm(s,c,a,b,c1);
input a,b,c1;
output s,c;
wire t1,t2,t3;
xor x1(s,a,b,c1);
xor y1(t1,a,b);
and y2(t2,t1,c1);
and y3(t3,a,b);
or X2(c,t3,t2);
endmodule

Data Flow model

module fadm(s,c,a,b,c1);
input a,b,c1;
output s,c;
assign s = a^b^c1;
assign c = (a*b)+(c1*(a^b));
endmodule

Behavioural model
module fabm(s,c,a,b,c1);
input a,b,c1;
output reg s,c;
always @ (a or b or c1)
begin

4
s = a^b^c1;
c = (a*b)+(c1*(a^b));
end
endmodule

Test bench
module fa_tb;
reg a,b,c1;
wire s,c;
fahabm X3(s,c,a,b,c1);
initial
begin
a=0;b=0;c1=0;#100;
a=0;b=0;c1=1;#100;
a=0;b=1;c1=0;#100;
a=0;b=1;c1=1;#100;
a=1;b=0;c1=0;#100;
a=1;b=0;c1=1;#100;
a=1;b=1;c1=0;#100;
a=1;b=1;c1=1;#100;
end
endmodule

5
Output:

Result:
Hence, a Half Adder and Full Adder are designed and their characteristics are
observed.

6
 EXPERIMENT 2
Full Adder using Half Adder

Aim:
To Design a Full Adder using Half Adder in
1. Gate-level Model Design
2. Dataflow Model Design
3. Behavioural Model Design

Apparatus Required:
➢Vivado Software
➢Windows OS

Procedure:
➢Open Vivado Software and select “Create Project”.
➢Enter the Project name and Project location.
➢Choose the Project Type to “RTL Project” and press Next.
➢In the Add Sources page, create a new Verilog File using the “Create
File” option under the “+” option.
➢In the Default Part page, select “ZedBoard Zynq Evaluation and
Development kit” from the Boards and finish the setup.
➢Enter the Code in the Design Source file and run the “Behavioural
Simulation” from the Simulation Section to observe the output and note
down the values.

7
Program:
Gate-Level model
module fahagm(s,c,a,b,c1);
input a,b,c1;
output s,c;
wire t1,t2,t3;
ha y1(t1,t2,a,b);
ha y2(s,t3,t1,c1);
or y3(c,t2,t3);
endmodule

module ha(s,c,a,b);
input a,b;
output reg s,c;
always @ (a or b)
begin
{c,s} = a+b;
end
endmodule

Data Flow Model

module fahadm(s,c,a,b,c1);
input a,b,c1;
output s,c;
wire t1,t2,t3;
ha ha1(t1,t2,a,b);
ha ha2(s,t3,t1,c1);

8
assign c = t3+t2;
endmodule

module ha(s,c,a,b);
input a,b;
output reg s,c;
always @ (a or b)
begin
{c,s} = a+b;
end
endmodule

Behavioural Model
module fahabm(s,c,a,b,c1);
input a,b,c1;
output reg s,c;
reg t1,t2,t3;
always @ (a or b or c)
begin
ha(t1,t2,a,b);
ha(s,t3,t1,c1);
c = t3+t2;
end
endmodule

module ha(s,c,a,b);
input a,b;

9
output reg s,c;
always @ (a or b)
begin
{c,s} = a+b;
end
endmodule

Test Bench
module fa_tb;
reg a,b,c1;
wire s,c;
fahagm X3(s,c,a,b,c1);
initial
begin
a=0;b=0;c1=0;#100;
a=0;b=0;c1=1;#100;
a=0;b=1;c1=0;#100;
a=0;b=1;c1=1;#100;
a=1;b=0;c1=0;#100;
a=1;b=0;c1=1;#100;
a=1;b=1;c1=0;#100;
a=1;b=1;c1=1;#100;
end
endmodule

10
Output:

Result:
Hence, a Full Adder using Half Adder is designed and its characteristics are
observed.

11
 EXPERIMENT 3
Binary to Gray Converter

Aim:
To Design a Binary to Gray Converter using
1. Gate-level Model Design
2. Dataflow Model Design
3. Behavioural Model Design

Apparatus Required:
➢Vivado Software
➢Windows OS

Procedure:
➢Open Vivado Software and select “Create Project”.
➢Enter the Project name and Project location.
➢Choose the Project Type to “RTL Project” and press Next.
➢In the Add Sources page, create a new Verilog File using the “Create
File” option under the “+” option.
➢In the Default Part page, select “ZedBoard Zynq Evaluation and
Development kit” from the Boards and finish the setup.
➢Enter the Code in the Design Source file and run the “Behavioural
Simulation” from the Simulation Section to observe the output and note
down the values.

12
Program:
Gate-Level Model
module binarytogrey(g0,g1,g2,g3,b0,b1,b2,b3);
input b0,b1,b2,b3;
output g0,g1,g2,g3;
assign g0=b0;
xor X1(g1,b0,b1);
xor X2(g2,b2,b1);
xor X3(g3,b2,b3);
endmodule

Data Flow Model

module binarytogrey_dm(g0,g1,g2,g3,b0,b1,b2,b3);
input b0,b1,b2,b3;
output g0,g1,g2,g3;
assign g0=b0;
assign g1=b0^b1;
assign g2=b1^b2;
assign g3=b3^b2;
endmodule

Behavioural Model
module binarytogrey_bm(g0,g1,g2,g3,b0,b1,b2,b3);
input b0,b1,b2,b3;
output reg g0,g1,g2,g3;
always @(b0 or b1 or b2 or b3)
begin

13
assign g0=b0;
assign g1=b0^b1;
assign g2=b1^b2;
assign g3=b3^b2;
end
endmodule

Test Bench
module binarytogrey_tb();
reg b0,b1,b2,b3;
wire g0,g1,g2,g3;
binarytogrey_bm x5(g0,g1,g2,g3,b0,b1,b2,b3);
initial
begin
b0=0;b1=0;b2=0;b3=0;#50;
b0=0;b1=0;b2=0;b3=1;#50;
b0=0;b1=0;b2=1;b3=0;#50;
b0=0;b1=0;b2=1;b3=1;#50;
b0=0;b1=1;b2=0;b3=0;#50;
b0=0;b1=1;b2=0;b3=1;#50;
b0=0;b1=1;b2=1;b3=0;#50;
b0=0;b1=1;b2=1;b3=1;#50;
b0=1;b1=0;b2=0;b3=0;#50;
b0=1;b1=0;b2=0;b3=1;#50;
b0=1;b1=0;b2=1;b3=0;#50;
b0=1;b1=0;b2=1;b3=1;#50;
b0=1;b1=1;b2=0;b3=0;#50;

14
b0=1;b1=1;b2=0;b3=1;#50;
b0=1;b1=1;b2=1;b3=0;#50;
b0=1;b1=1;b2=1;b3=1;#50;
end
endmodule

Output:

Result:
Hence, a Binary to Gray Converter is designed and its characteristics are
observed.

15
 EXPERIMENT 4
Gray To Binary Converter

Aim:
To Design a Gray to Binary Converter using
1. Gate-level Model Design
2. Dataflow Model Design
3. Behavioural Model Design

Apparatus Required:
➢Vivado Software
➢Windows OS

Procedure:
➢Open Vivado Software and select “Create Project”.
➢Enter the Project name and Project location.
➢Choose the Project Type to “RTL Project” and press Next.
➢In the Add Sources page, create a new Verilog File using the “Create
File” option under the “+” option.
➢In the Default Part page, select “ZedBoard Zynq Evaluation and
Development kit” from the Boards and finish the setup.
➢Enter the Code in the Design Source file and run the “Behavioural
Simulation” from the Simulation Section to observe the output and note
down the values.

16
Program:
Gate-Level Model
module gtb(b3,b2,b1,b0,g3,g2,g1,g0);
output b0,b1,b2,b3;
input g0,g1,g2,g3;
assign b3=g0;
xor X1(b2,b3,g1);
xor X2(b1,b2,g2);
xor X3(b0,b1,g3);
endmodule

Data Flow Model

module gtb_dm(b3,b2,b1,b0,g3,g2,g1,g0);
output b0,b1,b2,b3;
input g0,g1,g2,g3;
assign b3=g0;
assign b2=b3^g1;
assign b1=b2^g2;
assign b0=b1^g3;
endmodule

Behavioural Model
module gtb_bm(b3,b2,b1,b0,g3,g2,g1,g0);
output reg b0,b1,b2,b3;
input g0,g1,g2,g3;
always @(g0 or g1 or g2 or g3)
begin

17
assign b3=g0;
assign b2=b3^g1;
assign b1=b2^g2;
assign b0=b1^g3;
end
endmodule

Test Bench
module gtb_tb();
wire b0,b1,b2,b3;
reg g0,g1,g2,g3;
gtb_dm x5(b3,b2,b1,b0,g3,g2,g1,g0);
initial
begin
g0=0;g1=0;g2=0;g3=0;#50;
g0=0;g1=0;g2=0;g3=1;#50;
g0=0;g1=0;g2=1;g3=1;#50;
g0=0;g1=0;g2=1;g3=0;#50;
g0=0;g1=1;g2=1;g3=0;#50;
g0=0;g1=1;g2=1;g3=1;#50;
g0=0;g1=1;g2=0;g3=1;#50;
g0=0;g1=1;g2=0;g3=0;#50;
g0=1;g1=1;g2=0;g3=0;#50;
g0=1;g1=1;g2=0;g3=1;#50;
g0=1;g1=1;g2=1;g3=1;#50;
g0=1;g1=1;g2=1;g3=0;#50;
g0=1;g1=0;g2=1;g3=0;#50;

18
 g0=1;g1=0;g2=1;g3=1;#50;
g0=1;g1=0;g2=0;g3=1;#50;
g0=1;g1=0;g2=0;g3=0;#50;

end
endmodule

Output:

Result:
Hence, a Gray to Binary Converter is designed and its characteristics are
observed.

19
 EXPERIMENT 5
2 to 4 Decoder

Aim:
To Design a 2 to 4 Decoder using
1. Gate-level Model Design
2. Dataflow Model Design
3. Behavioural Model Design

Apparatus Required:
➢Vivado Software
➢Windows OS

Procedure:
➢Open Vivado Software and select “Create Project”.
➢Enter the Project name and Project location.
➢Choose the Project Type to “RTL Project” and press Next.
➢In the Add Sources page, create a new Verilog File using the “Create
File” option under the “+” option.
➢In the Default Part page, select “ZedBoard Zynq Evaluation and
Development kit” from the Boards and finish the setup.
➢Enter the Code in the Design Source file and run the “Behavioural
Simulation” from the Simulation Section to observe the output and note
down the values.

20
Program:
Gate-Level Model
module d2to4_gm(d3,d2,d1,d0,a1,a0);
input a1,a0;
output d3,d2,d1,d0;
wire t1,t2;
not y1(t1,a1);
not y2(t2,a0);
and X1(d0,t1,t2);
and X2(d1,t1,a0);
and X3(d2,a1,t2);
and X5(d3,a1,a0);
endmodule

Data Flow Model

module d2to4_dm(d3,d2,d1,d0,a1,a0);
input a1,a0;
output d3,d2,d1,d0;
wire t1,t2;
assign t1=~a1;
assign t2=~a0;
assign d0=t1&t2;
assign d1=t1&a0;
assign d2=a1&t2;
assign d3=a1&a0;
endmodule

21
Behavioural Model
module d2to4_bm(d3,d2,d1,d0,a1,a0);
input a1,a0;
output reg d3,d2,d1,d0;
reg t1,t2;
always @(a1 or a0)
begin
assign t1=~a1;
assign t2=~a0;
assign d0=t1&t2;
assign d1=t1&a0;
assign d2=a1&t2;
assign d3=a1&a0;
end
endmodule

Test Bench
module d2to4_tb();
reg a1,a0;
wire d3,d2,d1,d0;
d2to4_bm x4(d3,d2,d1,d0,a1,a0);
initial
begin
a1=0;a0=0;#100;
a1=0;a0=1;#100;
a1=1;a0=0;#100;
a1=1;a0=1;#100;

22
end
endmodule

Output:

Result:
Hence, a 2 to 4 Decoder is designed and its characteristics are observed.

23
 EXPERIMENT 6
8 to 1 Multiplexer

Aim:
To Design a 8 to 1 Multiplexer using
1. Gate-level Model Design
2. Dataflow Model Design
3. Behavioural Model Design

Apparatus Required:
➢Vivado Software
➢Windows OS

Procedure:
➢Open Vivado Software and select “Create Project”.
➢Enter the Project name and Project location.
➢Choose the Project Type to “RTL Project” and press Next.
➢In the Add Sources page, create a new Verilog File using the “Create
File” option under the “+” option.
➢In the Default Part page, select “ZedBoard Zynq Evaluation and
Development kit” from the Boards and finish the setup.
➢Enter the Code in the Design Source file and run the “Behavioural
Simulation” from the Simulation Section to observe the output and note
down the values.

24
Program:
Gate-Level Model
module m8to1_gm(y,d0,d1,d2,d3,d4,d5,d6,d7,s0,s1,s2);
input s0,s1,s2,d0,d1,d2,d3,d4,d5,d6,d7;
output y;
wire t0,t1,t2,m0,m1,m2,m3,m4,m5,m6,m7;
not z1(t0,s0);
not z2(t1,s1);
not z3(t2,s2);
and z4(m0,t0,t1,t2,d0);
and z5(m1,t0,t1,s2,d1);
and z6(m2,t0,s1,t2,d2);
and z7(m3,t0,s1,s2,d3);
and z8(m4,s0,t1,t2,d4);
and z9(m5,s0,t1,s2,d5);
and z10(m6,s0,s1,t2,d6);
and z11(m7,s0,s1,s2,d7);
or z12(y,m0,m1,m2,m3,m4,m5,m6,m7);
endmodule

Data Flow Model

module m8to1_dm(y,d0,d1,d2,d3,d4,d5,d6,d7,s0,s1,s2);
input s0,s1,s2,d0,d1,d2,d3,d4,d5,d6,d7;
output y;
wire t0,t1,t2,m0,m1,m2,m3,m4,m5,m6,m7;
assign t0=~s0;
assign t1=~s1;

25
assign t2=~s2;
assign m0=t0&t1&t2&d0;
assign m1=t0&t1&s2&d1;
assign m2=t0&s1&t2&d2;
assign m3=t0&s1&s2&d3;
assign m4=s0&t1&t2&d4;
assign m5=s0&t1&s2&d5;
assign m6=s0&s1&t2&d6;
assign m7=s0&s1&s2&d7;
assign y=m0+m1+m2+m3+m4+m5+m6+m7;
endmodule

Behavioural Model
module m8to1_bm(y,d0,d1,d2,d3,d4,d5,d6,d7,s0,s1,s2);
input s0,s1,s2,d0,d1,d2,d3,d4,d5,d6,d7;
output reg y;
reg t0,t1,t2,m0,m1,m2,m3,m4,m5,m6,m7;
always @(s0 or s1 or s2 or d0 or d1 or d2 or d3 or d4 or d5 or d6 or d7)
begin
assign t0=~s0;
assign t1=~s1;
assign t2=~s2;
assign m0=t0&t1&t2&d0;
assign m1=t0&t1&s2&d1;
assign m2=t0&s1&t2&d2;
assign m3=t0&s1&s2&d3;
assign m4=s0&t1&t2&d4;

26
assign m5=s0&t1&s2&d5;
assign m6=s0&s1&t2&d6;
assign m7=s0&s1&s2&d7;
assign y=m0+m1+m2+m3+m4+m5+m6+m7;
end
endmodule

Test Bench
module m8to1_gm_tb();
reg a,b,c1,d0,d1,d2,d3,d4,d5,d6,d7;;
wire y;
m8to1_dm x1(y,d0,d1,d2,d3,d4,d5,d6,d7,a,b,c1);
initial
begin
d0=1;d1=0;d2=0;d3=0;d4=0;d5=0;d6=0;d7=0;a=0;b=0;c1=0;#100;
d0=0;d1=0;d2=0;d3=0;d4=0;d5=0;d6=0;d7=0;a=0;b=0;c1=1;#100;
d0=0;d1=0;d2=1;d3=0;d4=0;d5=0;d6=0;d7=0;a=0;b=1;c1=0;#100;
d0=0;d1=0;d2=0;d3=0;d4=0;d5=0;d6=0;d7=0;a=0;b=1;c1=1;#100;
d0=0;d1=0;d2=0;d3=0;d4=1;d5=0;d6=0;d7=0;a=1;b=0;c1=0;#100;
d0=0;d1=0;d2=0;d3=0;d4=0;d5=0;d6=0;d7=0;a=1;b=0;c1=1;#100;
d0=0;d1=0;d2=0;d3=0;d4=0;d5=0;d6=1;d7=0;a=1;b=1;c1=0;#100;
d0=0;d1=0;d2=0;d3=0;d4=0;d5=0;d6=0;d7=0;a=1;b=1;c1=1;#100;
end
endmodule

27
Output:

Result:
Hence, a 8 to 1 Multiplexer is designed and its characteristics are observed.

28
 EXPERIMENT 7
1 to 8 Demultiplexer

Aim:
To Design a 1 to 8 Demultiplexer using
1. Gate-level Model Design
2. Dataflow Model Design
3. Behavioural Model Design

Apparatus Required:
➢Vivado Software
➢Windows OS

Procedure:
➢Open Vivado Software and select “Create Project”.
➢Enter the Project name and Project location.
➢Choose the Project Type to “RTL Project” and press Next.
➢In the Add Sources page, create a new Verilog File using the “Create
File” option under the “+” option.
➢In the Default Part page, select “ZedBoard Zynq Evaluation and
Development kit” from the Boards and finish the setup.
➢Enter the Code in the Design Source file and run the “Behavioural
Simulation” from the Simulation Section to observe the output and note
down the values.

29
Program:
Gate-Level Model
module dm1to8_gm(y0,y1,y2,y3,y4,y5,y6,y7,d,s2,s1,s0);
input d,s2,s1,s0;
output y0,y1,y2,y3,y4,y5,y6,y7;
wire t0,t2,t1;
not z1(t0,s0);
not z2(t1,s1);
not z3(t2,s2);
and x1(y0,d,t2,t1,t0);
and x2(y1,d,t2,t1,s0);
and x3(y2,d,t2,s1,t0);
and x4(y3,d,t2,s1,s0);
and x5(y4,d,s2,t1,t0);
and x6(y5,d,s2,t1,s0);
and x7(y6,d,s2,s1,t0);
and x8(y7,d,s2,s1,s0);
endmodule

Data Flow Model

module dm1to8_dm(y0,y1,y2,y3,y4,y5,y6,y7,d,s2,s1,s0);
input d,s2,s1,s0;
output y0,y1,y2,y3,y4,y5,y6,y7;
wire t0,t2,t1;
assign t0=~s0;
assign t1=~s1;
assign t2=~s2;

30
assign y0=d&t2&t1&t0;
assign y1=d&t2&t1&s0;
assign y2=d&t2&s1&t0;
assign y3=d&t2&s1&s0;
assign y4=d&s2&t1&t0;
assign y5=d&s2&t1&s0;
assign y6=d&s2&s1&t0;
assign y7=d&s2&s1&s0;
endmodule

Behavioural Model
module dm1to8_bm(y0,y1,y2,y3,y4,y5,y6,y7,d,s2,s1,s0);
input d,s2,s1,s0;
output reg y0,y1,y2,y3,y4,y5,y6,y7;
reg t0,t2,t1;
always @(d or s2 or s1 or s0)
begin
assign t0=~s0;
assign t1=~s1;
assign t2=~s2;
assign y0=d&t2&t1&t0;
assign y1=d&t2&t1&s0;
assign y2=d&t2&s1&t0;
assign y3=d&t2&s1&s0;
assign y4=d&s2&t1&t0;
assign y5=d&s2&t1&s0;
assign y6=d&s2&s1&t0;

31
assign y7=d&s2&s1&s0;
end
endmodule

Test Bench
module dm1to8_gm_tb();
reg b0,b1,b2,b3;
wire y0,y1,y2,y3,y4,y5,y6,y7;
dm1to8_bm x10(y0,y1,y2,y3,y4,y5,y6,y7,b0,b1,b2,b3);
initial
begin
b0=0;b1=0;b2=0;b3=0;#50;
b0=0;b1=0;b2=0;b3=1;#50;
b0=0;b1=0;b2=1;b3=0;#50;
b0=0;b1=0;b2=1;b3=1;#50;
b0=0;b1=1;b2=0;b3=0;#50;
b0=0;b1=1;b2=0;b3=1;#50;
b0=0;b1=1;b2=1;b3=0;#50;
b0=0;b1=1;b2=1;b3=1;#50;
b0=1;b1=0;b2=0;b3=0;#50;
b0=1;b1=0;b2=0;b3=1;#50;
b0=1;b1=0;b2=1;b3=0;#50;
b0=1;b1=0;b2=1;b3=1;#50;
b0=1;b1=1;b2=0;b3=0;#50;
b0=1;b1=1;b2=0;b3=1;#50;
b0=1;b1=1;b2=1;b3=0;#50;
b0=1;b1=1;b2=1;b3=1;#50;

32
end
endmodule

Output:

Result:
Hence, a 1 to 8 Demultiplexer is designed and its characteristics are observed.

33
 EXPERIMENT 8
8 to 3 Encoder

Aim:
To Design a 8 to 3 Encoder using
1. Gate-level Model Design
2. Dataflow Model Design
3. Behavioural Model Design

Apparatus Required:
➢Vivado Software
➢Windows OS

Procedure:
➢Open Vivado Software and select “Create Project”.
➢Enter the Project name and Project location.
➢Choose the Project Type to “RTL Project” and press Next.
➢In the Add Sources page, create a new Verilog File using the “Create
File” option under the “+” option.
➢In the Default Part page, select “ZedBoard Zynq Evaluation and
Development kit” from the Boards and finish the setup.
➢Enter the Code in the Design Source file and run the “Behavioural
Simulation” from the Simulation Section to observe the output and note
down the values.

34
Program:
Gate-Level Model
module e8to3_gm(a2,a1,a0,y7,y6,y5,y4,y3,y2,y1,y0);
input y7,y6,y5,y4,y3,y2,y1,y0;
output a2,a1,a0;
or x1(a2,y7,y6,y5,y4);
or x2(a1,y7,y6,y3,y2);
or x3(a0,y7,y3,y5,y1);
endmodule

Data Flow Model

module e8to3_dm(a2,a1,a0,y7,y6,y5,y4,y3,y2,y1,y0);
input y7,y6,y5,y4,y3,y2,y1,y0;
output a2,a1,a0;
assign a2=y7+y6+y5+y4;
assign a1=y7+y6+y3+y2;
assign a0=y7+y3+y5+y1;
endmodule

Behavioural Model
module e8to3_bm(a2,a1,a0,y7,y6,y5,y4,y3,y2,y1,y0);
input y7,y6,y5,y4,y3,y2,y1,y0;
output reg a2,a1,a0;
always @( y7 or y6 or y5 or y4 or y3 or y2 or y1 or y0)
begin
assign a2=y7+y6+y5+y4;
assign a1=y7+y6+y3+y2;

35
assign a0=y7+y3+y5+y1;
end
endmodule

Test Bench
module e8to3_tb();
reg y7,y6,y5,y4,y3,y2,y1,y0;
wire a2,a1,a0;
e8to3_dm x4(a2,a1,a0,y7,y6,y5,y4,y3,y2,y1,y0);
initial
begin
y7=0;y6=0;y5=0;y4=0;y3=0;y2=0;y1=0;y0=1;#100;
y7=0;y6=0;y5=0;y4=0;y3=0;y2=0;y1=1;y0=0;#100;
y7=0;y6=0;y5=0;y4=0;y3=0;y2=1;y1=0;y0=0;#100;
y7=0;y6=0;y5=0;y4=0;y3=1;y2=0;y1=0;y0=0;#100;
y7=0;y6=0;y5=0;y4=1;y3=0;y2=0;y1=0;y0=0;#100;
y7=0;y6=0;y5=1;y4=0;y3=0;y2=0;y1=0;y0=0;#100;
y7=0;y6=1;y5=0;y4=0;y3=0;y2=0;y1=0;y0=0;#100;
y7=1;y6=0;y5=0;y4=0;y3=0;y2=0;y1=0;y0=0;#100;
end
endmodule

36
Output:

Result:
Hence, a 8 to 3 Encoder is designed and its characteristics are observed.

37
 EXPERIMENT 9
3 to 8 Decoder using 2 to 4 Decoder

Aim:
To Design a 3 to 8 Decoder using 2 to 4 Decoder in Gate-level Model Design.

Apparatus Required:
➢Vivado Software
➢Windows OS

Procedure:
➢Open Vivado Software and select “Create Project”.
➢Enter the Project name and Project location.
➢Choose the Project Type to “RTL Project” and press Next.
➢In the Add Sources page, create a new Verilog File using the “Create
File” option under the “+” option.
➢In the Default Part page, select “ZedBoard Zynq Evaluation and
Development kit” from the Boards and finish the setup.
➢Enter the Code in the Design Source file and run the “Behavioural
Simulation” from the Simulation Section to observe the output and note
down the values.

Program:
module d3to8using2to4(y7,y6,y5,y4,y3,y2,y1,y0,a2,a1,a0);
input a2,a1,a0;
wire t3;

38
output y7,y6,y5,y4,y3,y2,y1,y0;
not m1(t3,a2);
d2to4_gm z1(y3,y2,y1,y0,t3,a1,a0);
d2to4_gm z2(y7,y6,y5,y4,a2,a1,a0);
endmodule

module d2to4_gm(d3,d2,d1,d0,en,a1,a0);
input a1,a0,en;
output d3,d2,d1,d0;
wire t1,t2;
not y1(t1,a1);
not y2(t2,a0);
and X1(d0,t1,t2,en);
and X2(d1,t1,a0,en);
and X3(d2,a1,t2,en);
and X5(d3,a1,a0,en);
endmodule

Test Bench
module d3to8using2to4_tb();
reg a2,a1,a0;
wire y7,y6,y5,y4,y3,y2,y1;
d3to8using2to4 n1(y7,y6,y5,y4,y3,y2,y1,y0,a2,a1,a0);
initial
begin
a2=0;a1=0;a0=0;#100;
a2=0;a1=0;a0=1;#100;

39
a2=0;a1=1;a0=0;#100;
a2=0;a1=1;a0=1;#100;
a2=1;a1=0;a0=0;#100;
a2=1;a1=0;a0=1;#100;
a2=1;a1=1;a0=0;#100;
a2=1;a1=1;a0=1;#100;
end
endmodule

Output:

Result:
Hence, a 3 to 8 Decoder using 2 to 4 Decoder is designed and its characteristics
are observed.

40
 EXPERIMENT 10
16 to 1 Multiplexer using 8 to 1 Multiplexer

Aim:
To Design a 16 to 1 Multiplexer using 8 to 1 Multiplexer using in Gate-level
Model design .

Apparatus Required:
➢Vivado Software
➢Windows OS

Procedure:
➢Open Vivado Software and select “Create Project”.
➢Enter the Project name and Project location.
➢Choose the Project Type to “RTL Project” and press Next.
➢In the Add Sources page, create a new Verilog File using the “Create
File” option under the “+” option.
➢In the Default Part page, select “ZedBoard Zynq Evaluation and
Development kit” from the Boards and finish the setup.
➢Enter the Code in the Design Source file and run the “Behavioural
Simulation” from the Simulation Section to observe the output and note
down the values.

Program:
module
m16to1using8to1(y,d0,d1,d2,d3,d4,d5,d6,d7,d8,d9,d10,d11,d12,d13,d14,d15,s3,
s2,s1,s0 );
input d0,d1,d2,d3,d4,d5,d6,d7,d8,d9,d10,d11,d12,d13,d14,d15,s3,s2,s1,s0;

41
output y;
wire p1,p2;
m8to1_gm v1(p1,d0,d1,d2,d3,d4,d5,d6,d7,s2,s1,s0);
m8to1_gm v2(p2,d8,d9,d10,d11,d12,d13,d14,d15,s2,s1,s0);
m2to1 v3(y,s3,p1,p2);
endmodule

module m2to1(y,s,a,b);
input s,a,b;
output y;
wire m1,m2,m3;
not n1(m1,s);
and n2(m2,a,m1);
and n4(m3,b,s);
or n3(y,m2,m3);
endmodule

module m8to1_gm(y,d0,d1,d2,d3,d4,d5,d6,d7,s0,s1,s2);
input s0,s1,s2,d0,d1,d2,d3,d4,d5,d6,d7;
output y;
wire t0,t1,t2,m0,m1,m2,m3,m4,m5,m6,m7;
not z1(t0,s0);
not z2(t1,s1);
not z3(t2,s2);
and z4(m0,t0,t1,t2,d0);
and z5(m1,t0,t1,s2,d1);

42
and z6(m2,t0,s1,t2,d2);
and z7(m3,t0,s1,s2,d3);
and z8(m4,s0,t1,t2,d4);
and z9(m5,s0,t1,s2,d5);
and z10(m6,s0,s1,t2,d6);
and z11(m7,s0,s1,s2,d7);
or z12(y,m0,m1,m2,m3,m4,m5,m6,m7);
endmodule

Test Bench
module m16to1using8to1_tb();
reg d0,d1,d2,d3,d4,d5,d6,d7,d8,d9,d10,d11,d12,d13,d14,d15,s3,s2,s1,s0 ;
wire y;
m16to1using8to1
r1(y,d0,d1,d2,d3,d4,d5,d6,d7,d8,d9,d10,d11,d12,d13,d14,d15,s3,s2,s1,s0 );
initial
begin
d0=1;d1=0;d2=0;d3=0;d4=0;d5=0;d6=0;d7=0;d8=0;d9=0;d10=0;d11=0;d12=0;
d13=0;d14=0;d15=0;s3=0;s2=0;s1=0;s0=0;#50;
d0=0;d1=0;d2=0;d3=0;d4=0;d5=0;d6=0;d7=0;d8=0;d9=0;d10=0;d11=0;d12=0;
d13=0;d14=0;d15=0;s3=0;s2=0;s1=0;s0=1;#50;
d0=0;d1=0;d2=1;d3=0;d4=0;d5=0;d6=0;d7=0;d8=0;d9=0;d10=0;d11=0;d12=0;
d13=0;d14=0;d15=0;s3=0;s2=0;s1=1;s0=0;#50;
d0=0;d1=0;d2=0;d3=0;d4=0;d5=0;d6=0;d7=0;d8=0;d9=0;d10=0;d11=0;d12=0;
d13=0;d14=0;d15=0;s3=0;s2=0;s1=1;s0=1;#50;
d0=0;d1=0;d2=0;d3=0;d4=1;d5=0;d6=0;d7=0;d8=0;d9=0;d10=0;d11=0;d12=0;
d13=0;d14=0;d15=0;s3=0;s2=1;s1=0;s0=0;#50;
d0=0;d1=0;d2=0;d3=0;d4=0;d5=0;d6=0;d7=0;d8=0;d9=0;d10=0;d11=0;d12=0;
d13=0;d14=0;d15=0;s3=0;s2=1;s1=0;s0=1;#50;

43
d0=0;d1=0;d2=0;d3=0;d4=0;d5=0;d6=1;d7=0;d8=0;d9=0;d10=0;d11=0;d12=0;
d13=0;d14=0;d15=0;s3=0;s2=1;s1=1;s0=0;#50;
d0=0;d1=0;d2=0;d3=0;d4=0;d5=0;d6=0;d7=0;d8=0;d9=0;d10=0;d11=0;d12=0;
d13=0;d14=0;d15=0;s3=0;s2=1;s1=1;s0=1;#50;
d0=0;d1=0;d2=0;d3=0;d4=0;d5=0;d6=0;d7=0;d8=1;d9=0;d10=0;d11=0;d12=0;
d13=0;d14=0;d15=0;s3=1;s2=0;s1=0;s0=0;#50;
d0=0;d1=0;d2=0;d3=0;d4=0;d5=0;d6=0;d7=0;d8=0;d9=0;d10=0;d11=0;d12=0;
d13=0;d14=0;d15=0;s3=1;s2=0;s1=0;s0=1;#50;
d0=0;d1=0;d2=0;d3=0;d4=0;d5=0;d6=0;d7=0;d8=0;d9=0;d10=1;d11=0;d12=0;
d13=0;d14=0;d15=0;s3=1;s2=0;s1=1;s0=0;#50;
d0=0;d1=0;d2=0;d3=0;d4=0;d5=0;d6=0;d7=0;d8=0;d9=0;d10=0;d11=0;d12=0;
d13=0;d14=0;d15=0;s3=1;s2=0;s1=1;s0=1;#50;
d0=0;d1=0;d2=0;d3=0;d4=0;d5=0;d6=0;d7=0;d8=0;d9=0;d10=0;d11=0;d12=1;
d13=0;d14=0;d15=0;s3=1;s2=1;s1=0;s0=0;#50;
d0=0;d1=0;d2=0;d3=0;d4=0;d5=0;d6=0;d7=0;d8=0;d9=0;d10=0;d11=0;d12=0;
d13=0;d14=0;d15=0;s3=1;s2=1;s1=0;s0=1;#50;
d0=0;d1=0;d2=0;d3=0;d4=0;d5=0;d6=0;d7=0;d8=0;d9=0;d10=0;d11=0;d12=0;
d13=0;d14=1;d15=0;s3=1;s2=1;s1=1;s0=0;#50;
d0=0;d1=0;d2=0;d3=0;d4=0;d5=0;d6=0;d7=0;d8=0;d9=0;d10=0;d11=0;d12=0;
d13=0;d14=0;d15=0;s3=1;s2=1;s1=1;s0=1;#50;
end
endmodule

44
Output:

Result:
Hence, a 16 to 1 Multiplexer using 8 to 1 Multiplexer is designed and its
characteristics are observed.

45
 EXPERIMENT 11
Flip Flops

Aim:
To Design a Flip Flops - JK,SR,D,T in Behavioural Model Design.

Apparatus Required:
➢Vivado Software
➢Windows OS

Procedure:
➢Open Vivado Software and select “Create Project”.
➢Enter the Project name and Project location.
➢Choose the Project Type to “RTL Project” and press Next.
➢In the Add Sources page, create a new Verilog File using the “Create
File” option under the “+” option.
➢In the Default Part page, select “ZedBoard Zynq Evaluation and
Development kit” from the Boards and finish the setup.
➢Enter the Code in the Design Source file and run the “Behavioural
Simulation” from the Simulation Section to observe the output and note
down the values.

Program:
SR Flip Flop
module srff(q,s,r,q0,c);
input s,r,q0,c;

46
output reg q;
always @(s or r or c==1)
begin
if(s==0 && r==0)
begin
q=q0;
end
else if(s==1 && r==0)
begin
q=1;
end
else if(s==0 && r==1)
begin
q=0;
end
else if(s==1 && r==1)
begin
q=1'bx;
end
end
endmodule

Test Bench
module ff_tb();
reg s,r,q0,c;
wire q;
srff x1(q,s,r,q0,c);

47
initial
begin
c=1;s=0;r=0;q0=0;#50;
c=0;s=0;r=0;q0=0;#50;
c=1;s=0;r=0;q0=1;#50;
c=0;s=0;r=0;q0=1;#50;
c=1;s=0;r=1;q0=0;#50;
c=0;s=0;r=1;q0=0;#50;
c=1;s=0;r=1;q0=1;#50;
c=0;s=0;r=1;q0=1;#50;
c=1;s=1;r=0;q0=0;#50;
c=0;s=1;r=0;q0=0;#50;
c=1;s=1;r=0;q0=1;#50;
c=0;s=1;r=0;q0=1;#50;
c=1;s=1;r=1;q0=0;#50;
c=0;s=1;r=1;q0=0;#50;
c=1;s=1;r=1;q0=1;#50;
c=0;s=1;r=1;q0=1;#50;
end
endmodule

Output:

48
JK Flip Flop
module jkff(q,j,k,q0,c);
input j,k,q0,c;
output reg q;
always @(j or k or c==1)
begin
if(j==0 && k==0)
begin
assign q=q0;
end
else if(j==1 && k==0)
begin
assign q=1;
end
else if(j==0 && k==1)
begin
assign q=0;
end
else if(j==1 && k==1)
begin
assign q=~q0;
end
end
endmodule

49
Test Bench
module jkff_tb();
reg j,k,q0,c;
wire q;
jkff x1(q,j,k,q0,c);
initial
begin
c=1;j=0;k=0;q0=0;#50;
c=0;j=0;k=0;q0=0;#50;
c=1;j=0;k=0;q0=1;#50;
c=0;j=0;k=0;q0=1;#50;
c=1;j=0;k=1;q0=0;#50;
c=0;j=0;k=1;q0=0;#50;
c=1;j=0;k=1;q0=1;#50;
c=0;j=0;k=1;q0=1;#50;
c=1;j=1;k=0;q0=0;#50;
c=0;j=1;k=0;q0=0;#50;
c=1;j=1;k=0;q0=1;#50;
c=0;j=1;k=0;q0=1;#50;
c=1;j=1;k=1;q0=0;#50;
c=0;j=1;k=1;q0=0;#50;
c=1;j=1;k=1;q0=1;#50;
c=0;j=1;k=1;q0=1;#50;
end
endmodule

50
Output:

D Flip Flop
module dff(q,d,q0,c);
input d,q0,c;
output reg q;
always @(d or c==1)
begin
q=d;
end
endmodule

Test Bench
module dff_tb();
reg d,q0,c;
wire q;
dff x1(q,d,q0,c);
initial
begin
c=1;d=0;q0=0;#50;

51
c=0;d=0;q0=0;#50;
c=1;d=0;q0=1;#50;
c=0;d=0;q0=1;#50;
c=1;d=1;q0=0;#50;
c=0;d=1;q0=0;#50;
c=1;d=1;q0=1;#50;
c=0;d=1;q0=1;#50;

Output:

T Flip Flop
module tff(q,t,q0,c);
input t,q0,c;
output reg q;
always @(t or c==1)
begin
if(t==0)
begin
q=q0;
end
else
begin

52
q=~q0;
end
end
endmodule

Test Bench
module tff_tb();
reg t,q0,c;
wire q;
tff x1(q,t,q0,c);
initial
begin
c=1;t=0;q0=0;#50;
c=0;t=0;q0=0;#50;
c=1;t=0;q0=1;#50;
c=0;t=0;q0=1;#50;
c=1;t=1;q0=0;#50;
c=0;t=1;q0=0;#50;
c=1;t=1;q0=1;#50;
c=0;t=1;q0=1;#50;
end
endmodule

53
Output:

Result:
Hence, a SR,JK,D,T Flip Flops are designed and their characteristics are
observed.

54
 EXPERIMENT 12
Counter
Aim:
To Design a Counter in Behavioural Model Design.

Apparatus Required:
➢Vivado Software
➢Windows OS

Procedure:
➢Open Vivado Software and select “Create Project”.
➢Enter the Project name and Project location.
➢Choose the Project Type to “RTL Project” and press Next.
➢In the Add Sources page, create a new Verilog File using the “Create
File” option under the “+” option.
➢In the Default Part page, select “ZedBoard Zynq Evaluation and
Development kit” from the Boards and finish the setup.
➢Enter the Code in the Design Source file and run the “Behavioural
Simulation” from the Simulation Section to observe the output and note
down the values.

Program:
module counter(o,c);
input c;
output reg [3:0]o;
initial

55
begin
o=4'b0000;
end
always @(posedge c)
begin
if(o<=4'b1111)
begin
o = o+1;
end
else
begin
o=4'b0000;
end
end
endmodule

Test Bench
module c_tb();
reg c;
wire [3:0]o;
counter x1(o,c);
initial
begin
c=0;#25;
c=1;#25;
c=0;#25;
c=1;#25;

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c=0;#25;
c=1;#25;
c=0;#25;
c=1;#25;
c=0;#25;
c=1;#25;
c=0;#25;
c=1;#25;
c=0;#25;
c=1;#25;
c=0;#25;
c=1;#25;
c=0;#25;
c=1;#25;
c=0;#25;
c=1;#25;
c=0;#25;
c=1;#25;
c=0;#25;
c=1;#25;
c=0;#25;
c=1;#25;
c=0;#25;
c=1;#25;
c=0;#25;
c=1;#25;
c=0;#25;

57
c=1;#25;
c=0;#25;
c=1;#25;
c=0;#25;
c=1;#25;
end
endmodule

Output:

Result:
Hence, a Counter is designed and its characteristics are observed.

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