SDRAM Memory Systems:

Architecture Overview and Design Verification

Primer
Primer

Contents
Introduction .................................................................... 3 Memory System Design ............................................... 13
DRAM Trends ...................................................................3 Design Simulation ...........................................................13
DRAM . .............................................................................4 Design Verification . .........................................................13
Verification Strategy ........................................................13
SDRAM ........................................................................... 6
SDRAM Verification .........................................................14
DDR SDRAM ....................................................................6
DDR2 SDRAM ..................................................................7 Glossary......................................................................... 16
DDR3 SDRAM ..................................................................8
DDR4 SDRAM ..................................................................9

GDDR and LPDDR ......................................................... 9

DIMMs . ........................................................................... 9
DIMM Physical Size ........................................................10
DIMM Data Width ...........................................................10
DIMM Rank . ...................................................................10
DIMM Memory Size & Speed ..........................................10
DIMM Architecture ..........................................................10
Serial Presence ...............................................................12

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 SDRAM Memory Systems: Architecture Overview and Design Verification

Introduction Memory needs to be compatible with a wide variety

of memory controller hubs used by the computer
DRAM (Dynamic Random Access Memory) is attractive to manufacturers.
designers because it provides a broad range of performance
and is used in a wide variety of memory system designs for Memory needs to work when a mixture of different
computers and embedded systems. This DRAM memory manufacturer’s memories is used in the same memory
primer provides an overview of DRAM concepts, presents system of the computer.
potential future DRAM developments and offers an overview Open memory standards are useful in helping to ensure
for memory design improvement through verification. memory compatibility.

DRAM Trends On the other hand, embedded systems typically use a fixed
memory configuration, meaning the user does not modify
There is a continual demand for computer memories to be the memory system after purchasing the product. The
larger, faster, lower powered and physically smaller. These embedded systems manufacturer then has total control over
needs are the driving force in the advancement of DRAM which memories from specific manufacturers are used in
technology. Mainstream DRAMs have evolved over the years the embedded systems product. It is common to optimize
through several technology enhancements, such as SDRAM an embedded system’s performance and cost by using one
(Synchronous DRAM), DDR (Double Data Rate) SDRAM, specific memory from one memory manufacturer. As a result,
DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, LPDDR (Low it is less important in embedded systems, as compared to
Power DDR), GDDR2 (Graphics DDR2), GDDR3, GDDR4 and computer systems, to have a high level of multivendor memory
GDDR5. This evolution has also been driven by how computer interoperability.
memories are used on DIMMs (Dual Inline Memory Modules).
DIMM implementations have expanded from unregistered The JEDEC (Joint Electron Device Engineering Council) has
DIMMs to include registered DIMMs and FB-DIMMs (Fully helped the memory industry by creating memory specifications
Buffered DIMMs). in the form of JEDEC standards. JEDEC is a non-profit
organization with members from memory manufacturers,
Computer memories are not the only systems that continue to computer manufacturers, test equipment manufacturers,
demand larger, faster, lower powered and physically smaller etc. The open JEDEC standards define the required
memories. Embedded systems applications have similar specifications that are needed for manufacturers to implement
requirements and increasingly use DRAMs. memory products that are to be interoperable with other
However, memory systems are implemented differently in manufacturers’ memories and computer memory controller
computers versus embedded systems. Typically, computer hubs. These standards cover physical characteristics, DIMM
memories are mounted on pluggable DIMMs that are easily circuit board layouts, electrical signals, register definitions,
installed in the computer during assembly. The computer user functional operation, memory protocols, etc. Verifying and
may upgrade the computer memory by adding or replacing testing a memory conformance to the JEDEC specifications
the DIMMs after the computer has been purchased. As a is a critical step to ensuring reliable and interoperable memory
result, memories used in computers require a high level of operation with other manufacturer’s products.
compatibility with current and future computers, as well as
current and future memories used in conjunction with a DIMM.
There are two major areas of compatibility.

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Primer

Columns

1 1 0 0 0 1 0 0 0
1 0 0 1 1 0 0 0 1
Rows are refreshed
1 0 0 0 0 1 1 1 0
Rows are high address bits
Rows (page) 0 0 1 0 1 1 1 1 0
Columns are low address bits
1 0 1 1 1 0 0 0 1
Row is selected first then column
0 1 1 0 1 0 1 0 0
1 0 1 1 1 0 1 1 0

Figure 1. DRAM memory cells organized into a two-dimensional array of rows and columns.

New DRAM designs are meeting computer and embedded is built with one capacitor and one or three FET(s) (field-effect
systems memory requirements to be larger, faster, lower transistor). A typical SRAM (Static Random Access Memory)
powered and physically smaller. As a result, the following memory cell takes six FET devices, resulting in fewer memory
DRAMs changes are occurring: memory size is increasing, cells per same size IC. SRAMs are simpler to use, easier to
the numbers of banks are increasing, the burst length is interface to and have faster data access times than DRAMs.
increasing, the supply voltage is decreasing, the logic voltage
DRAMs core architecture consists of memory cells organized
swings are decreasing, the clock rates are increasing, the
into a two-dimensional array of rows and columns (See
data rates are increasing, memory channels implementations
Figure 1). To access a memory cell requires two steps. First,
are going from a large number of parallel signals to a
you address a specific row and then you address a specific
reduced number of high speed serial signals, the number of
column in the selected row. In other words, first an entire row
memory channels are increasing, the circuit board density is
is read internally in the DRAM IC and then the column address
increasing, etc. These trends are causing designers to use
selects which column of the row is to be read or to be written
new techniques and tools to design, verify and debug their
to the DRAM IC I/O (Input/Output) pins.
memory systems.
DRAM reads are destructive, meaning the data in the row of
As memory clock rates increase and logic voltage swings
memory cells are destroyed in the read operation. Therefore,
decrease, signal integrity has become more of an issue for
the row data need to be written back into the same row after
reliable memory operation. As result, there are trends for new
the completion of a read or write operation on that row. This
DRAM features to focus on improving signal integrity of the
operation is called precharge and is the last operation on
memory system. These features include dynamically controlled
a row. It must be done before accessing a new row and is
ODT (on-die termination), OCD (off-chip driver) calibration and
referred to as closing an open row.
Fully Buffered DIMMs with AMBs (Advanced Memory Buffers).
Analysis of computer memory accesses show that reads of
DRAM sequential memory addresses are the most common types of
An advantage of DRAM over other types of memory is its memory accesses. This is reasonable since reading computer
ability to be implemented with fewer circuits per memory instructions are typically more common than data read or
cell on the IC (integrated circuit). The DRAM’s memory cell is writes. Also, most instruction reads are sequential in memory
based on storing charge on a capacitor. A typical DRAM cell until an instruction branch or a jump to subroutine occurs.

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 SDRAM Memory Systems: Architecture Overview and Design Verification

Distributed
Refresh

Burst
Refresh

Time
Each pulse represents Required time to
a refresh cycle complete refresh
of all rows

Figure 2. DRAM refresh implementations include distributed refresh and burst refresh.

A DRAM row is called a memory page and once the row is on DQ pins is called latency. The last step is RAS#, CAS#
opened you can access multiple sequential or different column and OE# going high (inactive) and waiting for the internal
addresses in that row. This increases memory access speed precharge operation to complete restoration of the row data
and reduces memory latency by not having to resend the after the destructive read. The time from the first step to
row address to the DRAM when accessing memory cells in completion of the last step is the memory cycle time. Signal
the same memory page. As a result, the row address is the timing of the above signals is related to the sequence of
computer’s higher order address bits and the column address edges and is asynchronous. There are no synchronous clock
is the lower order address bits. Since the row and column operations with these early DRAMs.
addresses are sent at different times, the row address and
The DRAM memory cell needs to refresh to avoid losing its
the column address are multiplexed on the same DRAM
data contents. This requires refresh of the capacitor before
pins in order to reduce package pin count, cost and size.
it loses its charge. Refreshing memory is the responsibility
Typically the size of the row address is larger than the column
of the memory controller and the refresh time specification
address because the power usage is related to the number of
varies with different DRAM memories. The memory controller
columns.
performs a refresh by doing a RAS# only cycle with the row
Early DRAMs had control signals such as RAS# (Row Address address. At the end of the RAS# only cycle is the precharge
Select active low) and CAS# (Column Address Select active operation of restoring the row data that was address in the
low) to select the row and column addressing operation being RAS# only cycle. Typically, the memory controller would
performed. Additional DRAM control signals include WE# have a row counter that would sequentially generate all row
(Write Enable active low) for selecting write or read operation, addresses that were needed by the RAS# only refresh cycles.
CS# (Chip Select active low) for selecting the DRAM and
There are two refresh strategies (See Figure 2). The first
OE# (output enable active low). The early DRAMs had control
strategy is for the memory controller to refresh all rows
signals that were asynchronous and had various timing
sequentially in a burst of refresh cycles and then return control
specifications covering their sequence and time relationships
of memory back to the processor for normal operation. The
to determine the DRAM operating mode.
next burst of refresh operations occurs before reaching the
The early DRAMs read cycle had four steps. First, RAS# goes maximum refresh time. The second refresh strategy is for the
low with a row address on the address bus. Secondly, CAS# memory controller to interleave the refresh cycles with normal
goes low with a column address on the address bus. Third, processor memory operations. This refresh method spreads
OE# goes low and read data appears on DQ data pins. The out the refresh cycles over the maximum refresh time.
time from the first step to the third step when data is available

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Primer

Early DRAMs evolved and implemented the refresh counter DDR SDRAM Data Rate Memory Clock
on the DRAM IC to take care of sequentially generated row
DDR-266 266 Mb/s/pin 133 MHz
addresses. Internally to the DRAM IC, the refresh counter is
an input to a multiplexer that controls the memory array row DDR-333 333 Mb/s/pin 166 MHz
address. The other multiplexer input is from the row address DDR-400 400 Mb/s/pin 200 MHz
from the external address input pins. This internal refresh Table 1. DDR SDRAM data rates and clock speeds.
counter eliminated the need for an external refresh counter
circuit in the memory controller. Some of these DRAMs
supported a CAS# before RAS# cycle to initiate a refresh DDR SDRAM
cycle using the internally generated row address. DDR (Double Data Rate) SDRAMs increased the memory data
rate performance by increasing clock rates, bursting of data
SDRAM and transferring two data bits per clock cycle (See Table 1).
The DRAM’s asynchronous operation caused many design DDR SDRAMs burst multiple memory locations in a single
challenges when interfacing it to a synchronous processor. read or single write command. A read memory operation
entails sending an Activate command followed by a Read
SDRAM (Synchronous DRAM) was designed to command. The memory responds after its latency with a burst
synchronize the DRAM operation to the rest of of two, four, or eight memory locations at a data rate of two
memory locations per clock cycle. Therefore, four memory
the computer system and to eliminate defining all
locations are read from or written to in two consecutive clock
the different modes of memory operations based cycles.
on the sequence of CE# (Chip Enable active low),
DDR SDRAMs have multiple banks to provide multiple
RAS#, CAS# and WE# edge transitions. interleaved memory access, which increases memory
SDRAM added a clock signal and the concept of memory bandwidth. A bank is one array of memory, two banks are two
commands. The type of memory command is determined by arrays of memory, four banks are four arrays of memory, etc
the state of CE#, RAS#, CAS# and WE# signals at the rising (See Figure 3). Four banks require two bits for bank address
edge of the SDRAM clock. Data sheets describe the memory (BA0 & BA1).
commands in table form based on the state of CE#, RAS#, For example, a DDR SDRAM with four banks operates in the
CAS# and WE# signals. following manner. First, an Activate command opens a row
For example, an Activate command sends a row address in the first bank. A second Activate command opens a row
to the SDRAM to open a row (page) of memory. Next in the second bank. Now any combinations of Read or Write
is a sequence of Deselect commands to satisfy timing commands can be sent to either the first bank or the second
requirements before sending the Read or Write command bank with their open rows. When Read and Write operations
with the column address. Once the row (page) of memory is on the bank are completed, a Precharge command closes the
opened with an Activate command, several Read and Write row and the bank is ready for an Activate command to open a
commands can operate on the data in that row (page) of new row.
memory. A Precharge command is required to close the row
before another row can open.

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 SDRAM Memory Systems: Architecture Overview and Design Verification

DDR2 SDRAM Data Rate Memory Clock

DDR SDRAM IC DDR2-400 400 Mb/s/pin 200 MHz

Bank 0 Bank 2
DDR2-533 533 Mb/s/pin 266 MHz
Columns Columns DDR2-667 667 Mb/s/pin 333 MHz
1
1
1
0
0
0
0
1
0
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
0
1
1
0
0
0
0
0
0
1
DDR2-800 800 Mb/s/pin 400 MHz
Rows
1 0 0 0 0 1 1 1 0
Rows
1 0 0 0 0 1 1 1 0
DDR2-1066 1066 Mb/s/pin 533 MHz
0 0 1 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0
(page) (page)
1 0 1 1 1 0 0 0 1 1 0 1 1 1 0 0 0 1 Table 2. DDR2 SDRAM data rates and clock speeds.
0 1 1 0 1 0 1 0 0 0 1 1 0 1 0 1 0 0
1 0 1 1 1 0 1 1 0 1 0 1 1 1 0 1 1 0

DDR2 SDRAM
Bank 1 Bank 3
DDR2 SDRAM has several improvements over DDR SDRAM.
Columns Columns
1 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0
DDR2 SDRAM clock rates are higher, thus increasing the
1 0 0 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 memory data rates (See Table 2). Signal integrity becomes
1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 1 1 0
Rows 0 0 1 0 1 1 1 1 0
Rows 0 0 1 0 1 1 1 1 0
more important for reliable memory operation as the clock
(page) (page)
1 0 1 1 1 0 0 0 1 1 0 1 1 1 0 0 0 1 rates increase. As clock rates increase, signal traces on the
0 1 1 0 1 0 1 0 0 0 1 1 0 1 0 1 0 0
1 0 1 1 1 0 1 1 0 1 0 1 1 1 0 1 1 0 circuit boards become transmission lines and proper layout
and termination at the end of the signal traces becomes more
important.
Figure 3. Multiple memory banks in a DDR SDRAM provide increased access flexibility
and improved performance. Termination of the address, clock and command signals
are somewhat straightforward because these signals are
unidirectional and are terminated on the circuit boards. The
Note that the power required by the DDR SDRAM is related data signals and data strobes are bidirectional. The memory
to the number of banks with open rows. More open rows controller hub drives them during a write operation and the
require more power and larger row sizes require more power. DDR2 SDRAM drives them during a read operation. To add
Therefore, for low power applications one should open only to the complexity, multiple DDR2 SDRAMs are connected to
one row at a time in each bank and not have multiple banks the same data signals and data strobes. These multiple DDR2
each with open rows. SDRAMs can be on the same DIMM and on different DIMMs
Interleaving consecutive memory words in consecutive in the memory system. As a result, the data and data strobe
memory banks is supported when the bank address bits are drivers and receivers are constantly changing depending upon
connected to the lower order address bits in the memory the read/write operation and which DDR2 SDRAM is being
system. Consecutive memory words are in the same memory accessed.
bank when the bank address bits are connected to the higher DDR2 SDRAM improves the signal integrity of data signals
order address bits in the memory system. and data strobes by providing ODT (On-Die Termination), an
ODT signal to enable the on-die termination and the ability to
program the on-die termination values (75 ohms,150 ohms,
etc.) with the DDR2 SDRAM extended mode register.

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Primer

The on-die termination value and operation is controlled by DDR3 SDRAM Data Rate Memory Clock
the memory controller hub and are a function of a DDR2
DDR3-800 800 Mb/s/pin 400 MHz
SDRAM DIMM’s location and type of memory operation (reads
or writes). ODT operation results in better signal integrity by DDR3-1066 1066Mb/s/pin 533 MHz
creating a larger eye diagram for the data valid window with DDR3-1333 1333Mb/s/pin 667 MHz
increased voltage margins, increased slew rates, reduced DDR3-1600 1600 Mb/s/pin 800 MHz
overshoot and reduced ISI (Inter-Symbol Interference). DDR3-1866 1866Mb/s/pin 933 MHz
DDR2 SDRAM reduces memory system power by operating DDR3-2133 2133Mb/s/pin 1066 MHz
at 1.8 volts, which is 72% of DDR SDRAM’s 2.5 volts. In some Table 3. DDR3 SDRAM data rates and clock speeds.
implementations, the number of columns in a row has been
reduced, resulting in lower power when a row is activated for
read or writes. DDR3-1066 SDRAM uses less power than DDR2-800
SDRAM because the DDR3 SDRAM operating voltage is
Another benefit of the lower operating voltages is the lower 1.5 volts, which is 83% of DDR2 SDRAM’s 1.8 volts. Also,
logic voltage swings. For the same slew rate, the reduced the DDR3 SDRAM data DQ drivers are at higher 34 ohms
voltage swings increase logic transition speeds to support impedance than DDR2 SDRAM’s lower 18 ohms impedance.
faster clock rates. In addition, the data strobe can be
programmed to be a differential signal. Using differential DDR3 SDRAM will start with 512 Mb of memory and will grow
data strobe signals reduces noise, crosstalk, dynamic power to 8 Gb memory in the future. Just like DDR2 SDRAM, DDR3
consumption and EMI (Electromagnet Interference) and SDRAM data output configurations include x4, x8 and x16.
increases noise margin. Differential or single-end data strobe DDR3 SDRAM has eight banks where as DDR2 SDRAM has
operation is configured with the DDR2 SDRAM extended four or eight depending upon the memory size.
mode register. Both DDR2 and DDR3 SDRAMs have four mode registers.
A new feature introduced with DDR2 SDRAM is additive DDR2 defined the first two mode registers while the other
latency, which provides the memory controller hub the two were reserved for future use. DDR3 uses all four mode
flexibility to send the Read and Write commands sooner after registers. One significant difference is DDR2 mode registers
the Activate command. This optimizes memory throughput defined CAS latency for read operation and the write latency
and is configured by programming the additional latency using was one less the mode register read latency setting. DDR3
the DDR2 SDRAM extended mode register. mode registers have unique settings for both the CAS read
latency and write latency.
DDR2 SDRAM improves data bandwidth of 1Gb and 2Gb
DDR2 SDRAMs by using eight banks. The eight banks DDR3 SDRAM uses 8n prefetch architecture which transfers 8
increase the flexibility of accessing large memory DDR2 data words in 4 clock cycles. DDR2 SDRAM uses 4n prefetch
SDRAMs by interleaving different memory bank operations. architecture which transfers 4 data words in 2 clock cycles.
Also, for large memories, DDR2 SDRAM supports a burst The DDR3 SDRAM mode registers are programmed to
length up to eight. support the on the fly burst chop, which shortens the transfer
DDR2 SDRAM data sheets are over 100 pages and the above of 8 data words to 4 data words by setting the address line
DDR2 SDRAM features are highlights of its key features. Refer 12 low during a read or write command. On the fly burst chop
to DDR2 SDRAM data sheets for their complete features and is similar in concept to the read and write auto-precharge
details of operation. function of the address line 10 in both DDR2 and DDR3
SDRAMs.
DDR3 SDRAM Other noteworthy DDR3 SDRAM attributes include the data
DDR3 SDRAM is a performance evolution and enhancement strobes DQS which are differential, whereas DDR2 SDRAM
of SDRAM technology starting at 800 Mb/s, which is the data strobes could be programmed by the mode register to
highest data rate supported by most DDR2 SDRAMs. DDR3 be single-ended or differential. DDR3 SDRAM also has a new
SDRAMs support six levels of data rates and clock speeds pin which is the active low asynchronous RESET# pin, which
(See Table 3). DDR3-800/1066/1333 SDRAMs became will improve system stability by putting the SDRAM in a known
available in 2007, while DDR3-1600/1866 SDRAMs are state regardless of the current state. DDR3 SDRAM uses the
expected in 2008 and DDR3-2133 SDRAMs in 2009. same type of FBGA packages as DDR2 SDRAM.

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 SDRAM Memory Systems: Architecture Overview and Design Verification

DDR3 DIMMs have the terminations for the commands, SDRAM Data Rate Memory Clock
clock and address on the DIMM. Memory systems using
DDR4-1600 1600 Mb/s/pin 800 MHz
DDR2 DIMM terminate the commands, clock and address
on the motherboard. The DDR3 DIMM terminations on the DDR4-1866 1866 Mb/s/pin 933 MHZ
DIMM allow a fly-by topology where each command, clock DDR4-2133 2133 Mb/s/pin 1066 MHz
and address pin on the SDRAM is connected to a single DDR4-2400 2400 Mb/s/pin 1200 MHz
trace which is terminated at the trace end on the DIMM. This DDR4-2667 2667 Mb/s/pin 1333 MHz
improves the signal integrity and results in faster operation
DDR4-3200 3200 Mb/s/pin 1600 MHz
than the DDR2 DIMM tree structure.
Table 4. DDR4 SDRAM data rates and clock speeds.
The fly-by topology introduces a new write leveling feature of
DDR3 SDRAM for the memory controller to account for the
timing skew between the clock CK and data strobes DQS GDDR and LPDDR
during writes. The DDR3 DIMM is keyed differently than the
Other DDR variations such as GDDR (Graphics DDR) and
DDR2 DIMM to prevent the wrong DIMM being plugged into
LPDDR (Low Power DDR) are increasingly gaining importance
the motherboard.
in the industry as well.
DDR4 SDRAM GDDR is a graphics card-specific memory technology and
In September of 2012 JEDEC released preliminary standards is currently specified with four variants: GDDR2, GDDR3,
for DDR4. DDR4 has significant increases in performance GDDR4 and GDDR5. GDDR has a very similar technological
as well as improved reliability and reduced power compared base as conventional DDR SDRAM's but differs in the power
to the last generation of DRAM technology. DDR4 will have requirements. They have been reduced to allow for simplified
double the speed and memory density, and will use 20% less cooling and higher performance memory modules. GDDR is
power representing significant achievement relative to past also designed to better handle certain graphic requirements.
DRAM technologies. DDR4 is able to achieve lower power LPDDR uses 166 MHz clock speeds and is gaining
consumption by dropping voltages from 1.5V as in DDR3 to popularity in portable consumer electronics where low power
1.2V while increasing the performance factor to 2,133 MT/sec consumption is important. LPDDR2 improves power efficiency
to start with future goals of 3,200 MT/sec. even further with operating voltages as low as 1.2V and clock
One of the most significant changes is the proposed speeds ranging from 100 to 533 MHz. LPDDR3 continues to
requirement to establish the reference voltage or V center improve upon power efficacy while increasing clock speeds
used for compliance testing using a variable approach. For to 800MHz. The standards for LPDDR4 were published in
DDR3, this value was fixed at 750 mV. The new approach August of 2014 and represent the latest generation of LPDDR
involves making multiple acquisitions of the DQ and a DQS technology. LPDDR4 further improves upon the power
Write burst. The largest to smallest voltage value for each efficiency of the previous generation by about 40% at 1.1V
is then measured and an average created using a simple while doubling the clock rate of the previous generation to
formula. This then becomes the DQ voltage reference for 1.6GHz.
centering and making reference measurements using an eye
diagram. DIMMs
Following the lead of many serial standards, DDR4 will now Dual inline memory modules (DIMMs) are plug-in memory
incorporate a statistical jitter measurement approach for modules for computers.
speeds greater than 2,133. For speeds under 2,133, all jitter
will be assumed to be deterministic jitter or DJ. For 2,133 and
DIMMs vary in physical size, memory data width,
above, tests will look at both DJ and random jitter or RJ. To ranks, memory sizes, memory speeds and
date, many of the timing parameters for jitter have not been memory architectures.
published, but designers should be aware that jitter testing
JEDEC has defined DIMMs standards and continues to work
will be a requirement. One benefit of expanded jitter testing in
on defining new DIMMs based on new memory types and
DDR4 is that should devices fail to meet jitter requirements,
memory architectures.
the test and measurement vendor community offers robust
jitter decomposition tools that can help isolate the source of
problems.

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Primer

DIMM 4 I/Os per IC 8 I/Os per IC 16 I/Os per IC

UDIMM UDIMM UDIMM UDIMM
1 Rank 16 ICs 8 ICs 4 ICs
DRAM DRAM DRAM DRAM
2 Ranks 32 ICs 16 ICs 8 ICs
DRAM DRAM DRAM DRAM
4 Ranks 64 ICs 32 ICs 16 ICs
Table 5. Number of memory ICs per DIMM without ECC based on ranks on the DIMM DRAM DRAM DRAM DRAM
and number of data I/Os per memory IC. Memory
Controller DRAM DRAM DRAM DRAM
Hub
DRAM DRAM DRAM DRAM

Page Size I/Os Pins Banks DRAM DRAM DRAM DRAM

32 Meg bit 4 4 DRAM DRAM DRAM DRAM

16 Meg bit 8 4 DRAM DRAM DRAM DRAM

8 Meg bit 16 4
Table 6. Examples of different 512Mb (Meg bit) memory IC configurations. Figure 4. UDIMM has no buffering of the DRAM signals on the DIMM.

DIMM Physical Size DIMM Memory Size & Speed

The standard DIMM size is used in desktops, workstations DIMM memory size depends on size of memory ICs used
and servers. SO-DIMMs (Small Outline DIMMs) are small and DIMM configuration. A 512Mb (Meg bit) memory IC can
size DIMMs used in laptops and other space constant be designed as different configurations (See Table 6). DIMM
implementations. The Butterfly configuration refers to two speed depends on the clock speed supported by the DDR,
SO-DIMMs parallel to the computer motherboard that have DDR2, DDR3, and DDR4 SDRAMs used on the DIMM.
their edge connectors next to each other. Think of the two
edge connectors as the butterfly body and the SO-DIMMs DIMM Architecture
as the open butterfly wings. Mini-DIMMs (Miniature DIMMs) There are three major DIMM architectures: UDIMMs, RDIMMs
are smaller than SO-DIMMs and are used in single board and FB-DIMMs. Each DIMM architecture has advantages and
computers. VLP-DIMMs (Very Low Profile DIMMs) are shorter limitations.
in height and are used in blade servers.
UDIMM is an unregistered DIMM. UDIMM has no buffering of
DIMM Data Width the DDR, DDR2, DDR3, and DDR4 SDRAMs signals on the
DIMM (See Figure 4). UDIMMs were the first implementation
DIMM data width depends upon support for the ECC (Error
of DIMMs. For a single or dual DIMM memory system the
Correction Code). ECC is eight check bits used for error
UDIMMs are the fastest and lowest cost. The memory
detection and correction. The standard DIMM data width is 64
controller hub directly controls all the DRAM signals. No
bits without ECC and 72 bits with the eight ECC bits.
buffers or registers delay the signals between the memory
DIMM Rank controller hub and the SDRAM on the UDIMM. The number
of UDIMMs that can be on a memory controller hub memory
A rank is a complete group of memory devices on a DIMM to channel is limited by signal integrity. Signal integrity is
support 64 data bits or 72 bits with ECC. A rank of two is two decreased by the following factors: increased memory clock
groups of memory devices on a DIMM. Rank of four is four speed, increased trace lengths, increased number of UDIMMs
groups of memory devices on a DIMM. Table 5 shows how on a memory channel, and increased number of ranks on a
many memory ICs are on a DIMM that supports a data width UDIMM. The memory controller hub sees every connector,
of 64 bits without ECC. At some point there is not enough every trace, every trace branch and every SDRAM pin. The
room on both sides of the DIMM for all the memory ICs. To impedance problems of the tree stub architecture limit the
solve this problem, memory ICs are stacked on top of each clock frequency and the number of UDIMMs that a memory
other. channel can reliably operate.

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 SDRAM Memory Systems: Architecture Overview and Design Verification

RDIMM RDIMM RDIMM RDIMM FB-DIMM FB-DIMM FB-DIMM FB-DIMM

DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM

DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM

DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM

DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM

Memory Memory
Controller Commands Commands Commands Commands Controller Advanced Advanced Advanced Advanced
Hub & Address & Address & Address & Address Hub Memory Memory Memory Memory
Registers Registers Registers Registers Buffer Buffer Buffer Buffer

DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM

Point-to-point
DRAM DRAM DRAM DRAM channel DRAM DRAM DRAM DRAM
architecture
DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM

DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM

Figure 5. RDIMM buffers DRAM clock, command signals and address signals on the Figure 6. FB-DIMM buffers DDR2 SDRAM signals on the FB-DIMM.
DIMM.

Memory controller hubs that have separate memory channels RDIMM PLL. This reduced tree stub architecture allows for
are one way to increase the number of UDIMMs in a memory more RDIMMs to be used on a memory channel, making it
system. Two separate memory channels can support two high faster. There is no buffering or reduced signal loading benefits
speed UDIMMs with one UDIMM per memory channel. for the bidirectional DQ data lines and DQS data strobe lines.
Also, RDIMMs memory access times are one clock cycle
RDIMM is a registered DIMM. RDIMM reduces some of the
slower than UDIMM because one clock cycle is required to
problems of the tree stub architecture by buffering the RDIMM
latch the commands and address signals into the registers on
SDRAMs clock, command signals and address signals on
a RDIMM.
the RDIMM (See Figure 5). The clock signal is buffered with
the Phase Lock Loop (PLL) and the command signals and FB-DIMM is a fully buffered DIMM. FB-DIMM uses DDR2
addressing signals are buffered with register latches. A typical SDRAMs and FB-DIMM2 uses DDR3 SDRAMs. All DDR2
registered DIMM is implemented with a PLL IC and two ICs SDRAMs and DDR3 SDRAMs signals are buffered from the
with registers. The memory controller hub clock, command memory system with the AMB (Advanced Memory Buffer) IC
signals and address signals see the impedances of the on the FB-DIMM and FB-DIMM2 (See Figure 6).
motherboard traces, DIMM connectors, RDIMM registers and

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Primer

Byte Number Function Described SPD HEX Value

0 Defines number of bytes written into serial memory at module manufacturer 80
1 Total number of SPD memory bytes 08
2 Fundamental memory type (FPM or EDO) 01 or 02
3 Number of row addresses on the memory device 0C
4 Number of column addresses on memory device 0A
5 Number of physical banks on this memory module 01
6 Data width of this module 40
7 Data width (continued) 00
8 Module voltage interface levels 01
9 RAS access time of this assembly 3C
10 CAS access time of this assembly 0F
11 Module error correction configuration type (non-parity, parity, ECC) 00 or 01 or 02
12 Refresh rate/type 00 or 83
13 Primary DRAM width 10
14 Error checking DRAM data width 00
15 - 61 Reserved 00
62 SPD revision 00
63 Checksum for bytes 0-62 Calculated
64 Manufacturer JEDEC ID code 2C
65 - 71 Manufacturer JEDEC ID code (continued) 00
72 Manufacturing location 01 - 08
73 - 90 Manufacturer’s part number Variable
91 PCB identification code 01 - 09
92 PCB identification code (continued) 00
93 Year of manufacture Variable
94 Week of manufacture Variable
95 - 98 Module serial number Variable
99 - 125 Manufacturer-specific data Variable
126 - 127 Reserved 00
128 - 255 Open user free-form are not defined FF
Table 7. The computer BIOS reads the DIMM configuration using the Serial Presence Detect (SPD) interface. The SPD data is specified by JEDEC standards.

Serial Presence functions are specified by JEDEC standards. For UDIMMs

and RDIMMs the SPD functions are implemented in a small
Detect The Serial Presence Detect (SPD) function is on all
nonvolatile memory IC with a slow speed I2C interface that is
computer DIMMs and is used to provide DIMM memory
located on each DIMM. The motherboard has an I2C interface
configuration information such as memory size, speed,
with a unique address (0 through 7) for each DIMM slot. At
latency, timing, manufacturer, etc. to the computer’s BIOS
power-on, each DIMM slot is checked using the I2C interface.
during the computer’s power-on (See Table 7). At power-
If a DIMM is present the SPD values are read by the BIOS.
on, the BIOS (Basic Input Output Software) reads the
configuration information of each DIMM using the SPD For FB-DIMMs the SPD functions are implemented in the
function. This information is then used to configure the AMB, which has the I2C interface. The FB-DIMM I2C interface
memory controller hub and the DRAM mode and extended is called SMbus (System Management bus). The SMbus is
mode registers on each UDIMM and RDIMM. The SPD used to configure the AMB in each FB-DIMM.

12 [Link]/memory
 SDRAM Memory Systems: Architecture Overview and Design Verification

Memory System Design Design Verification

The first few steps of product design are product Using new DRAM features in designs requires new design
requirements, product architecture design and subsystem methods and techniques, which range from new techniques in
design. One of the subsystem designs is the memory system. design simulation to new BIOS operation. As a result, DRAM
design implementations require complete verification and
Memory system design is dependent on memory testing, ranging from circuit board construction to software
size, speed, power, existing standards, new operation to ensure reliable memory operation. Product
developing standards, reuse of existing designs reliability will suffer if a memory system has infrequent random
errors because of a design implementation that has not been
and other requirements.
fully verified. In addition, the customer may require a product
The computer chipset manufacturers heavily influence to satisfy various compliance testing requirements that have
memory system designs for computers. Some of these been defined by JEDEC or by other manufacturers.
computer chipset manufacturers have their own testing
procedures, validation processes and workshops to test
Verification Strategy
products. Typically, these computer chipset manufacturers’ It is important to have a strategy for effectively and quickly
web sites list memory products that passed their compatibility debugging design problems in any design implementation.
testing. Quick time-to-market product development requires
verification/debugging planning early in the design. This plan
Design Simulation should identify the following requirements:
A key part of memory system design is design simulation. What are new design elements and what are reused design
The importance of comprehensive memory system design elements.
simulation cannot be understated. Experience has shown
that a resistor value change of only a few ohms can have What to avoid and change based on past designs.
a significant impact on having a reliable operating memory What level of validation and testing is needed, does the
system. testing require special operating modes or signal patterns.
Memory system design simulation should include the effects What special design-in features are needed (e.g., probing
of probing loading caused by measurement any instrument test points or test fixtures), has simulation analysis
when it is connected to the prototype memory system. The accounted for probing the prototype, are signal stimuli
verification and debugging process will be very difficult if the needed, is special software needed to exercise the
prototype stops operating because of probe loading. Also, hardware.
simulation should analyze the signals at probe test points with
What environmental tests are needed (e.g., temperature,
an accounting of the signal impacts caused by the loading of
humidity, etc.).
the instrument probe. The data valid window will change along
the signal trace from the memory controller hub driver to the What circuit operational visibility do you have in order to
SDRAM pins. debug it.

Probing test points should be as close as possible to the What regulatory compliance testing is required, will the
receiver pins so that the instrument shows the signal that the validation/debug test points be used to test the product in
receiver is seeing. Sometimes this is not possible and BGA manufacturing, will the validation/debug test points be used
(Ball Grid Array) interposers, test adapter boards and other to repair the product in service, and how do you manage
special probing fixtures and aids are used to retrieve difficult to the risk of what you do not know today.
access signals. The signal loss impact of these probing aids
should also be included in design simulations to understand
their effect on the SDRAM signals and the measurement of
the signals.

[Link]/memory 13
Primer

Verification Tasks Instruments

Circuit Board Construction Single-ended trace impedances Sampling Oscilloscope with TDR
Differential trace impedances Sampling Oscilloscope with TDR
Trace lengths Sampling Oscilloscope with TDR
Crosstalk Sampling Oscilloscope with TDT
Electrical Power & Signals Power supply quality, noise, glitches & ground bounce Oscilloscope or Mixed Signal Oscilloscope (MSO)
Clock signal quality, rise & fall times/slew rates, spread Oscilloscope or Mixed Signal Oscilloscope (MSO) with
spectrum clocking profile jitter analysis software
Command, address & data valid windows, clock, strobes Oscilloscope or Mixed Signal Oscilloscope (MSO) with
& data signal skew jitter analysis software
FB-DIMM serial signals data valid windows Oscilloscope with serial data compliance and analysis
software, Signal Sources & FB-DIMM fixtures
Protocols Sequences & Timing Memory system power up initialization protocols & Logic analyzer with SDRAM support packages
timing
SDRAM mode register operation Logic analyzer with SDRAM support packages
SDRAM command protocols & timing Logic analyzer with SDRAM support packages
Read/Write data valid windows Logic analyzer with SDRAM support packages
Refresh operations Logic analyzer with SDRAM support packages
Memory channel traffic Logic analyzer with FB-DIMM support packages
Table 8. Verification tasks with associated test equipment.

For example, some verification strategies include building a test equipment. For example, a memory IC designer will not
validation prototype with numerous probing test points to be verifying circuit board construction whereas the DIMM
verify the new system architecture with new ASICs/FPGAs. designer will be verifying the DIMM circuit board construction.
It is best that the validation prototype operates at full speed
The memory controller is typically designed by the embedded
to verify at-speed operation and performance. Complex
systems designer because of its unique requirements to work
designs require more comprehensive visibility of their real-time
with a specific processor and unique embedded system
operation in order to pin-point problems quickly. Once the
input/output configuration. As a result, a significant part of the
validation prototype is running correctly and has completed
design work is designing the memory controller and designing
validation, the final prototype is implemented with reduced test
the circuit board layout between the memory controller and
points.
the memory ICs. Verifying this part of the design is critical for
SDRAM Verification reliable operation.

DRAM verification and testing techniques depend upon DRAM verification and testing techniques require a range
what is being designed. DRAM designs are grouped into of test and measurement equipment such as sampling
the following types: computer memory controller hub ICs, oscilloscopes, mixed signal oscilloscopes, logic analyzers,
memory ICs, AMB ICs, DIMMs, computer motherboards and probes, test fixtures, analysis software, compliance software,
embedded systems. Each of these products requires different etc. (See Table 8). Test equipment needs to provide precise
validation strategies, different validation tests and different acquisition, complete system visibility of electrical signals and
protocol layers and powerful analysis capabilities.

14 [Link]/memory
 SDRAM Memory Systems: Architecture Overview and Design Verification

Unobtrusive probing has been proven as one of the greater on logic analyzer display provides critical design insight to
challenges for memory designers. Increasing speeds, low real-time system operation. In addition, using integrated
power levels, decreasing geometries and a large number of oscilloscope and logic analyzer probing, triggering and display
pins require sophisticated probing solutions. Tektronix offers provides complete design visibility from the software listing,
a complete range of solutions for the most sophisticated the protocol listing, the digital waveforms and the analog
probing challenges. These include direct probing with waveforms on the same display. The result is a powerful,
minimum loading and a variety of probe tips that allow easy comprehensive and efficient analysis of the prototype.
access to the test points; chip interposers or BGA (Ball Grid
Tektronix offers a comprehensive tool set including industry
Array) Interposers that install between the memory IC and
leading oscilloscopes, mixed signal oscilloscopes, true
the circuit board. Instrumented DIMMS that are extended
differential TDRs, BGA Interposers for memory socket
DIMMs designed per the JEDEC specification with additional
probing, and logic analyzers with Nexus Technology memory
connectors to the instrumentation; and DIMM Interposers that
supports to enable embedded and computer designers to
install between the memory DIMM and the circuit board.
perform quick and accurate electrical testing and operational
Monitoring a computer system or embedded system with a validation of their memory designs. Collectively, this tool set
logic analyzer creates a powerful verification and debugging provides superior performance with unparalleled ease-of-
development environment. The logic analyzer is used to trace use, making it an ideal solution for embedded systems and
and correlate the processor bus activity, the memory activity computer memory systems verification and debugging.
and the input/output operations. Complete system visibility

[Link]/memory 15
Primer

Glossary Cyclic Redundancy Code (CRC): A number derived from,

and stored or transmitted with, a block of data in order to
For easy reference, the glossary also includes common terms detect corruption. By recalculating the CRC and comparing
not used in this document. it to the value originally transmitted, the receiver can detect
some types of transmission errors.
A
Advanced Memory Buffer (AMB): Provides intelligent D
Southbound and Northbound channel initialization to align the Decibel (dB): Unit used to express the relative difference in
high-speed serial clocks, locate frame boundaries and verify power between two electric signals, equal to ten times the
channel connectivity. common logarithm of the ratio of the two levels.
Amplitude: The magnitude of a quantity or strength of a Device Under Test (DUT): The device being tested by the
signal. In electronics, amplitude usually refers to either voltage measurement instrument.
or power.
Digital Oscilloscope: A type of oscilloscope that uses an
Analog Signal: A signal with continuously variable voltages. analog–to–digital converter (ADC) to convert the measured
Analog-to-Digital Converter (ADC): A digital electronic voltage into digital information. Three types: digital storage,
component that converts an electrical signal into discrete digital phosphor, and digital sampling oscilloscopes.
binary values. Digital Phosphor Oscilloscope (DPO): A type of digital
Asynchronous: Not synchronized. The logic analyzer runs its oscilloscope that closely models the display characteristics
own sampling clock. The clock is independent and unaware of an analog oscilloscope while providing traditional digital
of the timing on the device under test. This is the basis of the oscilloscope benefits (waveform storage, automated
“timing” acquisition mode. measurements, etc.) The DPO uses a parallel-processing
architecture to pass the signal to the raster-type display, which
Attenuation: A decrease in signal amplitude during its
provides intensity-graded viewing of signal characteristics
transmission from one point to another.
in real time. The DPO displays signals in three dimensions:
B amplitude, time and the distribution of amplitude over time.

Ball Grid Array (BGA): An integrated circuit package. Digital Sampling Oscilloscope: A type of digital oscilloscope
that employs equivalent-time sampling method to capture
Bandwidth: A frequency range, usually limited by –3 dB.
and display samples of a signal, ideal for accurately capturing
Bit: a binary character whose state may be either 1 or 0. signals whose frequency components are much higher than
the oscilloscope’s sample rate.
Byte: a unit of digital information usually consisting of eight
bits. Digital Signal: A signal whose voltage samples are
represented by discrete binary numbers.
C
Digital Storage Oscilloscope (DSO): A digital oscilloscope
Chip Enable (CE#): Activates the device. that acquires signals via digital sampling (using an analog-to-
Chip Select (CS#): Selects the device. digital converter). It uses a serial-processing architecture to
control acquisition, user interface, and the raster display.
Clock Rate: Fundamental rate in cycles per second at which
a device performs its most basic operation. Digitize: The process by which an analog-to-digital converter
(ADC) in the horizontal system samples a signal at discrete
Column Address Select (CAS#): Selects the address column
points in time and converts the signal’s voltage at these points
of interest within the device.
into digital values called sample points.
Cursor: An on-screen marker that you can align with a
waveform to make more accurate measurements.

16 [Link]/memory
 SDRAM Memory Systems: Architecture Overview and Design Verification

Double Data Rate (DDR): The peak data rate is twice the Input/Output (I/O): Typically referring to signals going into or
rate at which commands can be clocked into the device. out of a device.
Dual Inline Memory Module (DIMM): The prevalent Integrated Circuit (IC): A set of components and their
packaging scheme for dynamic random access memory interconnections etched or imprinted on a chip.
components in PC platforms.
Interleave: To intersperse or place at regular intervals.
Dynamic Random Access Memory (DRAM): A type of
iVerify™ Analysis: offers multi-channel bus analysis and
memory that stores each bit of data in a separate capacitor.
validation testing using oscilloscope-generated eye diagrams.
E iView™ Display: delivers time-correlated, integrated logic
Error Correction Code (ECC): Eight check bits used for error analyzer and oscilloscope measurements on the logic analyzer
detection and correction. display.

F J
Field Effect Transistor (FET): A transistor in which the output Joint Electron Device Engineering Council (JEDEC):
current is controlled by a variable electric field. The semiconductor engineering standardization body of the
Electronic Industries Alliance (EIA), a trade association that
Fine-pitch Ball Grid Array (FBGA): An integrated circuit represents all areas of the electronics industry. [Link]
package.
Frequency: The number of times a signal repeats in one
K
second, measured in Hertz (cycles per second). The Kilohertz (kHz): 1 thousand Hertz.
frequency equals 1/period.
L
Fully Buffered Dual Inline Memory Module (FB-DIMM): A
next generation memory architecture. Latency: The time that elapses between a stimulus and the
response. For example, the time from the first step to the third
G step of the read cycle when data is available on DQ pins.
GDDR: Graphics Double Data Rate Loading: The unintentional interaction of the probe and
oscilloscope with the circuit being tested which distorts a
Gigabit (Gb): 1 billion bits of information.
signal.
Gigabyte (GB): 1 billion bytes of information.
Logic Analyzer: An instrument used to make the logic
Gigahertz (GHz): 1 billion Hertz. states of many digital signals visible over time. It analyzes the
Gigatransfers per Second (GT/s): One billion data transfers digital data and can represent the data as real-time software
per second. execution, data flow values, state sequences, etc.

Glitch: An intermittent, high-speed error in a circuit. LPDDR: Low Power Double Data Rate

H M
Hertz (Hz): One cycle per second. The unit of frequency. MagniVu™ Acquisition: a unique high-resolution sampling
architecture at the heart of every TLA Series logic analyzer.
I MagniVu acquisition provides a dynamic record of signal
iCapture™ Multiplexing: provides simultaneous digital and activity surrounding the trigger point with higher resolution.
analog acquisition through a single logic analyzer probe. Megabit (Mb): One million bits of information.
iLink Toolset: consists of several elements designed to
™
Megabyte (MB): One million bytes of information.
speed problem detection and troubleshooting, including:
iCapture™ Multiplexing, iView™ Display, and iVerify™ Analysis.

[Link]/memory 17
Primer

Megahertz (MHz): One million Hertz. Pre-trigger Viewing: The ability of a digital instrument to
capture what a signal did before a trigger event. Determines
Megasamples per second (MS/s): A sample rate unit equal
the length of viewable signal both preceding and following a
to one million samples per second.
trigger point.
Megatransfers per second (MT/s): One million data transfers
Precharge: The phase in the access cycle of DRAM during
per second.
which the storage capacitors are charged to the appropriate
Memory Cycle Time: The time from the first step to value.
completion of the last step in a read cycle.
Probe: A measurement instrument input device, usually
Microsecond (μs): A unit of time equivalent to 0.000001 having a pointed metal tip for making electrical contact with
seconds. a circuit element, a lead to connect to the circuit’s ground
Millisecond (ms): A unit of time equivalent to 0.001 seconds. reference, and a flexible cable for transmitting the signal and
ground to the instrument.
Miniature Dual Inline Memory Module (Mini-DIMM):
Smaller than SO-DIMMs and typically used in single board Pulse: A common waveform shape that has a fast rising
computers. edge, a width, and a fast falling edge.

Mixed Signal Oscilloscope: Otherwise known as an MSO; Pulse Train: A collection of pulses traveling together.
an instrument capable of displaying analog-like signal behavior Pulse Width: The amount of time the pulse takes to go from
showing voltage changes visible over time alongside digital low to high and back to low again, conventionally measured at
signals with logic states visible across the same time scale. 50% of full voltage.
Typical channel count in an MSO is 4 analog and 16 digital
channels. R
Motherboard: A computer’s main system circuit board Ramps: Transitions between voltage levels of sine waves that
containing processor, memory controller, hard disk controller, change at a constant rate.
input/output interface chipset, etc. Other circuit boards such Random Access Memory (RAM): A memory device in which
as DIMMs and video cards are plugged into the motherboard. information can be accessed in any order.
N Read Cycle: Periodically repeated sequence of events used
to read from a device.
Nanosecond (ns): A unit of time equivalent to 0.000000001
seconds. Record Length: The number of waveform points used to
create a record of a signal.
Noise: An unwanted voltage or current in an electrical circuit.
Refresh: To maintain by sending a new electric pulse to
O recharge the chips.
Oscilloscope: An instrument used to make voltage changes Registered Dual Inline Memory Module (RDIMM): Reduces
visible over time. The word oscilloscope comes from some of the problems of the tree stub architecture by buffering
“oscillate,” since oscilloscopes are often used to measure the RDIMM SDRAMs clock, command signals and address
oscillating voltages. signals on the RDIMM.
Output Enable (OE#): Activates the device output. Rise Time: The time taken for the leading edge of a pulse to
rise from its low to its high values, typically measured from
P
10% to 90%.
Period: The amount of time it takes a wave to complete one
Row Address Select (RAS#): Selects the address row of
cycle. The period equals 1/frequency.
interest within the device.

18 [Link]/memory
 SDRAM Memory Systems: Architecture Overview and Design Verification

S T
Sample Point: The raw data from an ADC used to calculate Time Domain Reflectometry (TDR): A convenient way
waveform points. to evaluate impedance values and variations along a
transmission line such as cables, connectors or a microstrip
Sample Rate: Refers to how frequently a digital measurement
on a PC board.
instrument takes a sample of the signal, specified in samples
per second (S/s). Trigger: The circuit that references a horizontal sweep on a
measurement instrument.
Sampling: The conversion of a portion of an input signal
into a number of discrete electrical values for the purpose of Trigger Holdoff: A control that allows you to adjust the period
storage, processing and/or display by an instrument. of time after a valid trigger during which the instrument cannot
trigger.
Serial Presence Detect (SPD): Uses a separate,
electronically erasable/programable, read-only memory Trigger Level: The voltage level that a trigger source signal
(EEPROM) device to hold module density, timing, and must reach before the trigger circuit initiates a sweep.
performance parameters.
U
Signal Integrity: The accurate reconstruction of a signal,
determined by the systems and performance considerations Unregistered Dual Inline Memory Module (UDIMM):
of an instrument, in addition to the probe used to acquire the UDIMMs were the first implementation of DIMMs. UDIMM has
signal. no buffering of the DDR, DDR2 and DDR3 SDRAMs signals
on the DIMM.
Signal Source: A test device used to inject a signal
into a circuit input; the circuit’s output is then read by a V
measurement instrument. Also known as a signal generator.
Very Low Profile Dual Inline Memory Module (VLP-DIMM):
Small Outline Dual Inline Memory Module (SO-DIMM): DIMMS that are shorter in height and often used in blade
Small size DIMMs used in laptops and other space constant servers.
implementations.
Volt (V): The unit of electric potential difference.
Synchronous: Synchronized. A logic analyzer state
Voltage: The difference in electric potential, expressed in
acquisition is said to be synchronous because the logic
volts, between two points.
analyzer receives its clock information from an external
source, usually the DUT. This causes the two systems to be W
synchronized, and the logic analyzer acquires data only when
Wave: The generic term for a pattern that repeats over time.
the DUT is active. This is known as the “state” acquisition
Common types include: sine, square, rectangular, saw-tooth,
mode.
triangle, step, pulse, periodic, non-periodic, synchronous,
Synchronous Dynamic Random Access Memory asynchronous.
(SDRAM): Designed to synchronize the DRAM operation to
Write Enable (WE#): Activates the write ability to the device.
the rest of the computer system and to eliminate defining
all the different modes of memory operations based on the
sequence of CE#, RAS#, CAS# and WE# edge transitions.
System Under Test (SUT): The system being tested by the
measurement instrument.

[Link]/memory 19
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Contact List Updated June 2013

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