Chapter9 Consensus
Chapter9 Consensus
q That you mention their source, after all, I would like people to use my book!
q That you note that they are adapted from (or perhaps identical to)
my slides, and note my copyright of this material.
Consensus
1 0 1 1 0 1 0
p1 p2 p3 p4 p5 p6 … pn
1 1 1 1 1 1 1
1 0 1 1 0 1 0
p1 p2 p3 p4 p5 p6 … pn
1 1 1 1 1 1 1
q Timing assumptions.
q Randomization.
3-valued RMW
register
z ^
The Algorithm
q The first process to access z sets z to its input.
r1 r2 z 0
The Algorithm
1. Each process pi uses one bit ri to announce its input.
2. Then, each process tries to set z from 0 to 1.
3. The decision value is the input of the process that
succeeds in step 2.
RMW RMW
bit bit
x 0 y 0
RMW RMW
bit bit
x 0 y 0
RMW RMW
bit bit
x 0 y 0
NO
RMW RMW
bit bit
x 0 y 0
IMPOSSIBLE!
There is NO wait-free algorithm!!!
RMW
bits 0 0 0 0 0 0
atomic
read/write 0 0 0 0 0 0
registers
IMPOSSIBLE!
There is NO wait-free algorithm!!!
atomic atomic
register register
x 0 y 0
IMPOSSIBLE!
There is NO wait-free algorithm!!!
atomic
read/write 0 0 0 0 0 0
registers
IMPOSSIBLE!
There is NO wait-free algorithm!!!
RMW
bits 0 0 0 0
x y decision finish
RMW
bits 0 0 0 0
x y decision finish
The Algorithm
1. Process 1 and process 2 execute the algorithm for two
processes using x and y.
2. Then, they write the decision value into the decision bit
and set finish to 1.
3. Each other process busy waits until finish=1, and then
decides on the value of the decision bit.
RMW
bits 0 0 0 0
x y decision finish
read/write
registers
Theorem: There is NO consensus algorithm for n
processes that can tolerate one fault, for any n.
b c
0 0
circle circle
b=0 b=1
n én/2ù n én/2ù
n = 10
0 4
B = {0,1}
b c C = {0,…,13}
0 0
circle circle
b=0 b=1
n én/2ù n én/2ù
10 5 10 5
0 0
n =10
circle circle
b=0 b=1
0 4
5
11
n én/2ù n én/2ù
b c
10 5 10 5
The Algorithm:
q Each process reads the value of the shared register,
0 4
stores it, and increments c by one (modulo |C|).
q A process becomes the master if it learns (by
inspecting c) that more than half of the processes
have waked up and the value of b has not changed.
0 0 Example:
n =10
v=0
0-interval 0-interval Example:
0 v = 11
1
b c
10 1-interval 5 10 1-interval 5
The master:
q The master decides on its own input value, say v ;
one
q if v = 0 then c ç 0 else c ç én/2ù ; atomic
action
q if b = 0 then b ç 1 else b ç 0;
0 0
n =10
0-interval 0-interval
1 5
b c
10 1-interval 5 10 1-interval 5
The master:
q continues forever setting c to the beginning of the
interval corresponding to the decision.
(i.e., if v = 0 then c ç 0 else c ç én/2ù )
0 0
n =10
0-interval 0-interval
1 5
b c
10 1-interval 5 10 1-interval 5
0 0
n =10
0-interval 0-interval
1 5
b c
10 1-interval 5 10 1-interval 5
Every process:
q after making its decision, continues forever
setting c to the beginning of the interval
corresponding to its decision.
Comments:
q There is a fault-free solution that uses only 5
values. (Based on the See-Saw Barrier, page 215.)
q The known lower bound (when there are faults) is
Ω(n0.63) values.
Requirements:
q Solution must be wait-free.
q Can use many queues & atomic registers
Observations:
q With a peek operation – trivial for many processes.
q Three processes – Impossible! (without peek)
q Two processes with initialized queue – trivial (without peek)
q Two processes with empty queue – not trivial (without peek)
Notions: run
q run, empty run,
state
event
bivalent
step by p step by q
time
bivalent bivalent
0 1 0 0 0 1 1 1
bivalent
0 1
0 0 0 1 1 1
step by p2
Since CONS is correct,
this run can not be
extended forever.
step by pn
step by p1 x
step by p2
è for some process p,
for every extension y of
step by pn x the run yp is univalent.
single step x
by p
no steps by p
the shortest
extension of x
which is
single step x
by p
no steps by p
option 1:
single step
single step by p
by p
single step x
by p
no steps by p
option 2:
not a step
by p
single step
by p
p q
p q
q does not
take steps
decide 0
A contradiction
p does not
take steps
decide 0
A contradiction
decide 0
A contradiction
q does not
take steps
• different registers
• same register
decide 0
A contradiction
QED
Examples:
• CN(atomic-register) = 1
• CN(read-modify-write bit) = 2
• CN(queue) = 2
• CN(3-valued read-modify-write register) = ¥
• CN(compare-and-swap) = ¥
Theorem: Let o1 and o2 be two objects such that CN(o1) < CN(o2).
Then, in a system with CN(o2) processes,
q There is no wait-free implementation of an object of type o2
from objects of type o1 and atomic registers;
q There is a wait-free implementation of an object of type o1
from objects of type o2 and atomic registers.
Chapter 9 Synchronization Algorithms and Concurrent Programming 55
Gadi Taubenfeld © 2014
Section 9.6
Q(Öm)
2m-2
¥
Universality