iC-MSBSAFETY, iC-MSB2

SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER

Rev F4, Page 1/35

FEATURES APPLICATIONS
• PGA inputs to 500 kHz for differential and single-ended sensor • Programmable sensor interface
signals for optical and magnetic position
• Selectable adaptation to voltage or current signals sensors
• Flexible pin assignment due to signal path multiplexers • Linear gauges and incremental
• Sine/Cosine signal conditioning for offset, amplitude and phase encoders
• Separate index signal conditioning • Linear scales
• Short-circuit-proof and reverse polarity tolerant output drivers
(1 Vpp to 100 Ω)
• Stabilized output signal levels due to sensor control
• Signal and system monitoring with configurable alarm output
• Supply voltage monitoring with integrated switches for PACKAGES
reversed-polarity-safe systems
• Excessive temperature protection with sensor calibration
• I2 C multimaster interface
• Supply from 4.3 to 5.5 V, operation within -40 to +125 °C
• Suitable for SAFETY applications within -25 to +100 °C
• Verifyable chip release code TSSOP20 QFN32
• Version iC-MSB2 with output multiplexer (not for SAFETY ) TSSOP20-TP 5 mm x 5 mm x 0.9 mm
RoHS compliant
RoHS compliant

BLOCK DIAGRAM

VDDS VDD
REVERSE POLARITY
GNDS PROTECTION GND

SCL
MONITORING

SDA
SERIAL I2C
INTERFACE
CONFIGURATION
REGISTERS iC-MSB PWRon
Tw Toff ERR

PGA INPUTS SIGNAL PATH MUX SIGNAL SIGNAL LEVEL ANALOG OUTPUT
CONDITIONING CONTROL DRIVERS
X1 PZ
I/V x
CH0 -
X2 NZ
I/V x
X3 PC
I/V x
CH2 - x
X4 NC
I/V
x + -
X5 x PS
I/V x ADJ

X6
CH1 - + x NS
I/V x
ACO

Copyright © 2006, 2020 iC-Haus [Link]

iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER

Rev F4, Page 2/35

DESCRIPTION

iC-MSB is a signal conditioner with analog line drivers thresholds are reached and indicated at alarm output
for sine/cosine sensors which are used to determine ERR.
positions in linear and angular encoders, for example.
iC-MSB is protected against a reversed power sup-
Programmable instrumentation amplifiers with se- ply voltage; the integrated voltage switch for loads
lectable gain levels permit differential or referenced of up to 20 mA extends this protection to cover the
input signals; at the same time the modes of operation overall system. The analog output drivers are directly
differentiate between high and low input impedance. cable-compatible and tolerant to false wiring; if supply
This adaptation of the iC to voltage or current signals voltage is connected up to these pins, the device is
enables MR sensor bridges or photosensors to be not destroyed.
directly connected up to the device.
The device configuration and calibration parameters
The integrated signal conditioning unit allows signal are CRC protected and stored in an external EEP-
amplitudes and offset voltages to be calibrated ac- ROM; they are loaded automatically via the I2C in-
curately and also any phase error between the sine terface once the supply voltage has been connected
and cosine signals to be corrected. Separate zero up.
signal conditioning settings can be made for the gain
and offset; data is then output either as an analog A safety-technical analysis of iC-MSB on device level
or a differential square-wave signal (low/high level with the inclusion of layout and internal/external cir-
analogous to the sine/cosine amplitude). cuitry has been carried out together with the BGIA, St.
Augustin. The result proved iC-MSB’s capability for
For the stabilization of the sine and cosine output safety oriented applications with Siemens Sinumerik
signal levels a control signal is generated from the Controls.
conditioned and calibrated input signals which can
power the transmitting LED of optical systems via the General notice on application-specific programming
Parameters defined in the datasheet represent supplier’s
integrated 50 mA driver stage (output ACO). If MR
attentive tests and validations, but - by principle - do not imply
sensors are connected this driver stage also powers any warranty or guarantee as to their accuracy, completeness or
the measuring bridges. correctness under all application conditions. In particular, setup
conditions, register settings and power-up have to be thoroughly
validated by the user within his specific application environment
By tracking the sensor energy supply any signal vari- and requirements (system responsibility).
ations and temperature and aging effects can be com-
pensated for and the set signal amplitude maintained For magnetic sensor systems: The chip’s performance in
with absolute accuracy. At the same time the control application is impacted by system conditions like the quality of
the magnetic target, field strength and stray fields, temperature
circuitry monitors both whether the sensor is function- and mechanical stress, sensor alignment and initial calibration.
ing correctly and whether it is properly connected;
signal loss due to wire breakage, short circuiting, dirt For optical sensor systems: The chip’s performance in
or aging, for example, is recognized when control application is impacted by system conditions like the quality of
the optical target, the illumination, temperature and mechanical
stress, sensor alignment and initial calibration.
 iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER

Rev F4, Page 3/35

CONTENTS

PACKAGING INFORMATION 4 Voltage Signals . . . . . . . . . . . . . . . . . 23

PIN CONFIGURATION TSSOP20,
TSSOP20-TP . . . . . . . . . . . . . . . 4 SIGNAL PATH MULTIPLEXING: iC-MSBSAFETY 25
PACKAGE DIMENSIONS : TSSOP20-TP . . 5
PIN CONFIGURATION . . . . . . . . . . . . 6 EXTENDED SIGNAL PATH MULTIPLEXING:
iC-MSB2 ( not for safety applications ) 26
PACKAGE DIMENSIONS : QFN32-5x5
(5 mm x 5 mm) . . . . . . . . . . . . . . 7
SIGNAL CONDITIONING CH1, CH2 27
ABSOLUTE MAXIMUM RATINGS 8 Gain Settings CH1, CH2 . . . . . . . . . . . . 27
Offset Calibration CH1, CH2 . . . . . . . . . 28
THERMAL DATA 8 Phase Correction CH1 vs. CH2 . . . . . . . . 28

ELECTRICAL CHARACTERISTICS 9 SIGNAL CONDITIONING CH0 29

Gain Settings CH0 . . . . . . . . . . . . . . . 29
PROGRAMMING 14
Offset Calibration CH0 . . . . . . . . . . . . . 29
CONFIGURATION REGISTERS 15
SIGNAL LEVEL CONTROL and SIGNAL
2
SERIAL I C INTERFACE 17 MONITORING 30
EEPROM Device Selection . . . . . . . . . . 17
MONITORING AND ERROR OUTPUT 31
Device Startup . . . . . . . . . . . . . . . . . 18
Error Input/Output: pin ERR . . . . . . . . . . 31
Configuration Data Checksum . . . . . . . . 18
Excessive Temperature Warning . . . . . . . 31
I2 C Slave Mode (ENSL = 1) . . . . . . . . . . 19
Analog Output Drivers Shutdown . . . . . . . 31
BIAS SOURCE AND TEMPERATURE Error Protocol . . . . . . . . . . . . . . . . . . 32
SENSOR 20
ANALOG OUTPUT DRIVERS 32
OPERATING MODES 21
Calibration Op. Modes . . . . . . . . . . . . . 21 REVERSE POLARITY PROTECTION 32
Special Device Test Functions . . . . . . . . 21
Signal Filter . . . . . . . . . . . . . . . . . . . 21 APPLICATION HINTS 33
Connecting MR sensor bridges for
TEST MODE 22 safety-related applications . . . . . . . . 33
PLC Operation . . . . . . . . . . . . . . . . . 33
PGA INPUTS CONFIGURATION 23
Current Signals . . . . . . . . . . . . . . . . . 23 REVISION HISTORY 34
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SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER

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PACKAGING INFORMATION

PIN CONFIGURATION TSSOP20, TSSOP20-TP PIN FUNCTIONS

No. Name Function
1 X1 Signal Input 1 (Index +)
X1 1 20 ERR 2 X2 Signal Input 2 (Index -)
X2 2 19 PZ 3 X3 Signal Input 3
X3 3 18 NZ 4 X4 Signal Inout 4
5 VDDS1
Switched Supply Output and Internal
X4 4 17 VDD Analog Supply Voltage
<D-CODE>

<A-CODE>

<P-CODE>

VDDS 5 16 GND (reverse-polarity-proof, load 20 mA

GNDS 6 15 PS max.)
X5 7 14 NS 6 GNDS1 Switched Ground
(reverse-polarity-proof)
X6 8 13 PC 7 X5 Signal Input 5
ACO 9 12 NC 8 X6 Signal Input 6
SDA 10 11 SCL 9 ACO Signal Level Controller,
high-side current source output
10 SDA Serial Configuration Interface,
data line
11 SCL Serial Configuration Interface,
clock line
12 NC Neg. Cosine Output
13 PC Pos. Cosine Output
14 NS Neg. Sine Output
15 PS Pos. Sine Output
16 GND Ground
17 VDD +4.5 to +5.5 V Supply Voltage
18 NZ Neg. Index Output
19 PZ Pos. Index Output
20 ERR Error Signal (In/Out), and
Test Mode Trigger Input

TP2 Thermal Pad (TSSOP20-TP)

IC top marking: <P-CODE> = product code, <A-CODE> = assembly code (subject to changes), <D-CODE> = date code (subject to changes);
1
It is advisable to connect a bypass capacitor of about 100 nF (up to 1 µF max.) close to the chip’s analog supply terminals.
2
To improve heat dissipation the thermal pad of the package (bottom side) should be joined to an extended copper area which must have GNDS potential.
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SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER

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PACKAGE DIMENSIONS : TSSOP20-TP

SIDE FRONT

0.15
0.90

4°
0.10 0.60

TOP RECOMMENDED PCB-FOOTPRINT

6.50
4.20 4.20
4.40
6.40

5.40
3

3
1.60
0.65 0.25
0.65 0.40
All dimensions given in mm.
Tolerances of form and position according to JEDEC MO-153 dra_tssop20-tp-1_pack_1, 8:1
 iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER

Rev F4, Page 6/35

PIN CONFIGURATION PIN FUNCTIONS

No. Name Function
1, 2 n.c.3
32 31 30 29 28 27 26 25 3 ERR Error Signal (In/Out), and
Test Mode Trigger Input
1 24 4, 5 n.c.3
2 23 6 X1 Signal Input 1 (Index +)
7 X2 Signal Input 2 (Index -)
3 22 8, 9 n.c.3
4 21 10 X3Signal Input 3
<P-CODE>
5 20 11 X4Signal Inout 4
6 <A-CODE> 19 12 VDDS1
Switched Supply Output and Internal
7 18 Analog Supply Voltage
<D-CODE> (reverse-polarity-proof, load 20 mA
8 17 max.)
13 GNDS1 Switched Ground
9 10 11 12 13 14 15 16 (reverse-polarity-proof)
14 X5 Signal Input 5
15 X6 Signal Input 6
16 n.c.3
17 ACO Signal Level Controller,
high-side current source output
18 n.c.3
19 SDA Serial Configuration Interface,
data line
20, 21 n.c.3
22 SCL Serial Configuration Interface,
clock line
23, 24 n.c.3
25 NC Neg. Cosine Output
26 PC Pos. Cosine Output
27 NS Neg. Sine Output
28 PS Pos. Sine Output
29 GND Ground
30 VDD +4.5 to +5.5 V Supply Voltage
31 NZ Neg. Index Output
32 PZ Pos. Index Output
BP2 Backside Paddle
(top view) IC top marking: <P-CODE> = product code, <A-CODE> = assembly code (subject to changes), <D-CODE> = date code (subject to changes);
1
It is advisable to connect a bypass capacitor of about 100 nF (up to 1 µF max.) close to the chip’s analog supply terminals.
2
To improve heat dissipation the backside paddle should be soldered and joined to an extended copper area, which must have GNDS potential.
3
Pin numbers marked n.c. are not connected.
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SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER

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PACKAGE DIMENSIONS : QFN32-5x5 (5 mm x 5 mm)

RECOMMENDED PCB-FOOTPRINT
4.90
3.60 15
R0.

SIDE 0.90 ±0.10

4.90
3.60
0.70
0.50 0.30

TOP BOTTOM
5 3.65

3.65
5

0.40

0.50 0.22
All dimensions given in mm.
Tolerances of form and position according to JEDEC MO-220. drb_qfn32-5x5-6_pack_1, 10:1
 iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER

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ABSOLUTE MAXIMUM RATINGS

These ratings do not imply operating conditions; functional operation is not guaranteed. Beyond these ratings device damage may occur.
Item Symbol Parameter Conditions Unit
No. Min. Max.
G001 V() Voltage at VDD, GND, PC, NC, PS, NS, -6 6 V
PZ, NZ, ACO
G002 V() Voltage at ERR -6 8 V
G003 V() Pin-To-Pin Voltage between VDD, GND, 6 V
PC, NC, PS, NS, PZ, NZ, ACO, ERR
G004 V() Voltage at X1...X6, SCL, SDA -0.3 VDDS + V
0.3
G005 I(VDD) Current in VDD -100 100 mA
G006 I() Current in VDDS, GNDS -50 50 mA
G007 I() Current in X1...X6, SCL, SDA, ERR, PC, -20 20 mA
NC, PS, NS, PZ, NZ
G008 I(ACO) Current in ACO -100 20 mA
G009 Vd() ESD Susceptibility at all pins HBM 100 pF discharged through 1.5 kΩ 2 kV
G010 Ptot Permissible Power Dissipation TSSOP20 300 mW
TSSOP20-TP, QFN32-5x5 400 mW
G011 Tj Junction Temperature -40 150 °C
G012 Ts Storage Temperature Range -40 150 °C

THERMAL DATA
VDD = 4.3...5.5 V
Item Symbol Parameter Conditions Unit
No. Min. Typ. Max.
T01 Ta Operating Ambient Temperature Range iC-MSB2 TSSOP20 -25 100 °C

iC-MSB TSSOP20 -25 100 °C

iC-MSB TSSOP20-TP -40 125 °C
iC-MSB QFN32-5x5 -40 125 °C
T02 Ta_safe Operating Ambient Temperature Range for iC-MSB and all package models -25 100 °C
for SAFETY Applications
T03 Rthja Thermal Resistance Chip to Ambient TSSOP20 surface mounted to PCB 80 K/W
according to JEDEC 51
T04 Rthja Thermal Resistance Chip to Ambient TSSOP20-TP surface mounted to PCB (incl. 35 K/W
the thermal pad), according to JEDEC 51
T05 Rthja Thermal Resistance Chip to Ambient QFN32-5x5 surface mounted to PCB (incl. the 40 K/W
backside paddle), according to JEDEC 51

All voltages are referenced to Pin GNDS unless otherwise stated.

All currents flowing into the device pins are positive; all currents flowing out of the device pins are negative.
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SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER

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ELECTRICAL CHARACTERISTICS
Operating conditions: VDD = 4.3...5.5 V, Tj = -40...140 °C, IBN calibrated to 200 µA, reference point GNDS, unless otherwise stated.
Item Symbol Parameter Conditions Unit
No. Min. Typ. Max.
Total Device
001 VDD Permissible Supply Voltage VDD load current I(VDDS) up to 10 mA 4.3 5.5 V
versus GND load current I(VDDS) up to 20 mA 4.5 5.5 V
002 I(VDD) Supply Current in VDD to GND Tj = 27 °C, no load 25 50 mA
003 I(VDDS) Permissible Load Current VDDS -20 0 mA
004 Vcz()hi Clamp Voltage hi at all pins 11 V
005 Vc()hi Clamp Voltage hi at inputs Vc()hi = V() − V(VDDS), I() = 1 mA 0.4 1.5 V
SCL, SDA
006 Vc()hi Clamp Voltage hi at inputs Vc()hi = V() − V(VDDS), I() = 4 mA 0.3 1.2 V
X1...X6
007 Vc()lo Clamp Voltage lo at all pins I() = -4 mA -1.2 -0.3 V
008 Irev(VDD) Reverse-Polarity Current VDD vs. V(VDD) = −5.5 V...−4.3 V -1 1 mA
GND
PGA Inputs and Signal Conditioning: X3...X6
101 Vin()sig Permissible Input Voltage Range RIN12(3:0) = 0x01 0.75 VDDS V
− 1.5
RIN12(3:0) = 0x09, BIAS12 = 1 0 VDDS V
RIN12(3:0) = 0x09, BIAS12 = 0 0 VDDS V
− 1.5
102 Iin()sig Permissible Input Current Range RIN12(0) = 0, BIAS12 = 0 -300 -10 µA
RIN12(0) = 0, BIAS12 = 1 10 300 µA
103 Iin() Input Current RIN12(3:0) = 0x01 -10 10 µA
104 Rin() Input Resistance vs. VREFin Tj = 27 °C;
RIN12(3:0) = 0x09 16 20 24 kΩ
RIN12(3:0) = 0x00 1.1 1.6 2.1 kΩ
RIN12(3:0) = 0x02 1.6 2.3 3.0 kΩ
RIN12(3:0) = 0x04 2.2 3.2 4.2 kΩ
RIN12(3:0) = 0x06 3.2 4.6 6.0 kΩ
105 TCRin() Temperature Coefficient Rin 0.15 %/K
106 VREFin12 Reference Voltage RIN12(0) = 0, BIAS12 = 1 1.35 1.5 1.65 V
RIN12(0) = 0, BIAS12 = 0 2.25 2.5 2.75 V
107 G12 Selectable Gain Factors RIN12(3:0) = 0x01, GR12, GF1, GF2 = 0x0 2
RIN12(3:0) = 0x01, GR12, GF1, GF2 = max. 100

RIN12(3:0) = 0x09, GR12, GF1, GF2 = 0x0 0.5

RIN12(3:0) = 0x09, GR12, GF1, GF2 = max. 25
108 ∆Gdiff Differential Gain Accuracy calibration range 11 bit -0.5 0.5 LSB
109 ∆Gabs Absolute Gain Accuracy calibration range 11 bit, guaranteed monotony -1 1 LSB
110 Vin()diff Recommended Differential Input Vin()diff = V(CHPx) − V(CHNx);
Voltage RIN12(3) = 0 10 500 mVpp
RIN12(3) = 1 40 2000 mVpp
111 Vin()os Input Offset Voltage refered to side of input 20 µV
112 VOScal Offset Calibration Range referenced to the selected source (VOS12);
ORx = 00 ±100 %V()
ORx = 01 ±200 %V()
ORx = 10 ±600 %V()
ORx = 11 ±1200 %V()
113 ∆VOSdiff Differential Linearity Error of calibration range 11 bit -0.5 0.5 LSB
Offset Correction
114 ∆VOSint Integral Linearity Error of Offset calibration range 11 bit -1 1 LSB
Correction
115 PHIkorr Phase Error Calibration Range CH1 versus CH2 ±10.4 °
116 ∆PHIdiff Differential Linearity Error of calibration range 10 bit -0.5 0.5 LSB
Phase Calibration
117 ∆PHIint Integral Linearity Error of Phase calibration range 10 bit -1 1 LSB
Calibration
119 fin()max Permissible Input Frequency 500 kHz
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ELECTRICAL CHARACTERISTICS
Operating conditions: VDD = 4.3...5.5 V, Tj = -40...140 °C, IBN calibrated to 200 µA, reference point GNDS, unless otherwise stated.
Item Symbol Parameter Conditions Unit
No. Min. Typ. Max.
120 fc()in Input Amplifier Cut-off Frequency 250 kHz
(-3dB)
PGA Inputs and Signal Conditioning: X1, X2
201 Vin()sig Permissible Input Voltage Range RIN0(3:0) = 0x01 0.75 VDDS V
− 1.5
RIN0(3:0) = 0x09 0 VDDS V
202 Iin()sig Permissible Input Current Range RIN0(0) = 0, BIAS0 = 0 -300 -10 µA
RIN0(0) = 0, BIAS0 = 1 10 300 µA
203 Iin() Input Current RIN0(3:0) = 0x01 -10 10 µA
204 Vout(X2) Output Voltage at X2 BIASEX = 10, I(X2) = 0, referenced to VRE- 95 100 105 %
Fin12
205 Vin(X2) Permissible Input Voltage at X2 BIASEX = 11 0.5 VDDS V
−2
206 Rin(X2) Input Resistance at X2 BIASEX = 11, RIN0(3:0) = 0x01, RIN12(3:0) = 20 27 35 kΩ
0x01
207 Rin() Input Resistance vs. VREFin Tj = 27 °C;
RIN0(3:0) = 0x09 16 20 24 kΩ
RIN0(3:0) = 0x00 1.1 1.6 2.1 kΩ
RIN0(3:0) = 0x02 1.6 2.3 3.0 kΩ
RIN0(3:0) = 0x04 2.2 3.2 4.2 kΩ
RIN0(3:0) = 0x06 3.2 4.6 6.0 kΩ
208 TCRin() Temperature Coefficient Rin 0.15 %/K
209 VREFin0 Reference Voltage RIN0(0) = 0, BIAS0 = 1 1.35 1.5 1.65 V
RIN0(0) = 0, BIAS0 = 0 2.25 2.5 2.75 V
210 G0 Selectable Gain Factors RIN0(3:0) = 0x01, GR0 and GF0 = 0x0 2
RIN0(3:0) = 0x01, GR0 and GF0 = max. 100

RIN0(3:0) = 0x09, GR0 and GF0 = 0x0 0.5

RIN0(3:0) = 0x09, GR0 and GF0 = max 25
211 ∆Gdiff Differential Gain Accuracy calibration range 5 bit -0.5 0.5 LSB
212 ∆Gabs Absolute Gain Accuracy calibration range 5 bit, guaranteed monotony -1 1 LSB
213 Vin()diff Recommended Differential Input Vin()diff = V(CHP0) - V(CHN0);
Voltage RIN0(3:0) = 0x01 10 500 mVpp
RIN0(3:0) = 0x09 40 2000 mVpp
214 Vin()os Input Offset Voltage referred to side of input 75 µV
215 VOScal Offset Calibration Range referenced to the selected source (REFVOS);
OR0 = 00 ±100 %V()
OR0 = 01 ±200 %V()
OR0 = 10 ±600 %V()
OR0 = 11 ±1200 %V()
216 ∆VOSdiff Differential Linearity Error of calibration range 6 bit -0.5 0.5 LSB
Offset Correction
217 ∆VOSint Integral Linearity Error of Offset calibration range 6 bit -1 1 LSB
Correction
Signal Filter
301 fc Cut-off Frequency ENF = 1, f()in 100 kHz for sine/cosine 4000 kHz
302 phi Phase Delay (output vs. input) ENF = 1, f()in 500 kHz for sine/cosine 10 °
Index Pulse Comparator Output PZ, NZ
401 Vpk() Output Amplitude With Sensor EAZ = 1, ADJ(4:0) = 0x19 225 250 275 mV
Tracking via ACO
402 SR() Output Slew Rate EAZ = 1 1 V/µs
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ELECTRICAL CHARACTERISTICS
Operating conditions: VDD = 4.3...5.5 V, Tj = -40...140 °C, IBN calibrated to 200 µA, reference point GNDS, unless otherwise stated.
Item Symbol Parameter Conditions Unit
No. Min. Typ. Max.
Analog Output Drivers: PS, NS, PC, NC, PZ, NZ
501 Vpk()max Permissible Max. Output VDD = 4.5 V, DC level = VDD/2, 300 mV
Amplitude RL = 50 Ω vs. VDD/2
502 Vpk() Output Amplitude With Sensor ADJ (8:0) = 0x19 225 250 275 mV
Tracking via ACO
503 Vdc() DC Output Voltage versus GND; reference is VPAH, see 802 for 50 % VDD
tolerances
504 fc()out Cut-off Frequency CL = 250 pF 500 kHz
506 Isc() Short-circuit Current pin shorten to VDD or GND 10 30 50 mA
507 Ilk() Tristate Leakage Current tristate or reversed supply -1 1 µA
508 Rout() Output Impedance MODE = 0x02 (mode calibration 2), BYP = 0 5 kΩ
509 fout()cal Permissible Output Frequency for MODE = 0x02 (mode calibration 2), BYP = 0 2 kHz
Calibration CL = 250 pF
510 Rout()tm Bypass Resistance MODE = 0x02, 0x06, BYP = 1 7 kΩ
Signal Level Controller ACO
601 Vs()hi Saturation Voltage hi Vs() = VDD - V();
at ACO vs. VDD ADJ(8:0) = 0x11F, I() = -5 mA 1 V
ADJ(8:0) = 0x13F, I() = -10 mA 1 V
ADJ(8:0) = 0x15F, I() = -25 mA 1 V
Tj ≤ 125 °C, ADJ(8:0) = 0x17F, I() = -50 mA 1 V
Tj > 125 °C, ADJ(8:0) = 0x17F, I() = -50 mA 1.2 V
602 Isc()hi Short-circuit Current hi in ACO Tj ≤ 125 °C, V() = 0 ... VDD - 1 V;
Tj > 125 °C, V() = 0 ... VDD - 1.2 V;
ADJ(8:0) = 0x11F -10 -5 mA
ADJ(8:0) = 0x13F -20 -10 mA
ADJ(8:0) = 0x15F -50 -25 mA
ADJ(8:0) = 0x17F -100 -66 -50 mA
603 tr() Current Rise Time in ACO I(ACO): 0 → 90 % setpoint 1 ms
604 tset() Current Settling Time in ACO Square control, I(ACO): 50 → 100 % setpoint 400 µs
605 It()min Control Range Monitoring 1: referenced to range ADJ(6:5) 3 %Isc
lower limit
606 It()max Control Range Monitoring 2: referenced to range ADJ(6:5) 90 %Isc
upper limit
607 Vt()min Signal Level Monitoring 1: referenced to Vscq() 40 %Vpp
lower limit
608 Vt()max Signal Level Monitoring 2: referenced to Vscq() 130 %Vpp
upper limit
609 Vin(ACO) Permissible Input Voltage for versus GNDS, VOS12 = 0x0 0 VDDS V
Offset-Tracking
Test Current ERR
701 I(ERR) Permissible Test Current test mode activated 0 1 mA
Bias Current Source and Reference Voltages
801 IBN() Bias Current Source MODE(3:0) = 0x01, I(NC) vs. VDDS 180 200 220 µA
802 VPAH Reference Voltage VPAH referenced to GND 45 50 55 %VDD
803 V05 Reference Voltage V05 450 500 550 mV
804 V025 Reference Voltage V025 50 %V05
Power-Down-Reset
901 VDDon Turn-on Threshold increasing voltage at VDD vs. GND 3.7 4 4.3 V
(power-on release)
902 VDDoff Turn-off Threshold decreasing voltage at VDD vs. GND 3.2 3.5 3.8 V
(power-down reset)
903 VDDhys Threshold Hysteresis VDDhys = VDDon − VDDoff 0.3 V
Clock Oscillator
A01 fclk() Internal Clock Frequency MODE(3:0) = 0x0A (measured at pin NS) 120 160 200 kHz
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ELECTRICAL CHARACTERISTICS
Operating conditions: VDD = 4.3...5.5 V, Tj = -40...140 °C, IBN calibrated to 200 µA, reference point GNDS, unless otherwise stated.
Item Symbol Parameter Conditions Unit
No. Min. Typ. Max.
Error Input/Output: ERR
B01 Vs()lo Saturation Voltage lo vs. GND, I() = 4 mA 0.4 V
B02 Isc() Short-circuit Current lo vs. GND; V(ERR) ≤ VDD 4 mA
V(ERR) > VTMon 2 mA
B03 Vt()hi Input Threshold Voltage hi vs. GND 2 V
B04 Vt()lo Input Threshold Voltage lo vs. GND 0.8 V
B05 Vt()hys Input Hysteresis Vt()hys = Vt()hi − Vt()lo 300 500 mV
B06 Ipu() Input Pull-up Current V() = 0 . . . VDD − 1 V, EPU = 1 -400 -300 -200 µA
B07 Rpu() Input Pull-Up Resistor EPU = 0 500 kΩ
B08 Vpu() Pull-up Voltage Vpu() = VDD − V(), I() = -5 µA, EPU = 1 0.4 V
B09 VTMon Test Mode Activation Threshold increasing voltage at ERR VDD + V
1.5
B10 VTMoff Test Mode Disabling Threshold decreasing voltage at ERR VDD + V
0.5
B11 VTMhys Test Mode Hysteresis VTMhys = VTMon − VTMoff 0.15 0.3 V
B12 Ilk() Leakage Current tristate or reversed supply voltage -1 -10 -50 µA
B13 tp()tri Propagation Delay System Error V(ERR): hi → lo 35 µs
to Driver Shutdown (tristate)
Supply Switch and Reverse Polarity Protection: VDDS, GNDS
C01 Vs() Saturation Voltage Vs(VDDS) = VDD − V(VDDS)
VDDS vs. VDD I(VDDS) = -10 mA...0 mA 150 mV
I(VDDS) = -20 mA...-10 mA 250 mV
C02 Vs() Saturation Voltage Vs(GNDS) = V(GNDS) − GND
GNDS vs. GND I(GNDS) = 0 mA...10 mA 150 mV
I(GNDS) = 10 mA...20 mA 250 mV
C03 C() Backup Capacitor Analog Supply 100 nF
VDDS vs. GNDS
Serial I2 C Interface: SCL, SDA
D01 Vs()lo Saturation Voltage lo I() = 4 mA 400 mV
D02 Isc() Short-circuit Current lo 4 80 mA
D03 Vt()hi Input Threshold Voltage hi 2 V
D04 Vt()lo Input Threshold Voltage lo 0.8 V
D05 Vt()hys Input Hysteresis Vt()hys = Vt()hi − Vt()lo 300 500 mV
D06 Ipu() Input Pull-up Current V() = 0...VDDS − 1 V -650 -300 -60 µA
D07 Vpu() Input Pull-up Voltage Vpu() = VDDS − V(), I() = -5 µA 0.4 V
D08 fclk(SCL) Clock Frequency at SCL ENFAST = 0 60 80 100 kHz
ENFAST = 1 240 320 400 kHz
D09 tbusy()cfg Duration of Startup Configuration IBN not calibated, EEPROM access without
read failure, time to outputs operational;
ENFAST = 0 40 55 ms
ENFAST = 1 25 35 ms
D10 tbusy()err End Of I2C Communication; Time IBN not calibrated;
Until I2C Slave Mode Is Enabled V(SDA) = 0 V 4 12 ms
V(SCL) = 0 V or arbitration lost indef. ms
no EEPROM 45 135 ms
CRC ERROR 95 285 ms
D11 td() Start Of Master Activity On I2C SCL without clock signal: V(SCL) = constant;
Protocol Error IBN not calibrated 25 80 240 µs
IBN calibrated to 200 µA 64 80 120 µs
D12 td()i2c I2C-Slave Mode Enable Delay no EEPROM, V(SDA) = 0 V 4 6.2 ms
D13 fclk()ext Permissible External Clock Fre- 400 kHz
quency at SCL
iC-MSBSAFETY, iC-MSB2
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Rev F4, Page 13/35

ELECTRICAL CHARACTERISTICS
Operating conditions: VDD = 4.3...5.5 V, Tj = -40...140 °C, IBN calibrated to 200 µA, reference point GNDS, unless otherwise stated.
Item Symbol Parameter Conditions Unit
No. Min. Typ. Max.
Temperature Monitoring
E01 VTs Temperature Sensor Voltage VTs() = VDDS − V(PS), Tj = 27 °C, 600 650 700 mV
Calibration Mode 3, no load
E02 TCs Temp. Co. of Temperature Sen- -1.8 mV/K
sor Voltage
E03 VTth Temperature Warning Activation VTth() = VDDS − V(NS), Tj = 27 °C,
Threshold Calibration Mode 3, no load;
CFGTA(3:0) = 0x00 260 310 360 mV
CFGTA(3:0) = 0x0F 470 550 630 mV
E04 TCth Temp. Co. Temperature Warning 0.06 %/K
Activation Threshold
E05 Thys Temperature Warning Hysteresis Tj = 27 °C 4 12 20 °C
E06 ∆T Relative Shutdown Temperature ∆T = Toff − Tw, Tj = 27 °C 4 12 20 °C
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Rev F4, Page 14/35

PROGRAMMING

Register Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 15 Signal Conditioning CH1, CH2 (X3...X6) . . Page 27

GR12: Gain Range CH1, CH2 (coarse)
GF1: Gain Factor CH1 (fine)
Serial I2 C Interface . . . . . . . . . . . . . . . . . . . . . . . . Page 17 GF2: Gain Factor CH2 (fine)
ENFAST: I2 C Fast Mode Enable VOS12: Offset Reference Source CH1, CH2
ENSL: I2 C Slave Mode Enable VDC1: Intermediate Voltage CH1
DEVID: Device ID of EEPROM providing the chip VDC2: Intermediate Voltage CH2
configuration data (e.g. 0x50) OR1: Offset Range CH1 (coarse)
CHKSUM: CRC of chip configuration data OF1: Offset Factor CH1 (fine)
(address range 0x00 to 0x1E) OR2: Offset Range CH2 (coarse)
CHPREL: Chip Release OF2: Offset Factor CH2 (fine)
NTRI: Tristate Function and PH12: Phase Correction CH1 vs. CH2
Op. Mode Change
Signal Conditioning CH0 (X1, X2) . . . . . . . . . Page 29
Bias Current Source and GR0: Gain Range CH0 (coarse)
Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . Page 20 GF0: Gain Factor CH0 (fine)
CFGIBN: Bias Calibration VOS0: Offset Reference Source CH0
CFGTA: Temperature Sensor Calibration OR0: Offset Range CH0 (coarse)
OF0: Offset Factor CH0 (fine)
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . Page 21
MODE: Operation Mode Signal Level Control . . . . . . . . . . . . . . . . . . . . . . Page 30
ENF: Signal Filtering ADJ: Setup of ACO Output Function

Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Seite 22 Monitoring and Error Output . . . . . . . . . . . . . Page 31

TMODE: Test Mode Functions EPH: I/O Logic Alarm Output ERR
TMEM: Test Mode Memory Selection EMTD: Min. Indication Time Alarm Outp. ERR
EPU: Pull-Up Enable Alarm Output ERR
PGA Inputs Configuration and EMASKA: Error Mask Alarm Output ERR
Signal Path Multiplexer . . . . . . . . . . . . . . . . . . . Page 23 EMASKO: Error Mask Driver Shutdown
INMODE: Diff./Single-Ended Input Mode EMASKE: Error Mask EEPROM Savings
RIN12: I/V Mode and Input Resistance CH1, CH2
BIAS12: Reference Voltage CH1, CH2 ERR1: Error Protocol: First Error
RIN0: I/V Mode and Input Resistance CH0 ERR2: Error Protocol: Last Error
BIAS0: Reference Voltage CH0 ERR3: Error Protocol: History
MUXIN: Input-To-Channel Assignment:
X3...X6 to CH1, CH2 PDMODE: Driver Activation
INVZ: Index Signal Inversion
EAZ: Index Comparator Enable
MUXOUT: Output Multiplexer (iC-MSB2 only)
BIASEX: Input Reference Selection
BYP Input-to-output Feedthrough
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Rev F4, Page 15/35

CONFIGURATION REGISTERS

Register Map
Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Configuration Interface
0x00 ENFAST DEVID(6:0)
Calibration
0x01 CFGIBN(3:0) CFGTA(3:0)
Operation Modes
0x02 NTRI* 1 0 – MODE(3:0)
Input Configuration and Signal Path Multiplexer: iC-MSB
0x03 EAZ 0 0 0 INVZ INMODE MUXIN(1:0)
Input Configuration and Signal Path Multiplexer: iC-MSB2
0x03 EAZ MUXOUT(2:0) INVZ INMODE MUXIN(1:0)
Signal Conditioning CH1, CH2
0x04 GF2(4:0) GR12(2:0)
0x05 GF1(7:0)
0x06 VDC1(4:0) GF1(10:8)
0x07 VDC2(2:0) VDC1(9:5)
0x08 OR1(0) VDC2(9:3)
0x09 OF1(6:0) OR1(1)
0x0A OF2(1:0) OR2(1:0) OF1(10:7)
0x0B OF2(9:2)
0x0C PH12(6:0) OF2(10)
0x0D BIASEX(1:0) BYP 1 1 PH12(9:7)
0x0E ENF BIAS12 VOS12(1:0) RIN12(3:0)
Signal Level Controller
0x0F ADJ(0) – 0 1 0 0 0 0
0x10 ADJ(8:1)
Signal Conditioning CH0
0x11 GF0(4:0) GR0(2:0)
0x12 OF0(5:0) OR0(1:0)
0x13 0 BIAS0 VOS0(1:0) RIN0(3:0)
Error Monitoring and Alarm Output
0x14 0 EMASKA(6:0)
0x15 TMODE(1:0) EMTD(2:0) EPH 0 0
0x16 0 EMASKO(6:0)*
0x17 EMASKE(3:0) ENSL EPU 0 0
0x18 TMEM PDMODE 0 0 0 EMASKE(6:4)*
0x19.. not defined
0x1A
0x1B.. OEM Data
0x1E
Check Sum / Chip Release
0x1F EEPROM: CHKSUM(7:0) / ROM: CHPREL(7:0)
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Rev F4, Page 16/35

Register Map
Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Error Register
0x20 – ERR1(6:0)
0x21 ERR2(5:0) – –
0x22 ERR3(3:0) – – – ERR2(6)
0x23 – – – – – ERR3(6:4)
Notes The device RAM initially contains random data following power-on.
*) Mandatory programming of EEPROM: NTRI = 1, EMASKO(6) = 0, EMASKE(6) = 0.

Table 4: Register layout (EEPROM)

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Rev F4, Page 17/35

SERIAL I2 C INTERFACE

The multi-master capable I2 C interface consists of two I2 C Master Performance

bidirectional pins, SCL (for clock) and SDA (for data), Protocol Standard I2 C
and enables iC-MSB to restore its configuration from Output Clock Rate 100 kHz max. (see [Link]. D08),
the external serial EEPROM. For this function, the read- 400 kHz max. using ENFAST = 1
out can be accelerated from ENFAST reading onwards Addressing 11 bit: 8 bit register address plus
3 bit block selection
if a higher clock frequency is selected as an option.
Access Trials Read: up to 4x at power-on (I2 C error:
acknowledge missing),
1x at byte reading, 1x at byte writing
(for consecutive writing with pauses
The I2 C master of iC-MSB addresses I2 C devices using from byte to byte)
an 8-bit register address plus 3 block selection bits as Multi-Master Capability Yes
part of the I2 C device ID. That way an external EEP- I2 C Slave Performance
ROM of up to 2 Kbit is addressed at 0x50 (for ’1010 Input Clock Rate 400 kHz max. (see [Link]. D13)
000’ without the R/W bit), or 0xA0 respectively (for Device ID 0x55 (’1010 101’ w/o R/W bit)
’1010 0000’ with the R/W bit as zero), whereas the
block selections bits are zero. Table 7: I2 C interface performance

fclk(SCL)
Note: The I2 C bus lines are sensitive. Keeping the
SCL
traces short and shielding them with ground prevents
unwanted actions.
SDA S 1 0 1 0 A10 A9 A8 W ACK A7 ... A0 ACK D7 … D0 ACK P
The use of pull-up resistors (e.g. 2.2 kΩ at SCL and
SDA) supports the bus signals on logic high and im-
Start Slave Address Write ACK Slave Address ACK Data (8 bit) ACK Stop
cond. (4 bit Device ID + upper 3 bits of 11 Bit address) lower 8 bits cond.

proves the EMI immunity.

Figure 1: I2 C slave addressing for writing a single
byte to the EEPROM.
Note: When programming the EEPROM in-circuit,
iC-MSB must be powered up in advance to avoid in-
terferences by its I2 C master. Note that power must
Furthermore, the I2 C interface can be enabled to oper- be maintained (e.g. for 10 ms) to allow the EEPROM
ate as an I2 C slave (using ENSL), allowing an external finishing its write operation.
I2 C master to monitor and edit iC-MSB’s configuration
data. Attention: If a power failure interrupts the EEPROM’s
write operation, the entire page content may be lost.

ENFAST Addr. 0x00, bit 7 Attention: If error logging is enabled and periodic
Code Function errors occur, the maximum permissible write cycles
0 Regular clock rate, f(SCL) approx. 80 kHz may be exceeded. The recommended precaution is to
1 High clock rate, f(SCL) approx. 320 kHz disable error logging (refer to EMASKE), and to lock
Notes For in-circuit programming bus lines SCL and SDA the EEPROM by its WP pin after factory calibration.
require pull-up resistors (e.g. 2.2 kΩ for line
capacitances of up to 170 pF and clock rate 320 kHz;
the permissible minimum value is 1.5 kΩ).
A ground trace between SCL and SDA is
recommended to avoid cross talk.

Table 5: I2 C Fast Mode

ENSL Addr. 0x17, bit 3

Code Function
0 I2 C slave mode disabled
1 I2 C slave mode enabled (Device ID 0x55)

Table 6: I2 C Slave Mode

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Rev F4, Page 18/35

EEPROM Device Selection Device Startup

Once the supply has been switched on, i.e. after
a power down reset, the iC-MSB outputs are high
EEPROM Device Requirements impedance (tristate) until a valid configuration is read
Supply Voltage 3.3 V to 5.5 V from the EEPROM using device ID 0x50.
Power-On Threshold < 3.3 V (due to [Link]. 901)
Addressing 11 bit address max. If the configuration data is not confirmed by its check-
Device Address 0x50 (’1010 000’ w/o R/W bit), sum, the readin process is repeated. If no valid config-
0xA0 (’1010 0000’ with R/W = 0) uration data is available after a fourth attempt, iC-MSB
Page Buffer Support of Page Write with pages of at terminates communication with the EEPROM and en-
least 4 bytes.
ables I2 C slave mode. For timing information, refer to
Size Minimum 512 bit (64x8 bit)
(address range used is 0x00 to 0x3F)
the Electrical Characteristics, items D10 and D11.
Size Maximum 8 Kbit (4x 256x8 bit), type 24C08
If I2 C Slave Mode is disabled: For devices loading valid configuration data from the
16 Kbit (8x 256x8 bit), type 24C16 EEPROM, bit ENSL decides whether the I2 C slave func-
tion is enabled or not.
Table 8: EEPROM Device Requirements
Configuration Data Checksum
If the EEPROM does not feature Page Write, error The checksum at address 0x1F is used to initially con-
events can not be saved (EMASKE must be configured firm the configuration data read from the EEPROM.
to 0x00).

The following EEPROMs have been recommended, but

CHKSUM Addr. 0x1F, bit 7:0
may need to be re-tested for the above conditions: At-
Code Function
mel AT24C01, ST M24C01, ST M24C02 (2K), ROHM
0x00... Checksum for address range 0x00 to 0x1E;
BR24L01A-W, BR24L02-W. ...0xFF CRC polynomial 0x11D (x 8 + x 4 + x 3 + x 2 + 1)
Start value: 0x01
Attention: EEPROMs that ignore the block select or
upper address bits in the control byte (such as the Table 9: Configuration Data Checksum
Microchip 24AA0x/24LC0xB, and maybe other 5-pin
devices) should not be used with the iC-MSB.
EEPROMs that use the address pins as additional Example of CRC Calculation Routine:
enable bits should be used instead. unsigned char ucDataStream = 0 ;
i n t iCRCPoly = 0x11D ;
unsigned char ucCRC=0;
int i = 0;
Attention: When I2 C Slave Mode is enabled, iC-MSB
responds to device ID 0x55, limiting the maximum ucCRC = 1 ; / / s t a r t v a l u e ! ! !
f o r ( iReg = 0 ; iReg <31; iReg ++)
EEPROM size to 8 Kbit (0x50 to 0x53 addresses 4x {
256 bytes). ucDataStream = ucGetValue ( iReg ) ;
f o r ( i =0; i <=7; i ++) {
i f ( ( ucCRC & 0x80 ) ! = ( ucDataStream & 0x80 ) )
ucCRC = (ucCRC << 1 ) ^ iCRCPoly ;
else
ucCRC = (ucCRC << 1 ) ;
ucDataStream = ucDataStream << 1 ;
}
}
 iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER

Rev F4, Page 19/35

I2 C Slave Mode (ENSL = 1) Register Read access in I2 C slave mode (ENSL = 1)

In this mode iC-MSB behaves like an I2 C slave with the Address Content
device ID 0x55 and the configuration interface permits 0x00-0x18 Configuration: register addresses 0x00-0x18
write and read accesses to iC-MSB’s internal registers. 0x19-0x1A Not available
0x1B-0x1E OEM data (4 byte)
CHPREL Adr 0x1F, bit 7:0 (ROM) (see EEPROM addresses 0x1B-0x1E)
Code Chip Release 0x1F Chip release (ROM)
0x00 Not available 0x20-0x23 Configuration: register addresses 0x20-0x23
0x04 iC-MSB SAFETY v4 0x24-0x37 Not available
0x05 iC-MSB SAFETY v5 0x38 Configuration: register address 0x18
0x25 iC-MSB2 v5 0x39-0x3A Not available
0x3B-0x3E OEM data (4 byte)
(see EEPROM addresses 0x1B-0x1E)
Table 10: Chip Release
0x3F Chip release (ROM)
0x40-0x43 Current error memory
NTRI Adr 0x02, bit 7 (only active if enabled by EMASKE; messages are
Code Function transferred to EEPROM Addresses 0x20-0x23)
0 Output drivers disabled 0x44-0x7F Not available
1 Setting the operating mode, output drivers active
Notes NTRI is evaluated only during I2 C slave mode. Table 12: RAM Read Access

Table 11: Tristate Function And Op. Mode Change Register Write access in I2 C slave mode (ENSL = 1)
Address Access and conditions
0x00 Changes possible, no restrictions
0x01 Changes possible (wrong entries for CFGIBN can
limit functions)
0x02 Bit 7 = 0 (NTRI): changes to bits (6:0) permitted
A change of operating mode follows only on writing
Bit 7 = 1 (NTRI); when doing so changes to bits (6:0)
are not permitted.
0x03-0x16 Changes possible, no restrictions
0x17 Bit 3 = 1 (ENSL):
changes to bits (7:4) and (2:0) permitted
0x18 Changes possible, no restrictions
0x19-0x1A Not available
0x1B-0x1E Changes possible, no restrictions
others No changes permitted

Table 13: RAM Write Access

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BIAS SOURCE AND TEMPERATURE SENSOR

Bias Source Calibration Example: VTs(T1 ) is approx. 650 mV, measured from
The calibration of the bias current source in operation VDDS versus PS, with T1 = 25 °C;
mode Calibration 1 (Tab. 16) is prerequisite for ad-
herence to the given electrical characteristics and also The necessary activation threshold voltage VTth(T1 ) is
instrumental in the determination of the chip timing (e.g. then calculated. The required warning temperature T2 ,
SCL clock frequency). For setup purposes the IBN temperature coefficients TCs and TCth (see Electrical
value is measured using a 10 kΩ resistor by pin VDDS Characteristics, Section E) and measurement value
connected to pin NC. The setpoint is 200 µA which is VTs(T1 ) are entered into this calculation:
equivalent to a measurement voltage of 2 V.

VTs(T1 ) + TCs · (T2 − T1 )

Note: The measurement delivers a false reading VTth(T1 ) =
1 + TCth · (T2 − T1 )
when outputs are tristate (due to a configuration error
after cycling power, for instance).
Example: For T2 = T1 + 100 K, VTth(T1 ) must be pro-
grammed to 443 mV.
CFGIBN Adr 0x01, bit 7:4
31 31
Code k IBN ∼ 39−k
Code k IBN ∼ 39−k Activation threshold voltage VTth(T1 ) is provided for a
0x0 79 % 0x8 100 % high impedance measurement (10 MΩ) at output pin
0x1 81 % 0x9 103 % NS (measurement versus VDDS) and must be set by
0x2 84 % 0xA 107 % programming CFGTA(3:0) to the calculated value.
0x3 86 % 0xB 111 %
0x4 88 % 0xC 115 % Example: Altering VTth(T1 ) from 310 mV (measured
0x5 91 % 0xD 119 % with CFGTA(3:0)= 0x0) to 443 mV is equivalent to
0x6 94 % 0xE 124 % 143 %, the closest value for CFGTA is 0x9;
0x7 97 % 0xF 129 %
CFGTA Adr 0x01, bit 3:0
Table 14: Bias Current Source Calibration Code k VTth ∼ 65+3.25k
65
Code k VTth ∼ 65+3.25k
65
0x0 100 % 0x8 140 %
0x1 105 % 0x9 145 %
Temperature Sensor 0x2 110 % 0xA 150 %
The temperature monitor is calibrated in operating 0x3 115 % 0xB 155 %
mode Calibration Mode 3. 0x4 120 % 0xC 160 %
0x5 125 % 0xD 165 %
To set the required warning temperature T2 the tem- 0x6 130 % 0xE 170 %
perature sensor voltage VTs at which the warning is 0x7 135 % 0xF 175 %
generated is first determined. To this end a voltage Notes With CFGTA = 0xF Toff is 80 °C typ.,
ramp from VDDS towards GNDS is applied to pin PS with CFGTA = 0x0 Toff is 155 °C typ.
until pin ERR triggers an error message (for EMASKA =
0x20 and EMTD = 0x00). Table 15: Calibration of Temperature Monitoring
 iC-MSBSAFETY, iC-MSB2
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OPERATING MODES

In order to calibrate iC-MSB, compensate for the input various operating modes; the line drivers and protection
signals and test iC-MSB the mode of operation must be against reverse polarity facility are only active in normal
changed. The output function changes according to the mode.

MODE(3:0) Addr. 0x02; bit 3:0

BYP Addr. 0x0D; bit 5
Code Operating Mode Pin PS Pin NS Pin PC Pin NC Pin PZ Pin NZ Pin ERR
0x00 Normal operation PS NS PC NC PZ NZ ERR
0x01 Calibration 1 TANA0(2) VREFI0 VREFI12 IBN PZI NZI ERR
0x02 Calibration 2, BYP = 0 PCH1 NCH1 PCH2 NCH2 VDC1 VDC2 —
Calibration 2, BYP = 1* X4 X6 X3 X5 X1 X2
0x03 iC-Haus Test 1 VPAH VPD — CGUCK IPF V05 IERR
0x04 iC-Haus Test 2 PS_out NS_out PC_out NC_out PZ_out NZ_out IERR
0x05 iC-Haus Test 3 PS_out NS_out PC_out NC_out PZ_out NZ_out ERR
0x06 iC-Haus Test 4, BYP = 0 TANA12(0) TANA12(1) TANA12(2) TANA12(3) TANA12(4) TANA12(5) IERR
iC-Haus Test 4, BYP = 1* X4 X6 X3 X5 X1 X2
0x07 Calibration 3 VTs VTth — — — — ERR
0x08 Saturation low SCL, SDA and ERR low
0x09 — — — — — — — —
0x0A iC-Haus Test 5 TP CLK6 — — — — —
0x0B — — — — — — — —
0x0C — — — — — — — —
0x0D — — — — — — — —
0x0E IDDQ-Test All PU/PD resistors, oscillator and supply voltage deactivated
0x0F — — — — — — — —
Notes Analog calibration signals are output via approx. 5 kΩ source impedance (see Elec. Char. No.508).
For accuracy of calibration the signal frequency should not exceed 2 kHz (see Elec. Char. No.509).
* Bypass function: inputs (without voltage divider) to outputs, approx. 7 kΩ source impedance (see Elec. Char. No.510).

Table 16: Selection of Operating Modes

Calibration Op. Modes Signal Filter
In Calibration Mode 1 the user can measure the BIAS iC-MSB has a noise limiting signal filter to filter the con-
current (IBN), input amplifier reference potential VREFI ditioned analog signals. This can be activated using
and the analog signals from channel 0 following signal ENF.
conditioning (PCH0 and NCH0).
In Calibration Mode 2 the conditioned signals from ENF Adr 0x0E, bit 7
channels 1 and 2 are output (PCH1, NCH1, PCH2 Code Function
and NCH2). In addition the intermediate potentials of 0 Noise limiter deactivated
the compensating circuits are also available for CH1 1 Noise limiter activated
(VDC1) and CH2 (VDC2).
In Calibration Mode 3 the internal temperature monitor- Table 17: Signal Filtering
ing signals are provided.

Special Device Test Functions

IDDQ-Test, Saturation Low, Saturation High, and Test
1 to 5 are test modes for iC-Haus device tests. With
an activated bypass (BYP = 1), mode iC-Haus Test 4
permits the direct feedthrough of X1 - X6 input signals
to the output pins; in this instance the output impedance
is high-ohmic. Furthermore, if the input voltage divider
is selected (by RINx = 1- -1), it reduces the signal ampli-
tudes to approx. 7/8.
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TEST MODE

iC-MSB switches to test mode if a voltage larger TMODE Addr 0x15, bit 7:6
than VTMon is applied to pin ERR (precondition: Code Function during test Function following test
TMODE(0) = 1). In response iC-MSB transmits its con- mode mode
figuration settings as current-modulated data using I/O 00 Normal operation Normal operation
pin ERR either directly from the RAM (for TMEM = 1) 01 TMEM = 0: Repeated read out of
Transmission of EEPROM
or after re-reading the EEPROM (for TMEM = 0). If the EEPROM data (MODE = 0: 0x00-0x7F)
voltage at pin ERR falls below VTMoff, test mode is 0x1B-0x7F: (MODE > 0: 0x00-0x21)
terminated and data transmission aborted. OEM data (4 bytes) and
registered errors
The clock rate for the data output is determined by TMEM = 1:
Transmission of
ENFAST. Two clock rates can be selected: 780 ns for RAM data 0x3B-0x43:
ENFAST = 1 or 3.125 µs for ENFAST = 0 (see Electri- OEM data (4 bytes) and
cal Characteristics, D08, for clock frequency and toler- current errors
ances). 10 Normal operation Repeated read out of
EEPROM
(MODE = 0: 0x00-0x7F)
Data is output in Manchester code via two clock pulses (MODE > 0: 0x00-0x21)
per bit. To this end the lowside current source switches 11 Transmission of Repeated read out of
between a Z state (OFF = 0 mA) and an L state (ON = EEPROM data EEPROM
2 mA). (0x00-0x7F) (0x00-0x7F)

The bit information lies in the direction of the current Table 18: Test Mode Functions
source switch:
Zero bit: change of state Z → L (OFF to ON) TMEM Addr 0x18, bit 7
One bit: Change of state L → Z (ON to OFF) Code Memory selection
0 EEPROM
1 iC-MSB RAM (ENSL = 1)
Transmission consists of a start bit (a one bit), 8 data
bits and a pause interval in Z state (the timing is identi- Table 19: Test Mode Memory Selection
cal with an EEPROM access via the I2 C interface).
VP
U23-B
VP
VP LM393

Example: byte value = 1000 1010

7 8
C21
100nF
VP C22
U22-S 100nF
VP
U23-S
6
- 7

Transmission including the start bit: 1 1000 1010

AD8029 LM393 5
VN GND +
4 4

In Manchester code: LZ LZZL ZLZL LZZL LZZL

JP4 R24
ERR
470
M22 max. 5V
IRLML6401 VP C24 VDD
R26

Decoding of the data stream:

100pF
100k
R23
R28 2K C26
51k U22-A U23-A 100nF
LM393 R25
D21
2
- 2k

ZZZZZZ LZ LZ ZL ZL ZL LZ ZL LZ ZL ZZZZZZ -
DATA_ON M21 LL4148 6 2
2N7002 AD8029
3 1
+ NDIS 3
DATA_OUT
8 +
Pause 1 1 0 0 0 1 0 1 0 Pause R27
100k
R21
475k
5
8
U21
LM285
VP

C25
R22 100nF
4
365k

If test mode is quit with TMODE = 0x00, iC-MSB contin- VDD

ues operation without any interruption. C23

100nF

If test mode is quit with TMODE > 0x00, then iC-MSB

dra_mq1d_error_schem

again reads out its configuration from the EEPROM ac- Figure 2: Example circuit for the decoding and con-
cessible at the device ID filed to DEVID(6:0) of address version of the current-modulated signals to
0x00. logic levels.
In TMODE = 0x03 the EEPROM is read completely; in
all other cases only the address range 0x00 to 0x21 is
read to keep the configuration time for device testing
short.
 iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER

Rev F4, Page 23/35

PGA INPUTS CONFIGURATION

All input stages are configured as instrumentation am- INMODE Adr 0x03, bit 2
plifiers and thus directly suitable for differential input Code Function
signals. Referenced input signals can be processed as 0 Differential input signals
an option; in this mode input X2 acts as a reference. 1 Single-ended input signals *
Both current and voltage signals can be processed as Note * Input X2 is reference for all inputs.
input signals, selected using RIN12(0) and RIN0(0).
Table 20: Input Signal Mode

PXi GF
VP1

0.5 V PCHx
0.25 V
OR x OF x GR
0.05 x V(ACO)
NCHx
VDC RIN12 Adr 0x0E, bit 3:0
NXi RIN0 Adr 0x13, bit 3:0
GF
VN1 VPAH
INMODE Code Nominal Rin() Intern Rui() I/V Mode
VDCx
X2
k –000 1.7 kΩ 1.6 kΩ current input
VREFin
VREFI
BIASEX –010 2.5 kΩ 2.3 kΩ current input
–100 3.5 kΩ 3.2 kΩ current input
–110 4.9 kΩ 4.6 kΩ current input
Figure 3: Signal conditioning input circuit.
1—1 20 kΩ 5 kΩ voltage input 4:1*
0—1 high 1 MΩ voltage input 1:1
impedance

Current Signals Notes RIN0 must be set as RIN12 when using INMODE = 1
for single-ended input signals.
In I Mode an input resistor Rin() becomes active at each *) Refer to [Link]. No. 101 for permissible input
input pin, converting the current signal into a voltage voltage range.
signal. Input resistance Rin() consists of a pad wiring VREFin is the voltage divider’s footpoint; input
currents may be positive or negative (Vin > VREFin,
resistor and resistor Rui() which is linked to the ad-
or Vin < VREFin).
justable bias voltage source VREFin(). The following ta-
ble shows the possible selections, with Rin() giving the Table 21: I/V Mode and Input Resistance
typical resulting input resistance (see Electrical Char-
acteristics for tolerances). The input resistor should be
set in such a way that intermediate potentials VDC1
and VDC2 lie between 125 mV and 250 mV (verifiable
in Calibration Mode 2).

BIAS12 Adr 0x0E, bit 6

BIAS0 Adr 0x13, bit 6
Note: The input circuit is not suitable for back-to-back Code Function
photodiodes. 0 VREFI = 2.5 V
for low-side current sinks (e.g. photodiodes with
common anode at GNDS)
Note*: V(PXi) + V(NXi) < 2 x VREFin
Voltage Signals 1 VREFI = 1.5 V
In V Mode an optional voltage divider can be selected for high-side currrent-sources (e.g. photodiodes with
which reduces unacceptably large input amplitudes to common cathode at VDDS)
for voltage sources versus ground
approx. 25%. The circuitry is equivalent to the resistor for Wheatstone sensor bridges (e.g. iC-SM2)
chain in I Mode; the pad wiring resistor is considerably for voltage sources with low-side reference
larger here, however. (e.g. iC-LSHB, when using BIASEX = 11)
Note*: V(PXi) + V(NXi) > 2 x VREFin
Notes *) Relevant if using
- offset references VDC1/VDC2 (see Table 36)
For sensors whose offset calibration is to be propor- - the input voltage divider (see Table 21)
tional to an external DC voltage source the reference - sum control mode (see Table 47)
source can be selected using BIASEX; for all other
sensors BIASEX should be set to ’00’. Table 22: Reference Voltage
iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER

Rev F4, Page 24/35

BIASEX Adr 0x0D, bit 7:6

Code VREFin Pin function of X2
00* internal Input Index- (negative zero signal)
10 internal Output of VREFin12*
11 external Input for external reference**:
V(X2) replaces VREFI
Notes *) Do not load, buffering recommended
**) See Elec. Char. Nos. 205 and 206

Table 23: Input Reference Selection

5V

VDDS= 4.25 V VDDS= 4.25 V

4V VCM 3.75 V

3V 2.75 V
+IN
VCM 2.625 V VCM
+IN
2V -IN
-IN
VIN 250 mV max. VIN 1 V max.
VCM 1.125 V
1V VCM 0.75 V
1V
GNDS 0.25 V

V-Mode 1:1 V-Mode 4:1

VREFin 1.5 V or 2.5 V VREFin 1.5 V

NB: VREFin is referenced to GNDS.

Figure 4: Permissible common mode range and maximum input signal for lowest gain (GR12 = 0x0,
GF1, GF2 = 0x00); left side: voltage input 1:1, right side: voltage input 4:1.

5V
VDDS= 4.25 V VDDS= 4.25 V

4V
VCM 3.75 V VCM 3.75 V VCM 3.75 V

VIN 1 V max.
3V 2.75 V
+IN
VCM
VCM 2.25 V VCM 2.25 V
-IN
2V
1.75 V VCM 1.75 V

1V
1V VCM 0.75 V VCM 0.75 V
GNDS 0.25 V

V-Mode 4:1 V-Mode 4:1 V-Mode 4:1 V-Mode 4:1

VREFex 0.5 V VREFex 0.75 V VREFex 1.5 V VREFex 2.5 V
(BIASEX = 11) (BIASEX = 11) (BIASEX = 11) (BIASEX = 11)
- or - - or -
VREFin 1.5 V VREFin 2.5 V
NB: VREFex and VREFin are referenced to GNDS.

Figure 5: Permissible common mode range for voltage input 4:1 in dependancy to the reference voltage.
 iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER

Rev F4, Page 25/35

SIGNAL PATH MULTIPLEXING: iC-MSBSAFETY

Figure 6: Multiplexer Schematics

The signals for index channel CH0 are connected up to EAZ permits the activation of an analog comparator for
pins X1 and X2. Pins X3 to X6 are allocated to internal index channel CH0.
channels CH1 and CH2 via MUXIN. INMODE can be
activated for referenced input signals; this then selects INVZ Adr 0x03, bit 3
X2 as the reference input. For output purposes INVZ Code PZ_out NZ_out
allows the index signal phase to be inverted. 0 PCH0o NCH0o
1 NCH0o PCH0o
MUXIN 0x03, bit 1:0
Code PCH1i NCH1i PCH2i NCH2i Table 27: Index Signal Inversion
00 X4 X6 X3 X5
01 X4 X6 X5 X5
10 X4 X5 X3 X6
11 X4 X3 X5 X6

Table 24: Input Multiplexer for INMODE = 0

MUXIN 0x03, bit 1:0

Code PCH1i NCH1i PCH2i NCH2i
-0 X4 X2 X3 X2
-1 X4 X2 X5 X2

Table 25: Input Multiplexer for INMODE = 1

EAZ Adr 0x03, bit 7

Code Function
0 Comparator bypass
1 Comparator active

Table 26: Index Comparator Enable

 iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER

Rev F4, Page 26/35

( not for safety applications )

EXTENDED SIGNAL PATH MULTIPLEXING: iC-MSB2

Figure 7: Multiplexer Schematics

The signals for index channel CH0 are connected up to EAZ permits the activation of an analog comparator for
pins X1 and X2. Pins X3 to X6 are allocated to internal index channel CH0.
channels CH1 and CH2 via MUXIN. INMODE can be
activated for referenced input signals; this then selects EAZ Adr 0x03, bit 7
X2 as the reference input. For output purposes INVZ Code Function
allows the index signal phase to be inverted. 0 Comparator bypass
1 Comparator active
MUXIN 0x03, bit 1:0
Code PCH1i NCH1i PCH2i NCH2i Table 31: Index Comparator Enable
00 X4 X6 X3 X5
01 X4 X6 X5 X5 MUXOUT Adr 0x03, bit 6:4
10 X4 X5 X3 X6 Code PS_Out NS_Out PC_Out NC_Out
11 X4 X3 X5 X6 000 Channel 1 Channel 2
010 Channel 1 Channel 2 inverted
Table 28: Input Multiplexer for INMODE = 0 100 Channel 1 inverted Channel 2
110 Channel 1 inverted Channel 2 inverted
MUXIN 0x03, bit 1:0 001 Channel 2 Channel 1
Code PCH1i NCH1i PCH2i NCH2i 011 Channel 2 Channel 1 inverted
-0 X4 X2 X3 X2 101 Channel 2 inverted Channel 1
-1 X4 X2 X5 X2 111 Channel 2 inverted Channel 1 inverted

Table 29: Input Multiplexer for INMODE = 1 Table 32: Output Multiplexer

INVZ Adr 0x03, bit 3

Code PZ_out NZ_out
0 PCH0o NCH0o
1 NCH0o PCH0o

Table 30: Index Signal Inversion

 iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER

Rev F4, Page 27/35

SIGNAL CONDITIONING CH1, CH2

The voltage signals necessary for the conditioning of GR12 Adr 0x04, bit 2:0
channels 1 and 2 can be measured in operation mode Code Factor
Calibration 2. 0x0 2.0
0x1 4.1
Gain Settings CH1, CH2 0x2 5.3
The gain is set in four stages: 0x3 6.7
0x4 8.7
1. The sensor supply tracking is shut down and the con- 0x5 10.5
stant current source for the ACO output set to a suitable 0x6 13.2
output current (register ADJ; current value close to the 0x7 16.0
later operating point). Notes The effective total gain calculates as:
G12eff = GFx x GR12, respectively
G12eff = 1/4 x GFx x GR12
2. The coarse gain is selected so that the differential if using the input voltage divider (RIN12 = 0x9).
signal amplitudes of approx. 1 Vpp are produced (signal
Px vs. Nx, see Figure below). Table 33: Gain Range CH1, CH2

3. Using fine gain factor GF2 the CH2 signal amplitude GF2 Adr 0x04, bit 7:3
is then adjusted to 1 Vpp. Code Factor
0x00 1.00
4. The CH1 signal amplitude can then be adjusted to
0x01 1.06
the CH2 signal amplitude via fine gain factor GF1. GF2
... 6.25 31

0x1F 6.25

Table 34: Fine Gain Factor CH2

GF1 Adr 0x06, bit 2:0, Adr 0x05, bit 7:0

Code Factor
0x000 1.0
0x001 1.0009
GF1
... 6.25 1984
0x7FF 6.6245

Table 35: Fine Gain Factor CH1

Figure 8: Definition of 1 Vpp signal. Termination R0

must be high-ohmic during all Test and
Calibration modes.
 iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER

Rev F4, Page 28/35

Offset Calibration CH1, CH2 The calibration range for the CH1/CH2 offset is depen-
In order to calibrate the offset the reference source dent on the selected VOS12 source and is set using
must first be selected using VOS12. Two fixed voltages OR1 and OR2. Both sine and cosine signals are then
and two dependent sources are available for this pur- calibrated using factors OF1 and OF2. The calibration
pose. The fixed voltage sources should be selected for target is reached when the DC fraction of the differential
external sensors which provide stable, self-regulating signals PCHx versus NCHx is zero.
signals.
OR1 Adr 0x09, bit 0; Adr 0x08, bit 7
So that photosensors can be operated in optical en- OR2 Adr 0x0A, bit 5:4
coders iC-MSB tracks changes in offset voltages via Code Range
the signal-dependent source VDC when used in con- 0x0 x1
junction with the controlled sensor current source for 0x1 x2
LED supply (pin ACO). The VDC potential automatically 0x2 x6
tracks higher DC photocurrents. To this end intermedi- 0x3 x12
ate potentials VDC1 and VDC2 must be adjusted to a
minimal AC ripple using the selectable k factor. Table 38: Offset Range CH1, CH2

The feedback of pin voltage V(ACO) fulfills the same OF1 Adr 0xA, bit 3:0; Adr 0x9, bit 7:1
task as source VDC when MR bridge sensors are sup- OF2 Adr 0xC, bit 0; Adr 0xB, bit 7:0; Adr 0xA, bit 7:6
plied by the controlled current source or by supply Code Factor Code Factor
VDDS. 0x000 0 0x400 0
0x001 0.00098 0x401 − 0.00098
VOS12 Adr 0x0E, bit 5:4 ... + Code / 1023 ... − (Code - 1024)
Code Type of source / 1023
0x0 Feedback of ACO pin voltage: V(ACO)/20 0x3FF 1 0x7FF −1
for sensor supply-dependent diff. voltage signals
for Wheatstone sensor bridges Table 39: Offset Factors CH1, CH2
to measure VDDS
0x1, 0x2 Fixed reference: V05 of 500 mV, V025 of 250 mV
for single-ended current or voltage signals Phase Correction CH1 vs. CH2
for single-ended or differential stabilized signals
The phase shift between CH1 and CH2 can be adjusted
(regulated sensor or waveform generator)
using parameter PH12. Following phase calibration
0x3 Self-tracking sources VDC1, VDC2 (125...250 mV)
for differential current signals other calibration parameters may have to be adjusted
for differential voltage signals* again (those as amplitude compensation, intermediate
Notes *) Requires BIASEX = 11 and the sensor’s reference potentials and offset voltages).
level connected to input X2 (see Elec. Char. No.
205 for acceptable input voltage). PH12 Adr 0xD, bit 2:0; Adr 0xC, bit 7:1
Code Correction angle Code Correction angle
Table 36: Offset Reference Source CH1, CH2
0x000 0° 0x200 0°
0x001 + 0.0204 ° 0x201 − 0.0204 °
VDC1 Adr 0x07, bit 4:0; Adr 0x06, bit 7:3 ... + 10.42 ° · ... − 10.42 ° ·
VDC2 Adr 0x08, bit 6:0; Adr 0x07, bit 7:5 PH12 /511 (PH12 - 512) /511
Code VDCi = (1 − k) · VPi + k · VNi 0x1FF + 10.42 ° 0x3FF − 10.42 °
0x000 k = 1/3
0x001 k = 0.3337 Table 40: Phase Correction CH1 vs. CH2
... k = 1/3 + 1/3 · Code/1023
0x200 k = 0.5000 (center setting)
... ...
0x3FF k = 2/3
Notes Adjustment is required only if VOS12 = 0x3

Table 37: Intermediate Voltages CH1, CH2

 iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER

Rev F4, Page 29/35

SIGNAL CONDITIONING CH0

The voltage signals needed to calibrate channel 0 are GF0 Adr 0x11, bit 7:3
available in Calibration Mode 1. Code Factor
0x00 1.00
0x01 1.06
GFZ
... 6.25 31
Gain Settings CH0
0x1F 6.25
Parallel to the conditioning process for the CH1 and
CH2 signals the CH0 gain is set in the following stages:
Table 42: Fine Gain Factor CH0

Offset Calibration CH0

1. The sensor supply tracking unit is shut down and the
To calibrate the offset the source of supply must first
constant current source for the ACO output set to the
be selected using VOS0 (see Offset Calibration CH1
same output current as in the compensation of CH1
and CH2 for further information). For the CH0 path the
and CH2 (register ADJ; current value close to the later
dependent source VDC is identical to source VDC1.
operating point).
VOS0 Adr 0x13, bit 5:4
Code Source
2. The coarse gain is selected so that a differential sig- 0x0 0.05 · V(ACO)
nal amplitude of approx. 1 Vpp is produced internally 0x1 0.5 V
(signal PCHx versus NCHx). 0x2 0.25 V
0x3 VDC (ie. VDC1)

Table 43: Offset Reference Source CH0

3. GF0 then permits fine gain adjustment to 1 Vpp.

OR0 Adr 0x12, bit 1:0

Code Range
GR0 Adr 0x11, bit 2:0
0x0 x1
Code Factor
0x1 x2
0x0 2.0 0x2 x6
0x1 4.1 0x3 x12
0x2 5.3
0x3 6.7 Table 44: Offset Range CH0
0x4 8.7
0x5 10.5
OF0 Adr 0x12, bit 7:2
0x6 13.2
Code Factor Code Factor
0x7 16.0
0x00 0 0x20 0
Notes The effective total gain calculates as:
0x01 + 0.0322 0x21 − 0.0322
G0eff = GF0 x GR0, respectively
G0eff = 1/4 x GF0 x GR0 ... + OF0 /31 ... − (OF0 - 32 ) /31
if using the input voltage divider (RIN0 = 0x9). 0x1F +1 0x3F −1

Table 41: Gain Range CH0 Table 45: Offset Factor CH0
 iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER

Rev F4, Page 30/35

SIGNAL LEVEL CONTROL and SIGNAL MONITORING

Via the controlled sensor current source (pin ACO)

iC-MSB can keep the output signals for the ensuing
sine/digital converter constant regardless of tempera-
ture and aging effects by tracking the sensor supply.

Both the controller operating range and input signal

amplitude for the controller are monitored and can be
enabled for error messaging. A constant current source
can be selected for the ACO output when setting the
signal conditioning; the current range for the highside
current source is adjusted using ADJ(6:5).

ADJ (6:5) Adr 0x10, bit 5:4

Code Function Figure 9: Internal signal monitoring and test sig-
00 5 mA - Range nals in Calibration 2 mode (example for
01 10 mA - Range ADJ(8:0) = 0x19);
10 25 mA - Range
11 50 mA - Range Signal monitoring and limits
ADJ (4:0) Vt()min ... max ADJ (4:0) Vt()min ... max
Table 46: ACO Output Current Range (applies for con-
0x00 120 mV...390 mV 0x19 200 mV ...650 mV
trol modes and constant current source)
0x01 122 mV...397 mV ... ...
... ... 0x1F 240 mV...780 mV
ADJ (8:7) Adr 0x10, bit 7:6 Notes All values nominal, see also Elec. Char. Nos. 607,
Code Function 608
00 Sine/cosine square control
01 Sum control Table 49: Signal Monitoring
10 Constant current source
11 Not permitted (device test only) The signal monitoring limits are tracked according to
ADJ (4:0) and fit for square control mode. When using
Table 47: ACO Output Control Mode sum control mode a different operating point can be
required for which the monitoring limits may not be suit-
Note: Excessive input signals or internal signal clipping able. In this case signal monitoring should be disabled
can interfere control operation, so that the preset operating via the error mask (see EMASKA etc.).
point may not be reached (upon power up) or maintained
(upon disturbances). Use Control Error 2 and Signal Error 1 ADJ (4:0) Adr 0x10, bit 3:0; Adr 0x0F, bit 7
for monitoring and configure EMASKA accordingly. Code Sum control ADJ(8:7) = 01
0x00 VDC1 + VDC2 approx. 245 mV
ADJ (4:0) Adr 0x10, bit 3:0; Adr 0x0F, bit 7 0x01 VDC1 + VDC2 approx. 249 mV
77
Code Square control ADJ(8:7) = 00 ... ... ≈ 245mV 77−(1.25∗Code)
0x00 Vpp() approx. 300 mV (60 %) 0x1F VDC1 + VDC2 approx. 490 mV
0x01 Vpp() approx. 305 mV (61 %)
... ... 77
≈ 300 mV 77−(1.25∗Code) Table 50: Setpoint Sum Control (DC value)
0x19 Vpp() approx. 500 mV (101 %)
... ... ADJ (4:0) Adr 0x10, bit 3:0; Adr 0x0F, bit 7
0x1F Vpp() approx. 600 mV (120 %) Code Constant current source ADJ(8:7) = 10
0x00 I(ACO) approx. 3.125% Isc(ACO)
Table 48: Setpoint Square Control (internal sin/cos sig- 0x01 I(ACO) approx. 6.25% Isc(ACO)
nal amplitude) ... ... ≈ 3.125% ∗ (Code + 1) ∗ Isc(ACO)
0x1F I(ACO) approx. 100% Isc(ACO)
In operation with the active square control mode Notes See Elec. Char. No. 602 for Isc(ACO)
ADJ(4:0) sets the internal signal amplitudes accord-
ing to the relation (PCH1-NCH1)2 + (PCH2-NCH2)2 ; Table 51: Setpoint Current Source (ACO output cur-
these should be set to 0.25 Vpk. rent)
 iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER

Rev F4, Page 31/35

MONITORING AND ERROR OUTPUT

The following table gives the errors which can both be figured by EPH, and the minimum indication time by
recognized by iC-MSB and enabled either for messag- EMTD.
ing, output shutdown or protocol in the EEPROM.

Mask EMASKA stipulates that errors should be signaled Pin ERR also acts as an input for error messages of
at pin ERR, mask EMASKO determines whether the the external system. This function requires EPH = 0
line drivers are to be shutdown or not (with PDMODE and an external error being low active. Pin ERR can
defining reactivation) and mask EMASKE governs the also switch iC-MSB to test mode, for which a voltage of
storage of error events in the EEPROM. larger than VTMon must be applied (see page 22).

EMASKA Addr 0x14, bit 6:0

EPH Addr 0x15, bit 2
EMASKO Addr 0x16, bit 6:0
Code State with error State w/o error
EMASKE Addr 0x18, bit 2:0; Adr 0x17, bit 7:4
0* active low high impedance
Bit Error Event (evaluation of low active
6* Configuration error external system error)
(SDA or SCL pin error, no acknowledge signal from 1 high impedance active low
EEPROM or invalid check sum); (or optional pull-up)
5 Excessive temperature warning Note *) Pin ERR is disabled during driver shutdown and
4 External system error cannot indicate errors in this case.
3 Control error 2: range at max. limit
2 Control error 1: range at min. limit Table 53: I/O Logic, Alarm Output ERR
1 Signal error 2: clipping
0 Signal error 1: loss of signal
(wrong s/c phase, poor differential amplitude, may EMTD Addr 0x15, bit 5:3
also result from excessive input signals or internal
Code Indication Time Code Indication Time
signal clipping)
0x0 0 ms 0x4 50 ms
EMASKA Error Mask Alarm Output ERR
0x1 12.5 ms 0x5 62.5 ms
1 Enable: event changes state of pin ERR
(if EMASKO does not disable the output function). 0x2 25 ms 0x6 75 ms
0 Disable: event does not affect pin ERR. 0x3 37.5 ms 0x7 87.5 ms
*Note EMASKA(6): Pin ERR can not pull low on config.
error. Use EPH = 1 for high-active error logic. Table 54: Min. Indication Time, Alarm Output ERR
EMASKO Error Mask Driver Shutdown
1 Enable: event resets pin ACO to the 5 mA range,
tristates the line driver outputs and pin ERR (i.e. EPU Addr 0x17, bit 2
low-active error messages can not be displayed) Code Function
0 Disable: output functions remain active 0 No internal pull-up
*Note EMASKO(6) = 1 (ROM bit): The line drivers remain 1 Internal 300 µA pull-up current source active
high impedance (tristate) when cycling power.

Program EMASKO(6) = 0 to EEPROM. Table 55: Pull-Up Enable, Alarm Output ERR
This allows to reactivate disabled output drivers by
toggling bit NTRI (set zero, then one). If set 1, the
driver shutdown persists and can not be resolved.
Excessive Temperature Warning
EMASKE Error Mask EEPROM Savings
Exceeding the temperature warning threshold Tw (cor-
1 Enable: event will be latched
responds to T2 , refer to Tempeprature Sensor, page
0 Disable: event will not be latched
20) can be signaled at pin ERR or used to shut down
*Note Program EMASKE(6) = 0 to EEPROM.
This avoids conflicts with I2 C programming adapters the line drivers (via mask EMASKO). The temperature
which are not multi-master capable. warning is cleared when the temperature falls below
Tw - Thys .
Table 52: Error Masking

Error Input/Output: pin ERR Note: If the temperature shutdown threshold Toff =
Pin ERR is operated by a current-limited open-drain Tw + ∆ T is exceeded, the line drivers are shut down
output driver and has an internal pull-up which can be independently of EMASKO. For ∆ T refer to Elec.
disabled. The output logic (low or high active) is con- Char. E06.
 iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER

Rev F4, Page 32/35

Analog Output Drivers Shutdown an error has occurred can be recorded, with no infor-
mation as to the time and count of appearance of that
error given. Error recording can be used to statistically
PDMODE Addr 0x18, bit 6 evaluate the causes of system failure, for example.
Code Function
0 Driver shutdown terminates with the error event ERR1 Addr 0x20, bit 6:0
1 Permanent driver shutdown until cycling power ERR2 Addr 0x22, bit 0; Adr 0x21, bit 7:2
ERR3 Addr 0x23, bit 2:0; Adr 0x22, bit 7:4
Table 56: Driver Activation Bit Error Event
9:0 Assignation according to EMASKE
Error Protocol
Out of the errors enabled by EMASKE both the first Code Function
error (under ERR1) and last error (under ERR2) which 0 No event
occur after the iC-MSB is powered up are stored in the 1 Registered error event
EEPROM.
Table 57: Error Protocol
The EEPROM also has a memory area in which all oc-
curring errors can be stored (ERR3). Only the fact that

ANALOG OUTPUT DRIVERS

+250 mVpk -250 mVpk

iC-MSB outputs differential 1 Vpp signals with approx.
2.5 V in offset onto the transmission cable, which is ter-
VPAH= VDD/2 VPAH minated with 100 Ω or 120 Ω at the receiver end (PLC).
1 Vpp-diff.

iC-MSB The output drivers are shut down (tristated) in case

Px of excessive temperature (see page 31), or when re-
verse polarity is detected (see section Reverse Polarity
V(Px)

Nx
Vout
Protection, page 32).
V(Nx) RL()= 100...120 Ω
Using EMASKO for error masking, further events can
GND
be selected to shut down the output drivers (see Table
52). Using PDMODE, the duration of a shutdown can
Figure 10: Output amplitude and offset according to be prolonged until power was cycled (see Table 56).
Elec. Char. 502 and 503.
If there is no EEPROM or no valid configuration pro-
vided on power up, the output drivers will not be en-
abled.

REVERSE POLARITY PROTECTION

The analog output drivers of iC-MSB are protected Reverse polarity is permanently monitored and de-
against reverse polarity and short-circuiting. A defective tected if the voltage at a protected pin undershoots
or wrongly connected device cable causes no damage, the ground potential at GND.
neither to iC-MSB nor to the components protected
against reverse polarity by VDDS and GNDS. If the state of reverse polarity is resolved, iC-MSB
reboots from the EEPROM and enables the output
drivers.
The following pins feature reverse polarity protection:
PC, NC, PS, NS, PZ, NZ, ERR, VDD, GND and ACO Note: When iC-MSB is linked to a PLC and does not
(as long as GNDS is only loaded relative to VDDS). The enable its output drivers on power up, a negative line
maximum voltage difference between these pins should potential could be the root cause. Refer to Application
not exceed 6 V (8 V for pin ERR). Hints, page 33, for details and recommended counter-
measures.
 iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER

Rev F4, Page 33/35

APPLICATION HINTS

Connecting MR sensor bridges for safety-related applications

For safety-related applications iC-MSBSAFETY requires an external overvoltage protection of supply VDD (Zener
diode with fuse, for instance) and external pull-down resistors at the inputs X3 to X6 towards GNDS (of up to
100 kΩ).

F1
+5V
C1
100nF C2
R5 R6 100nF
2.2kΩ 2.2kΩ D1
VP VDDS VDD
SCL 5.6V
SCL
24xx SDA
I2C ERR
ERR
VN
SDA
iC-MSB
ACO
SIGNAL
LEVEL
PZ
CONTROL
RL
MR0 100Ω
X1
+ NZ

X2
-
INPUT ZERO PC
MR1
X3 RL
+ 100Ω
NC
X5

R1 R2
-
100kΩ 100kΩ INPUT COS
PS
MR2
X4
+ RL
X6
100Ω

R3 R4
- NS

100kΩ 100kΩ INPUT SIN

GNDS GND

0V

TVS diode array

Figure 11: Example circuit for safety-related applications with iC-MSBSAFETY .

PLC Operation the supply VDD nor the output pins, which are also mon-
There are PLCs with a remote sense supply which re- itored, must fall to below ground potential (pin GND);
quire longer for the voltage regulation to settle. At the otherwise the device is not configured and the outputs
same time the PLC inputs can have high-impedance remain permanently set to tristate.
resistances versus an internal, negative supply voltage
which define the input potential for open inputs.
Note: In order to ensure that iC-MSB starts with the
In this instance iC-MSB’s reverse polarity protection fea- PLCs mentioned above pull-up resistors can be used
ture can be activated as the outputs are tristate during in the encoder. Values of 100 kΩ are usually sufficient;
the start phase and the resistances in the PLC deter- it is, however, recommended that PLC specifications
mine the pin potential. During the start phase neither be specifically referred to here.
 iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER

Rev F4, Page 34/35

REVISION HISTORY

Rel. Rel. Date* Chapter Modification Page

F2 2016-09-29 Various Introduction of QFN32-5x5 package 1, 5-7,
32
REGISTER MAP Addr 0x14 to 0x18: Mandatory programming of undescribed bits; 15
Footnote on mandatory programming of specific parameters
SERIAL CONFIGURATION EEPROM device address, note on I2 C in-circuit programming 17
INTERFACE (EEPROM)
INPUT CONFIGURATION Figure 2 updated, Table 19: update of footnote, Table 19: update of contents 23
SIGNAL CONDITIONING CH1, Table 33: update of contents 27
CH2
SIGNAL CONDITIONING CH0 Table 41: update of contents 29
ERROR MONITORING AND Table 52, 53: update of contents 31
ALARM OUTPUT Alarm output: description improved
REVERSE POLARITY Max. voltage difference: 8 V at pin ERR 32
PROTECTION Note box added

Rel. Rel. Date* Chapter Modification Page

F3 2017-05-02 FEATURES, Operating temperature range (OTR) extended to +125 °C 1,
THERMAL DATA Introduction of OTR for SAFETY applications (Ta_safe) 8
ELECTRICAL Junction temperature range extended to +140 °C 9ff
CHARACTERISTICS Items 107, 301, 302: conditions corrected
Items 601, 602: conditions and limits updated
ORDERING INFORMATION Adaption of OTR for TSSOP20-TP, QFN32-5x5, and SAFETY applications 35

Rel. Rel. Date* Chapter Modification Page

F4 2020-08-19 BLOCK DIAGRAM Update of block diagram, adaption of section titles 1ff
DESCRIPTION Note box added 2
PACKAGING INFORMATION Pin configuration figure and footnote updated (value of bypass cap) 4
Package TSSOP20-TP: dimensions added
ELECTRICAL Item 001: conditions completed 9ff
CHARACTERISTICS Item D06: min limit changed to -650 µA
Items 503, D13 added
SERIAL I2 C INTERFACE Update of description, Figure 1 added, Table 5: note updated, Table 7 added, note and 17ff
attention boxes added;
Section EEPROM Device Selection: Table 8 added, update of description, note boxes
added;
BIAS SOURCE AND TEMP. Table 15: formula corrected 20
SENSOR CALIBRATION
ANALOG OUTPUT DRIVERS Section added 32
REVERSE POLARITY PROT. Description updated 32
ORDERING INFORMATION Listing updated 35

iC-Haus expressly reserves the right to change its products and/or specifications. A Datasheet Update Notification (DUN) gives details as to any amendments
and additions made to the relevant current specifications on our internet website [Link]/DUN and is automatically generated and shall be sent to
registered users by email.
Copying – even as an excerpt – is only permitted with iC-Haus’ approval in writing and precise reference to source.

The data specified is intended solely for the purpose of product description and shall represent the usual quality of the product. In case the specifications contain
obvious mistakes e.g. in writing or calculation, iC-Haus reserves the right to correct the specification and no liability arises insofar that the specification was from
a third party view obviously not reliable. There shall be no claims based on defects as to quality in cases of insignificant deviations from the specifications or in
case of only minor impairment of usability.
No representations or warranties, either expressed or implied, of merchantability, fitness for a particular purpose or of any other nature are made hereunder
with respect to information/specification or the products to which information refers and no guarantee with respect to compliance to the intended use is given. In
particular, this also applies to the stated possible applications or areas of applications of the product.

iC-Haus products are not designed for and must not be used in connection with any applications where the failure of such products would reasonably be
expected to result in significant personal injury or death (Safety-Critical Applications) without iC-Haus’ specific written consent. Safety-Critical Applications
include, without limitation, life support devices and systems. iC-Haus products are not designed nor intended for use in military or aerospace applications or
environments or in automotive applications unless specifically designated for such use by iC-Haus.
iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade
mark rights of a third party resulting from processing or handling of the product and/or any other use of the product.

Software and its documentation is provided by iC-Haus GmbH or contributors "AS IS" and is subject to the ZVEI General Conditions for the Supply of Products
and Services with iC-Haus amendments and the ZVEI Software clause with iC-Haus amendments ([Link]/EULA).
* Release Date format: YYYY-MM-DD
 iC-MSBSAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER

Rev F4, Page 35/35

ORDERING INFORMATION

Type Package Options Order Designation

iC-MSBSAFETY 20-pin TSSOP iC-MSB TSSOP20

RoHS compliant

20-pin TSSOP with Thermal Pad Temperature range iC-MSB TSSOP20-TP

RoHS compliant -40 °C to +125 °C*

32-pin QFN, 5 mm x 5 mm, Temperature range iC-MSB QFN32-5x5

thickness 0.9 mm, -40 °C to +125 °C*
RoHS compliant

iC-MSBSAFETY iC-MSB EVAL MSB1D

Evaluation Board

iC-MSB2 TSSOP20 iC-MSB2 TSSOP20

*) Note that for SAFETY applications, the compliant temperature range is -25 to +100 °C.

Please send your purchase orders to our order handling team:

Fax: +49 (0) 61 35 - 92 92 - 692

E-Mail: dispo@[Link]

For technical support, information about prices and terms of delivery please contact:

iC-Haus GmbH Tel.: +49 (0) 61 35 - 92 92 - 0

Am Kuemmerling 18 Fax: +49 (0) 61 35 - 92 92 - 192
D-55294 Bodenheim Web: [Link]
GERMANY E-Mail: sales@[Link]

Appointed local distributors: [Link]