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4-Bit Binary Decoder Logic Module

The document describes a Verilog module for a 4-bit binary decoder that outputs a 16-bit signal based on the input and an enable signal. It includes logic assignments for each output based on the combination of input bits and the enable signal. Additionally, a testbench is provided to simulate the decoder's functionality by incrementing the binary input and monitoring the outputs.

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chetansb2003
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6 views1 page

4-Bit Binary Decoder Logic Module

The document describes a Verilog module for a 4-bit binary decoder that outputs a 16-bit signal based on the input and an enable signal. It includes logic assignments for each output based on the combination of input bits and the enable signal. Additionally, a testbench is provided to simulate the decoder's functionality by incrementing the binary input and monitoring the outputs.

Uploaded by

chetansb2003
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd

module b8_4bit_dec_assign_logic(in,out,enable);

input enable;
input [3:0] in;
output [15:0] out;

assign out[0] = !in[0] & !in[1] & !in[2] & !in[3] & enable;
assign out[1] = in[0] & !in[1] & !in[2] & !in[3] & enable;
assign out[2] = !in[0] & in[1] & !in[2] & !in[3] & enable;
assign out[3] = in[0] & in[1] & !in[2] & !in[3] & enable;
assign out[4] = !in[0] & !in[1] & in[2] & !in[3] & enable;
assign out[5] = in[0] & !in[1] & in[2] & !in[3] & enable;
assign out[6] = !in[0] & in[1] & in[2] & !in[3] & enable;
assign out[7] = in[0] & in[1] & in[2] & !in[3] & enable;
assign out[8] = !in[0] & !in[1] & !in[2] & in[3] & enable;
assign out[9] = in[0] & !in[1] & !in[2] & in[3] & enable;
assign out[10] = !in[0] & in[1] & !in[2] & in[3] & enable;
assign out[11] = in[0] & in[1] & !in[2] & in[3] & enable;
assign out[12] = !in[0] & !in[1] & in[2] & in[3] & enable;
assign out[13] = in[0] & !in[1] & in[2] & in[3] & enable;
assign out[14] = !in[0] & in[1] & in[2] & in[3] & enable;
assign out[15] = in[0] & in[1] & in[2] & in[3] & enable;

endmodule

module testbench;
reg enable;
reg [3:0] binary;

wire [15:0] binary_out_logic;

b8_4bit_dec_assign_logic b8_4bit_dec_assign_logic(
.in(binary),
.out(binary_out_logic),
.enable(enable)
);

initial
begin
enable = 1;
binary = 0;
end

always #10 binary=binary+1;

initial
$monitor("enable=%b, binary=%b, binary_out_logic=%b",
enable, binary, binary_out_logic);

endmodule

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