Fall 2011 EE457 Instructor: Gandhi Puvvada
Final Exam (30%) Date: 12/8/2011, Thursday
Closed Book, Closed Notes Time: 8:00 - 10:45 AM SGM123
Verilog Guide and Calculators allowed Total points: 270
Name: Perfect score: 250 / 270
1 ( 9 + 4 + 2 + 9 + 25 = 49 points) min.
Pipelining, exceptions, and hardware to support implementing exceptions:
Let us implement exceptions in our late branch design (note: late branch design) as per the
following figure discussed in class. Note: We will wait until the senior-most offending instruction
reaches WB stage.
There can be several slightly differing but all correct implementations. Here we wish to
implement the following choice:
An offending instruction (the one having an exception) converts itself and its followers
juniors into a bubble. And it keeps doing the same (converting all juniors to bubbles) until
it reaches the WB stage.
The block diagram on the next page is just for your information. But on page 3, you find an
incomplete design for your to complete.
The IF_Flush, ID_Flush, and the EX_Flush due to successful branch are removed from page 3 so
that you can combine flushing due to successful branches with flushing due to exceptions.
For the sake of our simple design, let us assume that there is only a single cause for exception
from each of the first 4 stages and they are called C_IF (cause for exception for instruction fetch
stage), C_ID, C_EX, C_M respectively.
ee457_Final_Fall2011.fm December 6, 2011 11:01 pm EE457 Final Exam - Fall 2011 1 / 13
C Copyright 2011 Gandhi Puvvada
IF/ID ID/EX EX/MEM MEM/WB
IF-Stage ID-Stage EX-Stage MEM-Stage WB-Stage
ee457_Final_Fall2011.fm December 6, 2011 11:01 pm
Original (OLD) Lab 6 late branch block diagram -- Just FYI
[Link]
MemRead
Hazard
detection
unit WB
ME
[Link] ALUSrc
EX ALUOp
RegDst 0 WB
ME
0
(PC)
(PC)
+
Branch
EE457 Final Exam - Fall 2011
Control
(PC)
0
opcode
MemWrite
MemRead
RegWrite
(rs)
R1
ALU_result
r1 Shift ALU
rs
Left 2 MemtoReg
Registers Z @ WB
ALUSrc
Instruction
r2
memory
rt
MEM_data
memory
PC
w
(rt)
R2
2 / 13
Data
R
rd
Store_data
W
W
shift
rs
RegDst ALUOp
funct
ALU
REG_data
ctrl
WR
rt
C Copyright 2011 Gandhi Puvvada
[Link]
RegWrite
rd
Forwarding
WR
unit
shift
Sign
ext.
funct
Pipelined CPU (Late Branch from 1st Ed.) for the EE457 class Lab #6
3/26/2000 Original drawing provided by Prof. Dubois
ee457_Final_Fall2011.fm December 6, 2011 11:01 pm
MemRead
Hazard
detection
unit WB
0 0
ME
ALUSrc
ALUOp
1 1
EX
RegDst
0 WB 8000_0180H
ME
0
(PC)
(PC)
RegWrite
EE457 Final Exam - Fall 2011
Branch
Control
(PC)
0
opcode
0 MemtoReg
WB
0 1
RegWrite
2-input ae
M_Excp
Insert a
IF_Excp EX_Excp
Instruction
0 EPC
memory
1
DQ
PC
3 / 13
EPC
CLK
CLK
EPC
ID_Excp t
Abor EF EF EF EF Cause
0
DQ
Cause
1
Cause
Cause
Cause
0 0 0
CLK
C_IF C_ID
1 C_EX 1
C_M 1 CLK
C Copyright 2011 Gandhi Puvvada
Insert a wire
Insert a 3-input gate Insert a wire or an inverter
or an inverter
Complete this after going through the next page
9 1.1 We discussed about a potential conflict between the HDU and a successful branch.
pts In case of a conflict, the HDU should win in the ____________ (early/late) branch design.
2+5+2=9 ________________ (However/And also) in the ____________ (early/late) branch design
___________________________________________________________________________
___________________________________________________________________________.
In the design on page 2, this problem (conflict between the HDU and a successful branch in MEM
stage ______________________ (is already / is yet to be) solved.
If it is yet to be solved, fix it on page 3.
4
pts 1.1.1 Consider 5 load word instructions in the 5 stages of the design on page 3 supporting exceptions.
2+2=4 Say lw#4 is dependent on lw#3 as shown below.
IF ID EX M W
lw#5 lw#4 lw#3 lw#2 lw#1
page fault
exception
Student #1: HDU would not be disabling PC and IF/ID there by conflicting with the exception
logic’s intent to deposit 8000_0180H in the PC in order to transfer control to EHR (Exception
Handling Routine) because lw#1, when it was in MEM stage, would have flushed lw#3
(converted it to bubble) in ID stage. You __________________ (agree / disagree).
Student #2: If there is a successful branch in MEM stage (in the current design on page #3),
HDU conflicts with the successful branch.
You agree with Student #2 if there __________ (is isn’t) an instruction in the WB stage with
exception simultaneously.
2
pts 1.2 An Exception Flag (EF) is carried through the pipe to validate the cause and EPC registers.
On page 3, is EPC the PC of the offending instruction or the PC+4 ? _________________
9
pts 1.3 It is _____________________ (necessary/unnecessary) for the senior instruction with an
1+1+7=9
exception to prevent its junior instructions from carrying their active exception status into the next
stage _______________ (even though / because anyways) the junior instructions were converted
(or being converted) to bubbles. Explain with the example below.
IF ID EX M W
addi or add lw sub
illegal instr. page fault
exception exception
_____________________________________________________________________________
_____________________________________________________________________________
_____________________________________________________________________________
_____________________________________________________________________________
25
pts 1.4 Complete page-3 now. Make sure to complete all select lines on muxes. Read the bold print on page 1.
ee457_Final_Fall2011.fm December 6, 2011 11:01 pm EE457 Final Exam - Fall 2011 4 / 13
C Copyright 2011 Gandhi Puvvada