11/6/2023
RTL Design
HLSM Actions: Updates Occur Next Clock Cycle
S'
Local storage updated on clock edges only
Enter state on clock edge S3
Storage writes in that state occur on next clock edge S
Dctr := Dctr+1
Can think of as occurring on outgoing transitions
Thus, transition conditions use the OLD value, not the newly-
S' / Dctr := Dctr+1
written value
Example:
S3
S/
Dctr := Dctr+1
Inputs : B (bit)
Outputs : P (bit) // if B, 2 cycles high S0 S1 S1 S0
clk
Local storage: Jreg (8 bits)
B' B
Jreg<2
!(Jreg<2) 1 2 3
S0 S1 Jreg ? 1 2 3
B
P := '0' P := '1'
P
Jreg := 1 Jreg := Jreg + 1
(a) (b )
RTL Design
RTL Design Process
Capture behavior
Convert to circuit
Need target architecture
Datapath capable of HLSM's data operations
Controller to control datapath
External data
inputs
DP
...
External control
inputs
control
... ...
inputs
Controller Datapath
External ...
control ...
outputs DP
control ...
outputs
External data
outputs
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11/6/2023
RTL Design
RTL Design Process
Step Description
Step 1:
Capture a high-level Describe the system’s desired behavior as a high-level state
Capture
state machine machine. The state machine consists of states and transitions.
behavior
The state machine is “high-level” because the transition
conditions and the state actions are more than just Boolean
operations on single-bit inputs and outputs.
Step 2: 2A: Create Create a datapath to carry out the data operations of the high-
Convert a datapath level state machine.
to circuit
2B: Connect Connect the datapath to a controller block. Connect external
the datapath to a control inputs and outputs to the controller block.
controller
2C: Derive Convert the high-level state machine to a finite-state machine
the controller’s FSM (FSM) for the controller, by replacing data operations with setting
and reading of control signals to and from the datapath.
RTL Design
Ex: Cycles-High Counter
P = total number (in binary) of cycles that m is 1 CountHigh
m
Capture behavior as HLSM clk Preg
Preg required (multibit outputs must be registered) 32
Use to hold count P
CountHigh Inputs: m (bit) CountHigh Inputs: m (bit) CountHigh Inputs: m (bit)
Outputs: P (32 bits) Outputs: P (32 bits) Outputs: P (32 bits)
Local storage: Preg Local storage: Preg Local storage: Preg
S_Clr // Clear Preg to 0s S_Clr // Clear Preg to 0s S_Clr
// Clear Preg to 0s
Preg := 0 Preg := 0 Preg := 0
? m' // Wait for m == '1' m' // Wait for m == '1'
S_Wt S_Wt
m m' m
? // Increment Preg
m S_Inc Preg := Preg + 1
(a) (b) (c)
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11/6/2023
RTL Design CountHigh
Ctrl/DP Example for Earlier Cycles-High Counter
m 000...00001
A B
CountHigh add1
S
m
First clear Preg to 0s Preg ? 32
Then increment Preg for each Preg_clr
Create DP clr I
clock cycle that m is 1 ld Preg
Connect with Preg_ld Q
(a) P
controller DP
P 32
We created this HLSM (c)
earlier Derive controller
CountHigh Inputs : m (bit) CountHigh
Outputs : P (32 bits)
LocStr : Preg (32 bits)
m 000...00001
//Clear Preg to 0s //Preg := 0
S_Clr Preg := 0 S_Clr Preg_clr = 1 A B
Preg_ld = 0 add1
S
32
//Wait for m=='1' //Wait for m=1 Preg_clr
m' S_Wt m' Preg_clr = 0 clr I
S_Wt
Preg_ld = 0 ld Preg
m Preg_ld Q
m' m' m
DP
//Increment Preg //Preg:=Preg+1
m S_Inc m
Preg := Preg + 1 S_Inc Preg_clr = 0
Preg_ld = 1
(b) Controller
32
(d) P
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RTL Design
Example: Laser-Based Distance Measurer
T (in seconds)
B L
laser from button to laser
Laser-based
distance
sensor D 16 measurer S
to display from sensor
Inputs/outputs
B: bit input, from button, to begin measurement
L: bit output, activates laser
S: bit input, senses laser reflection
D: 16-bit output, to display computed distance
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11/6/2023
RTL Design
Example: Laser-Based Distance Measurer
DistanceMeasurer Inputs : B (bit), S (bit) Outputs : L (bit), D (16 bits) B Laser-based L
Local storage: Dreg, Dctr (16 bits) 16 distance measurer
D S
B' S'
S0 S1 S2 S3 S4
B S
L := '0' Dctr := 0 L := '1' L := '0' Dreg := Dctr/2
Dreg := 0 Dctr := Dctr+1 // calculate D
Once reflection detected (S), go to new state S4
Calculate distance
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Assuming clock frequency is 3x10 , Dctr holds number of meters, so Dreg:=Dctr/2
After S4, go back to S1 to wait for button again
RTL Design
Laser-Based Distance Measurer—Step 2A: Create a Datapath
DistanceMeasurer Inputs: B (bit), S (bit) Outputs: L (bit), D (16 bits)
Local storage: Dreg, Dctr (16 bits)
B' S'
S0 S1 S2 S3 S4
B S
L := '0' Dctr := 0 L := '1' L := '0' Dreg := Dctr/2
Dreg := 0 Dctr := Dctr+1 // calculate D
1 Datapath
16
a
A B
HLSM data I/O DP I/O Add1: add(16) 16 I
S Shr1: shiftR1(16)
HLSM local storage reg Dreg_clr 16 Q
Dreg_ld 16
HLSM state action and
transition condition data Dctr_clr clr I clr I
computation Datapath Dctr_ld ld Dctr: reg(16) ld Dreg: reg(16)
components and connections Q Q
16
D
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11/6/2023
RTL Design
Laser-Based Distance Measurer—Step 2B: Connecting the Datapath to a Controller
L
B to laser
from button
Controller
from sensor
Dreg_clr S
Dreg_ld
Dctr_clr Datapath
Dctr_ld
D
to display
16
300 MHz Clock
RTL Design
Laser-Based Distance Measurer—Step 2C: Derive the Controller FSM
HLSM 1
16
Datapath
DistanceMeasurer Inputs: B (bit), S (bit) Outputs: L (bit), D (16 bits)
A B
Local storage: Dreg, Dctr (16 bits) Add1: add(16) 16 I
S Shr1: shiftR1(16)
B' 16 Q
S' Dreg_clr
Dreg_ld 16
Dctr_clr clr I clr I
S0 S1 S2 S3 S4 Dctr_ld ld Dctr: reg(16) ld Dreg: reg(16)
B S
Q Q
L := '0' Dctr := 0 L := '1' L := '0' Dreg := Dctr/2
16
Dreg := 0 Dctr := Dctr+1 // calculate D D
Controller Inputs: B, S Outputs: L, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_ld
FSM has same states,
transitions, and control
I/O B S
Achieve each HLSM
data operation using B S
datapath control S0 S1 S2 S3 S4
signals in FSM
L=0 L=0 L=1 L=0 L=0
Dreg_clr = 1 Dreg_clr = 0 Dreg_clr = 0 Dreg_clr = 0 Dreg_clr = 0
Dreg_ld = 0 Dreg_ld = 0 Dreg_ld = 0 Dreg_ld = 0 Dreg_ld = 1
Dctr_clr = 0 Dctr_clr = 1 Dctr_clr = 0 Dctr_clr = 0 Dctr_clr = 0
Dctr_ld = 0 Dctr_ld = 0 Dctr_ld = 0 Dctr_ld = 1 Dctr_ld = 0
(laser off) (clear count) (laser on) (laser off) (load Dreg with Dctr/2)
(clear Dreg) (count up) (stop counting)
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