FDB13AN06A0 / FDP13AN06A0

July 2003

FDB13AN06A0 / FDP13AN06A0
N-Channel PowerTrench® MOSFET
60V, 62A, 13.5mΩ
Features Applications
• r DS(ON) = 11.5mΩ (Typ.), VGS = 10V, ID = 62A • Motor / Body Load Control
• Qg(tot) = 22nC (Typ.), VGS = 10V • ABS Systems
• Low Miller Charge • Powertrain Management
• Low QRR Body Diode • Injection Systems
• UIS Capability (Single Pulse and Repetitive Pulse) • DC-DC converters and Off-line UPS
• Qualified to AEC Q101 • Distributed Power Architectures and VRMs

Formerly developmental type 82555 • Primary Switch for 12V and 24V systems

DRAIN D
(FLANGE) SOURCE GATE
DRAIN
GATE G
SOURCE DRAIN
(FLANGE)
TO-220AB TO-263AB S
FDP SERIES FDB SERIES

MOSFET Maximum Ratings TC = 25°C unless otherwise noted

Symbol Parameter Ratings Units
VDSS Drain to Source Voltage 60 V
VGS Gate to Source Voltage ±20 V
Drain Current
Continuous (TC = 25oC, VGS = 10V) 62 A
ID Continuous (TC = 100oC, VGS = 10V) 44 A
Continuous (TA = 25oC, VGS = 10V, R θJA = 43oC/W) 10.9 A
Pulsed Figure 4 A
E AS Single Pulse Avalanche Energy (Note 1) 56 mJ
Power dissipation 115 W
PD
Derate above 25oC 0.77 W/oC
o
TJ, TSTG Operating and Storage Temperature -55 to 175 C

Thermal Characteristics
o
RθJC Thermal Resistance Junction to Case TO-220,TO-263 1.3 C/W
o
RθJA Thermal Resistance Junction to Ambient TO-220,TO-263 (Note 2) 62 C/W
RθJA Thermal Resistance Junction to Ambient TO-263, 1in2 copper pad area 43 o
C/W

This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a
copy of the requirements, see AEC Q101 at: [Link]
Reliability data can be found at: [Link]
All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems
certification.

©2003 Fairchild Semiconductor Corporation FDB13AN06A0 / FDP13AN06A0 Rev. A1

 FDB13AN06A0 / FDP13AN06A0
Package Marking and Ordering Information
Device Marking Device Package Reel Size Tape Width Quantity
FDB13AN06A0 FDB13AN06A0 TO-263AB 330mm 24mm 800 units
FDP13AN06A0 FDP13AN06A0 TO-220AB Tube N/A 50 units

Electrical Characteristics TC = 25°C unless otherwise noted

Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics
B VDSS Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 60 - - V
VDS = 50V - - 1
IDSS Zero Gate Voltage Drain Current µA
VGS = 0V TC = 150oC - - 250
IGSS Gate to Source Leakage Current VGS = ±20V - - ±100 nA

On Characteristics
VGS(TH) Gate to Source Threshold Voltage VGS = VDS, ID = 250µA 2 - 4 V
ID = 62A, VGS = 10V - 0.0115 0.0135
ID = 31A, VGS = 6V - 0.022 0.034
rDS(ON) Drain to Source On Resistance Ω
ID = 62A, VGS = 10V,
- 0.026 0.030
TJ = 175oC

Dynamic Characteristics
CISS Input Capacitance - 1350 - pF
VDS = 25V, VGS = 0V,
COSS Output Capacitance - 260 - pF
f = 1MHz
CRSS Reverse Transfer Capacitance - 90 - pF
Qg(TOT) Total Gate Charge at 10V VGS = 0V to 10V 22 29 nC
Qg(TH) Threshold Gate Charge VGS = 0V to 2V VDD = 30V - 2.6 3.4 nC
Qgs Gate to Source Gate Charge ID = 62A - 8.5 - nC
Qgs2 Gate Charge Threshold to Plateau Ig = 1.0mA - 5.9 - nC
Qgd Gate to Drain “Miller” Charge - 6.4 - nC

Switching Characteristics (VGS = 10V)

tON Turn-On Time - - 158 ns
td(ON) Turn-On Delay Time - 9 - ns
tr Rise Time VDD = 30V, ID = 62A - 96 - ns
td(OFF) Turn-Off Delay Time VGS = 10V, RGS = 12Ω - 24 - ns
tf Fall Time - 26 - ns
tOFF Turn-Off Time - - 74 ns

Drain-Source Diode Characteristics

ISD = 62A - - 1.25 V
VSD Source to Drain Diode Voltage
ISD = 31A - - 1.0 V
trr Reverse Recovery Time ISD = 62A, dISD/dt = 100A/µs - - 25 ns
QRR Reverse Recovered Charge ISD = 62A, dISD/dt = 100A/µs - - 17 nC
Notes:
1: Starting TJ = 25°C, L = 45µH, I AS = 50A.
2: Pulse width = 100s.

©2003 Fairchild Semiconductor Corporation FDB13AN06A0 / FDP13AN06A0 Rev. A1

 FDB13AN06A0 / FDP13AN06A0
Typical Characteristics TC = 25°C unless otherwise noted

1.2 80

1.0
POWER DISSIPATION MULTIPLIER

ID, DRAIN CURRENT (A)

60
0.8

0.6 40

0.4

20
0.2

0 0
0 25 50 75 100 125 150 175 25 50 75 100 125 150 175
TC , CASE TEMPERATURE (oC) TC, CASE TEMPERATURE (oC)

Figure 1. Normalized Power Dissipation vs Figure 2. Maximum Continuous Drain Current vs

Ambient Temperature Case Temperature

2
DUTY CYCLE - DESCENDING ORDER
1 0.5
0.2
0.1
0.05
THERMAL IMPEDANCE

0.02
ZθJC, NORMALIZED

0.01
PDM
0.1

t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
SINGLE PULSE PEAK TJ = PDM x ZθJC x RθJC + TC
0.01
10-5 10-4 10-3 10-2 10-1 100 101
t, RECTANGULAR PULSE DURATION (s)

Figure 3. Normalized Maximum Transient Thermal Impedance

800
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
TRANSCONDUCTANCE
MAY LIMIT CURRENT CURRENT AS FOLLOWS:
IDM, PEAK CURRENT (A)

IN THIS REGION
I = I25 175 - TC

VGS = 10V 150

100

30

10-5 10-4 10-3 10-2 10-1 100 101

t, PULSE WIDTH (s)

Figure 4. Peak Current Capability

©2003 Fairchild Semiconductor Corporation FDB13AN06A0 / FDP13AN06A0 Rev. A1

 FDB13AN06A0 / FDP13AN06A0
Typical Characteristics TC = 25°C unless otherwise noted

1000 100
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
10µs If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]

IAS, AVALANCHE CURRENT (A)

ID, DRAIN CURRENT (A)

100
100µs STARTING TJ = 25o C

1ms 10
10 OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON) STARTING TJ = 150oC

1
SINGLE PULSE 10ms
TJ = MAX RATED DC
TC = 25oC

0.1 1
1 10 100 0.01 0.1 1 10 100
VDS, DRAIN TO SOURCE VOLTAGE (V) tAV, TIME IN AVALANCHE (ms)

Figure 5. Forward Bias Safe Operating Area NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching
Capability

100 100
PULSE DURATION = 80µs TC = 25oC VGS = 20V
DUTY CYCLE = 0.5% MAX
VDD = 15V
80 80
ID , DRAIN CURRENT (A)

VGS = 10V
ID, DRAIN CURRENT (A)

60 60
VGS = 6V
TJ = 175 oC
40 40
TJ = 25oC TJ = -55oC PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
20 20

VGS = 5V
0 0
3 4 5 6 7 0 0.5 1.0 1.5 2.0
VGS , GATE TO SOURCE VOLTAGE (V) VDS , DRAIN TO SOURCE VOLTAGE (V)

Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics

30 2.5
PULSE DURATION = 80µs PULSE DURATION = 80µs
DRAIN TO SOURCE ON RESISTANCE(mΩ)

DUTY CYCLE = 0.5% MAX DUTY CYCLE = 0.5% MAX

NORMALIZED DRAIN TO SOURCE

25 2.0
ON RESISTANCE

VGS = 6V

20 1.5

15
1.0
VGS = 10V

VGS = 10V, ID =62A

10
0.5
0 10 20 30 40 50 60 70 -80 -40 0 40 80 120 160 200
ID, DRAIN CURRENT (A) TJ, JUNCTION TEMPERATURE (oC)

Figure 9. Drain to Source On Resistance vs Drain Figure 10. Normalized Drain to Source On
Current Resistance vs Junction Temperature

©2003 Fairchild Semiconductor Corporation FDB13AN06A0 / FDP13AN06A0 Rev. A1

 FDB13AN06A0 / FDP13AN06A0
Typical Characteristics TC = 25°C unless otherwise noted

1.4 1.2
VGS = VDS, I D = 250µA ID = 250µA

NORMALIZED DRAIN TO SOURCE

1.2

BREAKDOWN VOLTAGE
THRESHOLD VOLTAGE
NORMALIZED GATE

1.1
1.0

0.8
1.0

0.6

0.4
-80 -40 0 40 80 120 160 200 0.9
-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC) TJ , JUNCTION TEMPERATURE (o C)

Figure 11. Normalized Gate Threshold Voltage vs Figure 12. Normalized Drain to Source
Junction Temperature Breakdown Voltage vs Junction Temperature

3000
10
VDD = 30V
VGS , GATE TO SOURCE VOLTAGE (V)

8
1000 CISS = CGS + C GD
C, CAPACITANCE (pF)

COSS ≅ C DS + C GD
6

CRSS = CGD 4

WAVEFORMS IN
100 2 DESCENDING ORDER:
ID = 62A
ID = 31A
VGS = 0V, f = 1MHz
40 0
0.1 1 10 60 0 5 10 15 20 25
VDS , DRAIN TO SOURCE VOLTAGE (V) Qg , GATE CHARGE (nC)

Figure 13. Capacitance vs Drain to Source Figure 14. Gate Charge Waveforms for Constant
Voltage Gate Current

©2003 Fairchild Semiconductor Corporation FDB13AN06A0 / FDP13AN06A0 Rev. A1

 FDB13AN06A0 / FDP13AN06A0
Test Circuits and Waveforms

VDS
BVDSS

L tP
VDS

VARY tP TO OBTAIN IAS

+
VDD
REQUIRED PEAK IAS RG
VDD
VGS -
DUT

tP
0V IAS
0.01Ω 0

tAV

Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms

VDS
VDD Qg(TOT)

L VDS
VGS
VGS = 10V
VGS
+

VDD Qgs2
-

DUT
VGS = 2V
Ig(REF)
0
Qg(TH)
Qgs Qgd

Ig(REF)
0

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms

VDS tON tOFF

td(ON) td(OFF)

RL tr tf
VDS
90% 90%

+
VGS
VDD
10% 10%
- 0

DUT 90%
RGS
VGS 50% 50%
PULSE WIDTH
VGS 10%
0

Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms

©2003 Fairchild Semiconductor Corporation FDB13AN06A0 / FDP13AN06A0 Rev. A1

 FDB13AN06A0 / FDP13AN06A0
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM , and the 80
thermal resistance of the heat dissipating path determines RθJA = 26.51+ 19.84/(0.262+Area) EQ.2
the maximum allowable device power dissipation, PDM , in an
application. Therefore the application’s ambient RθJA = 26.51+ 128/(1.69+Area) EQ.3

temperature, TA (oC), and thermal resistance RθJA (oC/W)

60
must be reviewed to ensure that TJM is never exceeded.

RθJA (o C/W)
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.

(T –T )
JM A (EQ. 1) 40
P D M = -----------------------------
R θ JA

In using surface mount devices such as the TO-263

package, the environment in which it is applied will have a 20
significant influence on the part’s current and maximum 0.1 1 10
power dissipation ratings. Precise determination of P DM is (0.645) (6.45) (64.5)
complex and influenced by many factors: AREA, TOP COPPER AREA in2 (cm2 )
Figure 21. Thermal Resistance vs Mounting
1. Mounting pad area onto which the device is attached and Pad Area
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.

Thermal resistances corresponding to other copper areas

can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches square and equation 3 is for area in centimeters
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.

19.84
R = 26.51 + ------------------------------------- (EQ. 2)
θ JA ( 0.262 + Area )
Area in Inches Squared

128
R = 26.51 + ---------------------------------- (EQ. 3)
θ JA ( 1.69 + Area )
Area in Centimeters Squared

©2003 Fairchild Semiconductor Corporation FDB13AN06A0 / FDP13AN06A0 Rev. A1

 FDB13AN06A0 / FDP13AN06A0
PSPICE Electrical Model
.SUBCKT FDB13AN06A0 2 1 3 ; rev August 2002
Ca 12 8 5.1e-10
Cb 15 14 5.1e-10 LDRAIN
Cin 6 8 1.3e-9 DPLCAP 5 DRAIN
2
10
Dbody 7 5 DbodyMOD RLDRAIN
RSLC1
Dbreak 5 11 DbreakMOD DBREAK
51
Dplcap 10 5 DplcapMOD RSLC2
+
5
51 ESLC 11
Ebreak 11 7 17 18 65.40 -
Eds 14 8 5 8 1 50 +
-
Egs 13 8 6 8 1 RDRAIN 17 DBODY
6 EBREAK 18
Esg 6 10 6 8 1 ESG 8
EVTHRES -
Evthres 6 21 19 8 1 + 16
+ 19 - 21
Evtemp 20 6 18 22 1 LGATE EVTEMP MWEAK
8
GATE RGATE + 18 - 6
It 8 17 1 1 22 MMED
9 20
RLGATE MSTRO
Lgate 1 9 6.9e-9 LSOURCE
CIN SOURCE
Ldrain 2 5 1.0e-9 8 7 3
Lsource 3 7 2.91e-9
RSOURCE
RLSOURCE
RLgate 1 9 69 S1A S2A
RLdrain 2 5 10 12 RBREAK
13 14 15
17 18
RLsource 3 7 29.1 8 13
S1B S2B RVTEMP
Mmed 16 6 8 8 MmedMOD 13 CB 19
Mstro 16 6 8 8 MstroMOD CA
14 IT -
+ +
Mweak 16 21 8 8 MweakMOD 6 5 VBAT
EGS EDS +
8 8
Rbreak 17 18 RbreakMOD 1 - - 8
Rdrain 50 16 RdrainMOD 3.0e-3 22
Rgate 9 20 3.77 RVTHRES
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 5.5e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD

Vbat 22 19 DC 1

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*160),6))}

.MODEL DbodyMOD D (IS=1.5E-11 N=1.08 RS=3.3e-3 TRS1=2.2e-3 TRS2=2.5e-9

+ CJO=0.9e-9 M=5.1e-1 TT=1e-9 XTI=3.9)
.MODEL DbreakMOD D (RS=1.5e-1 TRS1=1e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=4.1e-10 IS=1e-30 N=10 M=0.45)

.MODEL MmedMOD NMOS (VTO=3.5 KP=6 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=3.77)
.MODEL MstroMOD NMOS (VTO=4.3 KP=50 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=2.88 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=3.77e+1 RS=0.1)

.MODEL RbreakMOD RES (TC1=9e-4 TC2=-5e-7)

.MODEL RdrainMOD RES (TC1=1.5e-2 TC2=4e-5)
.MODEL RSLCMOD RES (TC1=1.8e-3 TC2=1.7e-5)
.MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-5.3e-3 TC2=-1.0e-5)
.MODEL RvtempMOD RES (TC1=-2.5e-3 TC2=1e-6)

.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-5 VOFF=-2)

.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-5)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=0.5)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.5 VOFF=-1.5)

.ENDS
*Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.

©2003 Fairchild Semiconductor Corporation FDB13AN06A0 / FDP13AN06A0 Rev. A1

 FDB13AN06A0 / FDP13AN06A0
SABER Electrical Model
rev August 2002
template FDB13AN06A0 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=1.5e-11,nl=1.08,rs=3.3e-3,trs1=2.2e-3,trs2=2.5e-9,cjo=0.9e-9,m=5.1e-1,tt=1e-9,xti=3.9)
dp..model dbreakmod = (rs=1.5e-1,trs1=1e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=4.1e-10,isl=10e-30,nl=10,m=0.45)
m..model mmedmod = (type=_n,vto=3.5,kp=6,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=4.3,kp=50,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=2.88,kp=0.05,is=1e-30, tox=1,rs=0.1)
LDRAIN
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-5,voff=-2) DPLCAP 5 DRAIN
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2,voff=-5) 2
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1.5,voff=0.5) 10
RLDRAIN
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.5,voff=-1.5) RSLC1
[Link] n12 n8 = 5.1e-10 51
RSLC2
[Link] n15 n14 = 5.1e-10
[Link] n6 n8 = 1.3e-9 ISCL

50 DBREAK
[Link] n7 n5 = model=dbodymod -
6 RDRAIN
[Link] n5 n11 = model=dbreakmod ESG 11
8 DBODY
[Link] n10 n5 = model=dplcapmod + EVTHRES 16
+ 19 - 21
LGATE EVTEMP MWEAK
[Link] n11 n7 n17 n18 = 65.40 8
GATE RGATE + 18 - 6
[Link] n14 n8 n5 n8 = 1 1 MMED EBREAK
9 22 +
[Link] n13 n8 n6 n8 = 1 20
MSTRO
RLGATE 17
[Link] n6 n10 n6 n8 = 1 18 LSOURCE
[Link] n6 n21 n19 n8 = 1 CIN - SOURCE
8 7
[Link] n20 n6 n18 n22 = 1 3
RSOURCE
RLSOURCE
[Link] n8 n17 = 1
S1A S2A
12 RBREAK
13 14 15
[Link] n1 n9 = 6.9e-9 17 18
8 13
[Link] n2 n5 = 1.0e-9
[Link] n3 n7 = 2.91e-9 S1B S2B RVTEMP
13 CB 19
CA
14 IT -
[Link] n1 n9 = 69 + +
[Link] n2 n5 = 10 6 5 VBAT
EGS 8 EDS 8 +
[Link] n3 n7 = 29.1
- - 8
22
[Link] n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u RVTHRES
[Link] n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
[Link] n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u

[Link] n17 n18 = 1, tc1=9e-4,tc2=-5e-7

[Link] n50 n16 = 3.0e-3, tc1=1.5e-2,tc2=4e-5
[Link] n9 n20 = 3.77
res.rslc1 n5 n51 = 1e-6, tc1=1.8e-3,tc2=1.7e-5
res.rslc2 n5 n50 = 1e3
[Link] n8 n7 = 5.5e-3, tc1=1e-3,tc2=1e-6
[Link] n22 n8 = 1, tc1=-5.3e-3,tc2=-1.0e-5
[Link] n18 n19 = 1, tc1=-2.5e-3,tc2=1e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

[Link] n22 n19 = dc=1

equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/160))** 6))
}

©2003 Fairchild Semiconductor Corporation FDB13AN06A0 / FDP13AN06A0 Rev. A1

 FDB13AN06A0 / FDP13AN06A0
PSPICE Thermal Model JUNCTION
th
REV 23 March 2002

FDB13AN06A0T
CTHERM1 TH 6 9.7e-4
CTHERM2 6 5 6.2e-3
CTHERM3 5 4 4.6e-3
CTHERM4 4 3 4.9e-3 RTHERM1 CTHERM1
CTHERM5 3 2 8e-3
CTHERM6 2 TL 4.2e-2

RTHERM1 TH 6 5.24e-2 6
RTHERM2 6 5 10.08e-2
RTHERM3 5 4 4.28e-1
RTHERM4 4 3 1.8e-1
RTHERM2 CTHERM2
RTHERM5 3 2 1.9e-1
RTHERM6 2 TL 2.1e-1

SABER Thermal Model 5

SABER thermal model FDB14AN06A0T

template thermal_model th tl
thermal_c th, tl RTHERM3 CTHERM3
{
ctherm.ctherm1 th 6 =9.7e-4
ctherm.ctherm2 6 5 =6.2e-3
4
ctherm.ctherm3 5 4 =4.6e-3
ctherm.ctherm4 4 3 =4.9e-3
ctherm.ctherm5 3 2 =8e-3
ctherm.ctherm6 2 tl =4.2e-2 RTHERM4 CTHERM4

rtherm.rtherm1 th 6 =5.24e-2
rtherm.rtherm2 6 5 =10.08e-2
rtherm.rtherm3 5 4 =4.28e-1 3
rtherm.rtherm4 4 3 =1.8e-1
rtherm.rtherm5 3 2 =1.9e-1
rtherm.rtherm6 2 tl =2.1e-1
RTHERM5 CTHERM5
}

RTHERM6 CTHERM6

tl CASE

©2003 Fairchild Semiconductor Corporation FDB13AN06A0 / FDP13AN06A0 Rev. A1

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DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER

NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant into support device or system whose failure to perform can
the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can be effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or This datasheet contains the design specifications for
In Design product development. Specifications may change in
any manner without notice.

Preliminary First Production This datasheet contains preliminary data, and

supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

Obsolete Not In Production This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.

Rev. I3